790 lines
24 KiB
C++
790 lines
24 KiB
C++
/*
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* Copyright (c) 2021, RPTU Kaiserslautern-Landau
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors:
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* Derek Christ
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* Marco Mörz
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*/
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#include <DRAMSys/config/DRAMSysConfiguration.h>
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#include <DRAMSys/config/MemSpec.h>
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#include <DRAMUtils/util/json.h>
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#include <DRAMUtils/memspec/MemSpec.h>
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#include <DRAMUtils/memspec/standards/MemSpecDDR5.h>
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#include <fstream>
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#include <gtest/gtest.h>
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#include <iostream>
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#include <optional>
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using namespace DRAMSys::Config;
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class ConfigurationTest : public ::testing::Test
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{
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protected:
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ConfigurationTest() :
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memSpec(createMemSpec()),
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tracePlayer(createTracePlayer()),
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traceGeneratorOneState(createTraceGeneratorOneState()),
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traceGeneratorMultipleStates(createTraceGeneratorMultipleStates()),
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traceHammer(createTraceHammer())
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{
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}
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static DRAMUtils::MemSpec::MemSpecVariant createMemSpec();
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static DRAMSys::Config::TracePlayer createTracePlayer();
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static DRAMSys::Config::TrafficGenerator createTraceGeneratorOneState();
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static DRAMSys::Config::TrafficGeneratorStateMachine createTraceGeneratorMultipleStates();
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static DRAMSys::Config::RowHammer createTraceHammer();
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static std::vector<DRAMSys::Config::AddressMapping::BitEntry>
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addressMapBitVector(std::initializer_list<std::vector<unsigned int>> bits)
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{
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auto result = std::vector<DRAMSys::Config::AddressMapping::BitEntry>();
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for (const auto& bit : bits)
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{
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result.push_back(DRAMSys::Config::AddressMapping::BitEntry({bit.begin(), bit.end()}));
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}
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return result;
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};
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static std::vector<DRAMSys::Config::AddressMapping::BitEntry>
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addressMapBitVector(std::vector<unsigned int> bits)
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{
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return {bits.begin(), bits.end()};
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};
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DRAMSys::Config::AddressMapping addressMapping{
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addressMapBitVector({0, 1}),
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addressMapBitVector({2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12}),
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addressMapBitVector({16}),
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addressMapBitVector({13, 14, 15}),
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addressMapBitVector({17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}),
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addressMapBitVector({33}),
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std::nullopt,
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std::nullopt,
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std::nullopt};
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DRAMSys::Config::McConfig mcConfig{PagePolicyType::Open,
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SchedulerType::FrFcfs,
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0,
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0,
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SchedulerBufferType::Bankwise,
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8,
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std::nullopt,
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std::nullopt,
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CmdMuxType::Oldest,
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RespQueueType::Fifo,
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RefreshPolicyType::AllBank,
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0,
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0,
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PowerDownPolicyType::NoPowerDown,
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ArbiterType::Simple,
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128,
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std::nullopt,
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std::nullopt,
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std::nullopt,
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std::nullopt,
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std::nullopt,
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std::nullopt,
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std::nullopt,
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std::nullopt,
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std::nullopt};
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DRAMSys::Config::SimConfig simConfig{0,
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false,
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true,
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false,
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false,
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false,
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{"ddr5"},
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true,
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DRAMSys::Config::StoreModeType::NoStorage,
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false,
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false,
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1000,
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1e-3,
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std::nullopt};
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DRAMUtils::MemSpec::MemSpecVariant memSpec;
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DRAMSys::Config::TracePlayer tracePlayer;
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DRAMSys::Config::TrafficGenerator traceGeneratorOneState;
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DRAMSys::Config::TrafficGeneratorStateMachine traceGeneratorMultipleStates;
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DRAMSys::Config::RowHammer traceHammer;
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std::vector<DRAMSys::Config::Initiator> traceSetup{
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{
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DRAMSys::Config::Initiator{tracePlayer},
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DRAMSys::Config::Initiator{traceGeneratorOneState},
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DRAMSys::Config::Initiator{traceGeneratorMultipleStates},
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DRAMSys::Config::Initiator{traceHammer}
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}
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};
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DRAMSys::Config::Configuration configuration{
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addressMapping, mcConfig, memSpec, simConfig, "std::string_simulationId", traceSetup};
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};
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DRAMUtils::MemSpec::MemSpecVariant ConfigurationTest::createMemSpec()
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{
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DRAMUtils::MemSpec::MemArchitectureSpecTypeDDR5 memArchitectureSpec
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{
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2, // nbrOfChannels
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8, // nbrOfDevices
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1, // nbrOfRanks
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1, // nbrOfDIMMRanks
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1, // nbrOfPhysicalRanks
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1, // nbrOfLogicalRanks
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16, // nbrOfBanks
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8, // nbrOfBankGroups
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65536, // nbrOfRows
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2048, // nbrOfColumns
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16, // burstLength
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2, // dataRate
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4, // width
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DRAMUtils::MemSpec::RefModeTypeDDR5::REF_MODE_1, // RefMode
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16, // maxBurstLength
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1, // cmdMode
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32, // RAAIMT
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96, // RAAMMT
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1 // RAADEC
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};
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DRAMUtils::MemSpec::MemTimingSpecTypeDDR5 memTimingSpec
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{
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625, // tCK
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52, // RAS
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22, // RCD
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12, // RTP
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20, // WL
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48, // WR
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22, // RP
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2, // PPD
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22, // RL
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1, // RPRE
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0, // RPST
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0, // RDDQS
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2, // WPRE
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0, // WPST
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8, // CCD_L_slr
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32, // CCD_L_WR_slr
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16, // CCD_L_WR2_slr
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8, // CCD_M_slr
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32, // CCD_M_WR_slr
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8, // CCD_S_slr
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8, // CCD_S_WR_slr
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0, // CCD_dlr
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0, // CCD_WR_dlr
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0, // CCD_WR_dpr
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8, // RRD_L_slr
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8, // RRD_S_slr
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0, // RRD_dlr
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32, // FAW_slr
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0, // FAW_dlr
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16, // WTR_L
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16, // WTR_M
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4, // WTR_S
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312, // RFC1_slr
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208, // RFC2_slr
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0, // RFC1_dlr
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0, // RFC2_dlr
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0, // RFC1_dpr
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0, // RFC2_dpr
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184, // RFCsb_slr
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0, // RFCsb_dlr
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6240, // REFI1
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3120, // REFI2
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1560, // REFISB
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48, // REFSBRD_slr
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0, // REFSBRD_dlr
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2, // RTRS
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8, // CPDED
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12, // PD
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12, // XP
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2, // ACTPDEN
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2, // PRPDEN
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2 // REFPDEN
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};
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DRAMUtils::MemSpec::MemImpedanceSpecTypeDDR5 memImpedanceSpec {
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true, // ck_termination
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1e6, // ck_R_eq
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1e-12, // ck_dyn_E
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true, // ca_termination
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1e6, // ca_R_eq
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1e-12, // ca_dyn_E
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true, // rdq_termination
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1e6, // rdq_R_eq
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1e-12, // rdq_dyn_E
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true, // wdq_termination
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1e6, // wdq_R_eq
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1e-12, // wdq_dyn_E
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true, // rdqs_termination
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1e6, // rdqs_R_eq
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1e-12, // rdqs_dyn_E
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true, // wdqs_termination
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1e6, // wdqs_R_eq
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1e-12 // wdqs_dyn_E
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};
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DRAMUtils::MemSpec::MemPowerSpecTypeDDR5 memPowerSpec {
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0, // vdd
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0, // idd0
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0, // idd2n
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0, // idd3n
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0, // idd4r
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0, // idd4w
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0, // idd5c
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0, // idd6n
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0, // idd2p
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0, // idd3p
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0, // vpp
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0, // ipp0
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0, // ipp2n
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0, // ipp3n
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0, // ipp4r
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0, // ipp4w
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0, // ipp5c
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0, // ipp6n
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0, // ipp2p
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0, // ipp3p
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0, // idd5b // RefModeTypeDDR5::REF_MODE_1
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0, // idd5f // RefModeTypeDDR5::REF_MODE_2
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0, // ipp5b // RefModeTypeDDR5::REF_MODE_1
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0, // ipp5f // RefModeTypeDDR5::REF_MODE_2
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0, // vddq
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0, // iBeta_vdd
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0 // iBeta_vpp
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};
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DRAMUtils::MemSpec::MemSpecVariant variant;
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DRAMUtils::MemSpec::MemSpecDDR5 memspec
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{
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DRAMUtils::MemSpec::BaseMemSpec{}, // base
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"JEDEC_2x8x2Gbx4_DDR5-3200A", // memoryId
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memArchitectureSpec, // memarchitecturespec
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memPowerSpec, // mempowerspec
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memTimingSpec, // memtimingspec
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std::nullopt, // bankwisespec
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memImpedanceSpec, // memimpedancespec
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std::nullopt // dataratespec
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};
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variant.setVariant(memspec);
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return variant;
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}
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DRAMSys::Config::TracePlayer ConfigurationTest::createTracePlayer()
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{
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DRAMSys::Config::TracePlayer player;
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player.clkMhz = 100;
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player.dataLength = 64;
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player.name = "mytrace.stl";
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return player;
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}
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DRAMSys::Config::TrafficGenerator ConfigurationTest::createTraceGeneratorOneState()
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{
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DRAMSys::Config::TrafficGenerator gen;
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gen.clkMhz = 100;
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gen.dataLength = 64;
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gen.name = "MyTestGen";
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gen.numRequests = 1000;
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gen.rwRatio = 0.5;
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gen.addressDistribution = DRAMSys::Config::AddressDistribution::Random;
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gen.addressIncrement = {};
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gen.minAddress = {};
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gen.maxAddress = {};
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return gen;
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}
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DRAMSys::Config::TrafficGeneratorStateMachine
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ConfigurationTest::createTraceGeneratorMultipleStates()
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{
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DRAMSys::Config::TrafficGeneratorStateMachine gen;
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gen.clkMhz = 100;
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gen.dataLength = 64;
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gen.name = "MyTestGen";
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gen.maxPendingReadRequests = 8;
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DRAMSys::Config::TrafficGeneratorActiveState state0;
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state0.numRequests = 1000;
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state0.rwRatio = 0.5;
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state0.addressDistribution = DRAMSys::Config::AddressDistribution::Sequential;
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state0.addressIncrement = 256;
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state0.minAddress = {};
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state0.maxAddress = 1024;
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state0.id = 0;
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DRAMSys::Config::TrafficGeneratorActiveState state1;
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state1.numRequests = 100;
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state1.rwRatio = 0.75;
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state1.addressDistribution = DRAMSys::Config::AddressDistribution::Sequential;
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state1.addressIncrement = 512;
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state1.minAddress = 1024;
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state1.maxAddress = 2048;
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state1.id = 1;
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gen.states.push_back(state0);
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gen.states.push_back(state1);
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DRAMSys::Config::TrafficGeneratorStateTransition transistion0{0, 1, 1.0};
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gen.transitions.push_back(transistion0);
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return gen;
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}
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DRAMSys::Config::RowHammer ConfigurationTest::createTraceHammer()
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{
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DRAMSys::Config::RowHammer hammer;
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hammer.clkMhz = 100;
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hammer.dataLength = 64;
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hammer.name = "MyTestHammer";
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hammer.numRequests = 4000;
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hammer.rowIncrement = 2097152;
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return hammer;
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}
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TEST_F(ConfigurationTest, ToJson)
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{
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json_t config_json;
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config_json["simulation"] = configuration;
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std::ifstream file("reference.json");
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ASSERT_TRUE(file.is_open());
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json_t reference_json = json_t::parse(file);
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std::cout << reference_json.dump(4) << std::endl;
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EXPECT_EQ(config_json, reference_json);
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}
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TEST(Configuration, FromToJson)
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{
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std::ifstream file("reference.json");
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ASSERT_TRUE(file.is_open());
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json_t reference_json = json_t::parse(file);
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DRAMSys::Config::Configuration reference_configuration =
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reference_json["simulation"].get<DRAMSys::Config::Configuration>();
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json_t new_json;
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new_json["simulation"] = reference_configuration;
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EXPECT_EQ(new_json, reference_json);
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}
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TEST_F(ConfigurationTest, DumpConfiguration)
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{
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// This test does not test anything. It just dumps the configuration to stdout for manual
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// inspection.
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json_t json;
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json["simulation"] = configuration;
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std::cout << json.dump(4) << std::endl;
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}
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TEST(Configuration, FromPath)
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{
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// Test should not throw exceptions
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Configuration config = from_path("reference.json");
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}
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TEST(RefreshPolicyType, BackwardsCompatibility)
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{
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// Deserializing
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EXPECT_EQ(json_t("Rankwise").get<RefreshPolicyType>(), RefreshPolicyType::AllBank);
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EXPECT_EQ(json_t("Bankwise").get<RefreshPolicyType>(), RefreshPolicyType::PerBank);
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EXPECT_EQ(json_t("Groupwise").get<RefreshPolicyType>(), RefreshPolicyType::SameBank);
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// Serializing
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EXPECT_EQ(json_t(RefreshPolicyType::AllBank).get<std::string>(), "AllBank");
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EXPECT_EQ(json_t(RefreshPolicyType::PerBank).get<std::string>(), "PerBank");
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EXPECT_EQ(json_t(RefreshPolicyType::SameBank).get<std::string>(), "SameBank");
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}
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TEST_F(ConfigurationTest, SimConfig)
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{
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std::string_view simconfig_string = R"(
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{
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"simconfig": {
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"AddressOffset": 0,
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"CheckTLM2Protocol": false,
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"DatabaseRecording": true,
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"Debug": false,
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"EnableWindowing": false,
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"PowerAnalysis": false,
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"SimulationName": "ddr5",
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"SimulationProgressBar": true,
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"StoreMode": "NoStorage",
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"ThermalSimulation": false,
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"UseMalloc": false,
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"WindowSize": 1000,
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"SimulationTime": 1e-3
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}
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}
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)";
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json_t simconfig_reference = json_t::parse(simconfig_string);
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json_t simconfig_test;
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simconfig_test[SimConfig::KEY] = simConfig;
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EXPECT_EQ(simconfig_test, simconfig_reference);
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}
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TEST_F(ConfigurationTest, McConfig)
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{
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std::string_view mcconfig_string = R"(
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{
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"mcconfig": {
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"Arbiter": "Simple",
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"CmdMux": "Oldest",
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"HighWatermark": 0,
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"LowWatermark": 0,
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"MaxActiveTransactions": 128,
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"PagePolicy": "Open",
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"PowerDownPolicy": "NoPowerDown",
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"RefreshMaxPostponed": 0,
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"RefreshMaxPulledin": 0,
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"RefreshPolicy": "AllBank",
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"RequestBufferSize": 8,
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"RespQueue": "Fifo",
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"Scheduler": "FrFcfs",
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"SchedulerBuffer": "Bankwise"
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}
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}
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)";
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json_t mcconfig_reference = json_t::parse(mcconfig_string);
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json_t mcconfig_test;
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mcconfig_test[McConfig::KEY] = mcConfig;
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EXPECT_EQ(mcconfig_test, mcconfig_reference);
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}
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TEST_F(ConfigurationTest, MemSpec)
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{
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std::string_view memspec_string = R"(
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{
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"memspec": {
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"memarchitecturespec": {
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"RAADEC": 1,
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"RAAIMT": 32,
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"RAAMMT": 96,
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"burstLength": 16,
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"cmdMode": 1,
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"dataRate": 2,
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"maxBurstLength": 16,
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"nbrOfBankGroups": 8,
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"nbrOfBanks": 16,
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"nbrOfChannels": 2,
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"nbrOfColumns": 2048,
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"nbrOfDIMMRanks": 1,
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"nbrOfDevices": 8,
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"nbrOfLogicalRanks": 1,
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"nbrOfPhysicalRanks": 1,
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"nbrOfRanks": 1,
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"nbrOfRows": 65536,
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"RefMode": 1,
|
|
"width": 4
|
|
},
|
|
"memimpedancespec": {
|
|
"ck_termination": true,
|
|
"ck_R_eq": 1e6,
|
|
"ck_dyn_E": 1e-12,
|
|
|
|
"ca_termination": true,
|
|
"ca_R_eq": 1e6,
|
|
"ca_dyn_E": 1e-12,
|
|
|
|
"rdq_termination": true,
|
|
"rdq_R_eq": 1e6,
|
|
"rdq_dyn_E": 1e-12,
|
|
"wdq_termination": true,
|
|
"wdq_R_eq": 1e6,
|
|
"wdq_dyn_E": 1e-12,
|
|
|
|
"wdqs_termination": true,
|
|
"wdqs_R_eq": 1e6,
|
|
"wdqs_dyn_E": 1e-12,
|
|
"rdqs_termination": true,
|
|
"rdqs_R_eq": 1e6,
|
|
"rdqs_dyn_E": 1e-12
|
|
},
|
|
"memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A",
|
|
"memoryType": "DDR5",
|
|
"mempowerspec": {
|
|
"vdd": 0.0,
|
|
"idd0": 0.0,
|
|
"idd2n": 0.0,
|
|
"idd3n": 0.0,
|
|
"idd4r": 0.0,
|
|
"idd4w": 0.0,
|
|
"idd5c": 0.0,
|
|
"idd6n": 0.0,
|
|
"idd2p": 0.0,
|
|
"idd3p": 0.0,
|
|
"vpp": 0.0,
|
|
"ipp0": 0.0,
|
|
"ipp2n": 0.0,
|
|
"ipp3n": 0.0,
|
|
"ipp4r": 0.0,
|
|
"ipp4w": 0.0,
|
|
"ipp5c": 0.0,
|
|
"ipp6n": 0.0,
|
|
"ipp2p": 0.0,
|
|
"ipp3p": 0.0,
|
|
"idd5b": 0.0,
|
|
"idd5f": 0.0,
|
|
"ipp5b": 0.0,
|
|
"ipp5f": 0.0,
|
|
"vddq": 0.0,
|
|
"iBeta_vdd": 0.0,
|
|
"iBeta_vpp": 0.0
|
|
},
|
|
"memtimingspec": {
|
|
"RCD": 22,
|
|
"PPD": 2,
|
|
"RP": 22,
|
|
"RAS": 52,
|
|
"RL": 22,
|
|
"RTP": 12,
|
|
"RPRE": 1,
|
|
"RPST": 0,
|
|
"RDDQS": 0,
|
|
"WL": 20,
|
|
"WPRE": 2,
|
|
"WPST": 0,
|
|
"WR": 48,
|
|
"CCD_L_slr": 8,
|
|
"CCD_L_WR_slr": 32,
|
|
"CCD_L_WR2_slr": 16,
|
|
"CCD_M_slr": 8,
|
|
"CCD_M_WR_slr": 32,
|
|
"CCD_S_slr": 8,
|
|
"CCD_S_WR_slr": 8,
|
|
"CCD_dlr": 0,
|
|
"CCD_WR_dlr": 0,
|
|
"CCD_WR_dpr": 0,
|
|
"RRD_L_slr": 8,
|
|
"RRD_S_slr": 8,
|
|
"RRD_dlr": 0,
|
|
"FAW_slr": 32,
|
|
"FAW_dlr": 0,
|
|
"WTR_L": 16,
|
|
"WTR_M": 16,
|
|
"WTR_S": 4,
|
|
"RFC1_slr": 312,
|
|
"RFC2_slr": 208,
|
|
"RFC1_dlr": 0,
|
|
"RFC2_dlr": 0,
|
|
"RFC1_dpr": 0,
|
|
"RFC2_dpr": 0,
|
|
"RFCsb_slr": 184,
|
|
"RFCsb_dlr": 0,
|
|
"REFI1": 6240,
|
|
"REFI2": 3120,
|
|
"REFISB": 1560,
|
|
"REFSBRD_slr": 48,
|
|
"REFSBRD_dlr": 0,
|
|
"RTRS": 2,
|
|
"CPDED": 8,
|
|
"PD": 12,
|
|
"XP": 12,
|
|
"ACTPDEN": 2,
|
|
"PRPDEN": 2,
|
|
"REFPDEN": 2,
|
|
"tCK": 625
|
|
}
|
|
}
|
|
}
|
|
)";
|
|
|
|
json_t memspec_reference = json_t::parse(memspec_string);
|
|
json_t memspec_test;
|
|
memspec_test[MemSpecConstants::KEY] = memSpec;
|
|
|
|
EXPECT_EQ(memspec_test, memspec_reference);
|
|
}
|
|
|
|
TEST_F(ConfigurationTest, AddressMapping)
|
|
{
|
|
std::string_view addressmapping_string = R"(
|
|
{
|
|
"addressmapping": {
|
|
"BANKGROUP_BIT": [
|
|
17,
|
|
18,
|
|
19,
|
|
20,
|
|
21,
|
|
22,
|
|
23,
|
|
24,
|
|
25,
|
|
26,
|
|
27,
|
|
28,
|
|
29,
|
|
30,
|
|
31,
|
|
32
|
|
],
|
|
"BANK_BIT": [
|
|
13,
|
|
14,
|
|
15
|
|
],
|
|
"BYTE_BIT": [
|
|
0,
|
|
1
|
|
],
|
|
"COLUMN_BIT": [
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12
|
|
],
|
|
"RANK_BIT": [
|
|
33
|
|
],
|
|
"ROW_BIT": [
|
|
16
|
|
]
|
|
}
|
|
}
|
|
)";
|
|
|
|
json_t addressmapping_reference = json_t::parse(addressmapping_string);
|
|
json_t addressmapping_test;
|
|
addressmapping_test[AddressMapping::KEY] = addressMapping;
|
|
|
|
EXPECT_EQ(addressmapping_test, addressmapping_reference);
|
|
}
|
|
|
|
TEST_F(ConfigurationTest, TraceSetup)
|
|
{
|
|
std::string_view tracesetup_string = R"(
|
|
{
|
|
"tracesetup": [
|
|
{
|
|
"type": "player",
|
|
"clkMhz": 100,
|
|
"dataLength": 64,
|
|
"name": "mytrace.stl"
|
|
},
|
|
{
|
|
"type": "generator",
|
|
"addressDistribution": "random",
|
|
"clkMhz": 100,
|
|
"dataLength": 64,
|
|
"name": "MyTestGen",
|
|
"numRequests": 1000,
|
|
"rwRatio": 0.5
|
|
},
|
|
{
|
|
"type": "statemachine",
|
|
"clkMhz": 100,
|
|
"dataLength": 64,
|
|
"maxPendingReadRequests": 8,
|
|
"name": "MyTestGen",
|
|
"states": [
|
|
{
|
|
"addressDistribution": "sequential",
|
|
"addressIncrement": 256,
|
|
"id": 0,
|
|
"maxAddress": 1024,
|
|
"numRequests": 1000,
|
|
"rwRatio": 0.5
|
|
},
|
|
{
|
|
"addressDistribution": "sequential",
|
|
"addressIncrement": 512,
|
|
"id": 1,
|
|
"maxAddress": 2048,
|
|
"minAddress": 1024,
|
|
"numRequests": 100,
|
|
"rwRatio": 0.75
|
|
}
|
|
],
|
|
"transitions": [
|
|
{
|
|
"from": 0,
|
|
"probability": 1.0,
|
|
"to": 1
|
|
}
|
|
]
|
|
},
|
|
{
|
|
"type": "rowhammer",
|
|
"clkMhz": 100,
|
|
"dataLength": 64,
|
|
"name": "MyTestHammer",
|
|
"numRequests": 4000,
|
|
"rowIncrement": 2097152
|
|
}
|
|
]
|
|
}
|
|
)";
|
|
|
|
json_t tracesetup_reference = json_t::parse(tracesetup_string);
|
|
json_t tracesetup_test;
|
|
tracesetup_test[TraceSetupConstants::KEY] = traceSetup;
|
|
|
|
EXPECT_EQ(tracesetup_test, tracesetup_reference);
|
|
}
|