142 lines
3.7 KiB
JSON
142 lines
3.7 KiB
JSON
{
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"memspec": {
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"memarchitecturespec": {
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"burstLength": 16,
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"dataRate": 2,
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"nbrOfBankGroups": 8,
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"nbrOfBanks": 16,
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"nbrOfColumns": 2048,
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"nbrOfRanks": 8,
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"nbrOfDIMMRanks": 2,
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"nbrOfPhysicalRanks": 2,
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"nbrOfLogicalRanks": 2,
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"nbrOfRows": 65536,
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"width": 4,
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"nbrOfDevices": 8,
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"nbrOfChannels": 2,
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"cmdMode": 1,
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"RefMode": 1,
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"RAAIMT" : 16,
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"RAAMMT" : 96,
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"RAADEC" : 16,
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"maxBurstLength": 16
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},
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"memoryId": "JEDEC_2x8x8x8Gbx4_DDR5-3200A_4bit",
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"memoryType": "DDR5",
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"memtimingspec": {
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"RCD": 22,
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"PPD": 2,
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"RP": 22,
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"RAS": 52,
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"RL": 22,
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"RTP": 12,
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"RPRE": 1,
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"RPST": 0,
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"RDDQS": 0,
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"WL": 20,
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"WPRE": 2,
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"WPST": 0,
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"WR": 48,
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"CCD_L_slr": 8,
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"CCD_L_WR_slr": 32,
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"CCD_L_WR2_slr": 16,
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"CCD_M_slr": 8,
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"CCD_M_WR_slr": 32,
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"CCD_S_slr": 8,
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"CCD_S_WR_slr": 8,
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"CCD_dlr": 8,
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"CCD_WR_dlr": 8,
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"CCD_WR_dpr": 8,
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"RRD_L_slr": 8,
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"RRD_S_slr": 8,
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"RRD_dlr": 4,
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"FAW_slr": 32,
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"FAW_dlr": 16,
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"WTR_L": 16,
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"WTR_M": 16,
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"WTR_S": 4,
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"RFC1_slr": 312,
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"RFC2_slr": 208,
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"RFC1_dlr": 104,
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"RFC2_dlr": 70,
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"RFC1_dpr": 104,
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"RFC2_dpr": 70,
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"RFCsb_slr": 184,
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"RFCsb_dlr": 62,
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"REFI1": 6240,
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"REFI2": 3120,
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"REFISB": 1560,
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"REFSBRD_slr": 48,
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"REFSBRD_dlr": 24,
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"RTRS": 2,
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"CPDED": 8,
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"PD": 12,
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"XP": 12,
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"ACTPDEN": 2,
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"PRPDEN": 2,
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"REFPDEN": 2,
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"tCK": 625e-12
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},
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"mempowerspec": {
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"vdd": 0.0,
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"idd0": 0.0,
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"idd2n": 0.0,
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"idd3n": 0.0,
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"idd4r": 0.0,
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"idd4w": 0.0,
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"idd5c": 0.0,
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"idd6n": 0.0,
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"idd2p": 0.0,
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"idd3p": 0.0,
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"vpp": 0.0,
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"ipp0": 0.0,
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"ipp2n": 0.0,
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"ipp3n": 0.0,
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"ipp4r": 0.0,
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"ipp4w": 0.0,
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"ipp5c": 0.0,
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"ipp6n": 0.0,
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"ipp2p": 0.0,
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"ipp3p": 0.0,
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"idd5b": 0.0,
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"idd5f": 0.0,
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"ipp5b": 0.0,
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"ipp5f": 0.0,
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"vddq": 0.0,
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"iBeta_vdd": 0.0,
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"iBeta_vpp": 0.0
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},
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"memimpedancespec": {
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"ck_termination": true,
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"ck_R_eq": 1e6,
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"ck_dyn_E": 1e-12,
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"ca_termination": true,
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"ca_R_eq": 1e6,
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"ca_dyn_E": 1e-12,
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"rdq_termination": true,
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"rdq_R_eq": 1e6,
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"rdq_dyn_E": 1e-12,
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"wdq_termination": true,
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"wdq_R_eq": 1e6,
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"wdq_dyn_E": 1e-12,
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"wdqs_termination": true,
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"wdqs_R_eq": 1e6,
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"wdqs_dyn_E": 1e-12,
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"rdqs_termination": true,
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"rdqs_R_eq": 1e6,
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"rdqs_dyn_E": 1e-12
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},
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"dataratespec": {
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"ca_bus_rate": 2,
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"dq_bus_rate": 2,
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"dqs_bus_rate": 2
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},
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"bankwisespec": {
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"factRho": 1
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}
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}
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}
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