250 lines
7.9 KiB
C++
250 lines
7.9 KiB
C++
/*
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* dram.h
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*
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* Created on: Mar 16, 2014
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* Author: robert
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*/
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#ifndef DRAM_H_
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#define DRAM_H_
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#include <tlm.h>
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#include <systemc.h>
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#include <tlm_utils/peq_with_cb_and_phase.h>
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#include <tlm_utils/simple_target_socket.h>
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#include "../common/DebugManager.h"
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#include "../common/dramExtension.h"
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#include "../controller/core/TimingCalculation.h"
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#include "../controller/core/configuration/Configuration.h"
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#include "../common/protocol.h"
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#include "../common/Utils.h"
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#include "../common/TlmRecorder.h"
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#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
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#include "../common/third_party/DRAMPower/src/xmlparser/MemSpecParser.h"
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#include "../common/third_party/DRAMPower/src/MemorySpecification.h"
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#include "../common/third_party/DRAMPower/src/MemCommand.h"
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using namespace std;
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using namespace tlm;
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using namespace core;
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using namespace Data;
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#define POWER
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#ifdef POWER
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#define IFPOW(x) x
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#else
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#define IFPOW(x)
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#endif
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class column
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{
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private:
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unsigned char * data;
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unsigned int bytes;
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public:
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column()
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{
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bytes = 0;
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data = NULL;
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}
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column(int bytes)
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{
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this->bytes = bytes;
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data = new unsigned char[bytes];
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}
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~column()
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{
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delete data;
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}
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void set(unsigned char * payloadDataPtr)
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{
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//printf("Dest: %p Source: %p\n",data,payloadDataPtr);
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memcpy(data, payloadDataPtr, bytes);
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}
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void get(unsigned char * payloadDataPtr)
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{
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memcpy(payloadDataPtr, data, bytes);
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}
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};
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template<unsigned int BUSWIDTH = 128, unsigned int WORDS = 4096, bool STORE = true, bool FIXED_BL = false,
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unsigned int FIXED_BL_VALUE = 0>
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struct Dram: sc_module
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{
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tlm_utils::simple_target_socket<Dram, BUSWIDTH, tlm::tlm_base_protocol_types> tSocket;
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IFPOW(libDRAMPower *DRAMPower);
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map< unsigned long int, column * > memory;
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SC_CTOR(Dram) : tSocket("socket")
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{
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tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw);
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IFPOW( MemorySpecification memSpec(MemSpecParser::getMemSpecFromXML(Configuration::getInstance().memspecUri)) );
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IFPOW( DRAMPower = new libDRAMPower( memSpec, 0 ) );
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}
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~Dram()
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{
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IFPOW( DRAMPower->updateCounters(true));
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IFPOW( DRAMPower->getEnergy() );
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IFPOW( cout << "Total Energy" << "\t" << DRAMPower->mpm.energy.total_energy << endl);
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IFPOW( cout << "Average Power" << "\t" << DRAMPower->mpm.power.average_power << endl );
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std::cout << "Simulated Memory Size: " << memory.size() << endl;
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}
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virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& payload, tlm::tlm_phase& phase, sc_time& delay)
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{
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TlmRecorder::getInstance().recordPhase(payload, phase, sc_time_stamp() + delay);
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// This is only needed for power simulation:
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unsigned long long cycle = sc_time_stamp().value()/Configuration::getInstance().Timings.clk.value();
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unsigned int bank = DramExtension::getExtension(payload).getBank().ID();
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if (phase == BEGIN_PRE)
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{
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IFPOW(DRAMPower->doCommand(MemCommand::PRE, bank, cycle));
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sendToController(payload, END_PRE, delay + getExecutionTime(Command::Precharge, payload));
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}
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else if (phase == BEGIN_PRE_ALL)
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{
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IFPOW(DRAMPower->doCommand(MemCommand::PREA, bank, cycle));
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sendToController(payload, END_PRE_ALL,delay + getExecutionTime(Command::PrechargeAll, payload));
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}
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else if (phase == BEGIN_ACT)
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{
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IFPOW(DRAMPower->doCommand(MemCommand::ACT, bank, cycle));
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sendToController(payload, END_ACT, delay + getExecutionTime(Command::Activate, payload));
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}
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else if (phase == BEGIN_WR)
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{
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IFPOW(DRAMPower->doCommand(MemCommand::WR, bank, cycle));
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sendToController(payload, END_WR, delay + getExecutionTime(Command::Write, payload));
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// Save:
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//column * c = new column(16);
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//c->set(payload.get_data_ptr());
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//memory[payload.get_address()] = c;
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}
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else if (phase == BEGIN_RD)
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{
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IFPOW(DRAMPower->doCommand(MemCommand::RD, bank, cycle));
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sendToController(payload, END_RD, delay + getExecutionTime(Command::Read, payload));
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// Load:
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//if(memory.count(payload.get_address()) == 1)
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//{
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// column * c = memory[payload.get_address()];
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// c->get(payload.get_data_ptr());
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//}
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//else
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//{
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// SC_REPORT_WARNING ("DRAM", "Reading from an empty memory location");
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//}
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}
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else if (phase == BEGIN_WRA)
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{
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IFPOW(DRAMPower->doCommand(MemCommand::WRA, bank, cycle));
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sendToController(payload, END_WRA, delay + getExecutionTime(Command::WriteA, payload));
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}
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else if (phase == BEGIN_RDA)
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{
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IFPOW(DRAMPower->doCommand(MemCommand::RDA, bank, cycle));
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sendToController(payload, END_RDA, delay + getExecutionTime(Command::ReadA, payload));
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}
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else if (phase == BEGIN_REFA)
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{
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IFPOW(DRAMPower->doCommand(MemCommand::REF, bank, cycle));
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sendToController(payload, END_REFA, delay + getExecutionTime(Command::AutoRefresh, payload));
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}
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else if (phase == BEGIN_REFB)
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{
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IFPOW( SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported") );
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sendToController(payload, END_REFB, delay + getExecutionTime(Command::AutoRefresh, payload));
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}
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//Powerdown phases have to be started and ended by the controller, because they do not have a fixed length
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else if (phase == BEGIN_PDNA)
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{
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IFPOW(DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle));
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}
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else if (phase == END_PDNA)
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{
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IFPOW(DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle));
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}
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else if (phase == BEGIN_PDNAB)
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{
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IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"));
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}
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else if (phase == END_PDNAB)
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{
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IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"));
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}
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else if (phase == BEGIN_PDNP)
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{
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IFPOW(DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle));
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}
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else if (phase == END_PDNP)
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{
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IFPOW(DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle));
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}
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else if (phase == BEGIN_PDNPB)
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{
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IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"));
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}
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else if (phase == END_PDNPB)
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{
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IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"));
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}
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else if (phase == BEGIN_SREF)
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{
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IFPOW(DRAMPower->doCommand(MemCommand::SREN, bank, cycle));
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}
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else if (phase == END_SREF)
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{
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IFPOW(DRAMPower->doCommand(MemCommand::SREX, bank, cycle));
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}
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else if (phase == BEGIN_SREFB)
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{
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IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"));
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}
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else if (phase == END_SREFB)
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{
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IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported"));
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}
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else
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{
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IFPOW(SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase"));
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}
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return tlm::TLM_ACCEPTED;
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}
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void sendToController(tlm_generic_payload& payload, const tlm_phase& phase, const sc_time& delay)
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{
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tlm_phase TPhase = phase;
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sc_time TDelay = delay;
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tSocket->nb_transport_bw(payload, TPhase, TDelay);
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}
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void printDebugMessage(string message)
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{
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DebugManager::getInstance().printDebugMessage(name(), message);
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}
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};
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#endif /* DRAM_H_ */
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