Files
DRAMSys/scripts/simulation/example_ddr3_simulations.json

142 lines
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{
"simulation": {
"addressmapping": {
"BANK_BIT": [
6,
7,
8
],
"BYTE_BIT": [
0,
1,
2
],
"COLUMN_BIT": [
3,
4,
5,
9,
10,
11,
12,
13,
14,
15
],
"ROW_BIT": [
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
},
"mcconfig": {
"PagePolicy": "<page_policy>",
"SchedulerBuffer": "<scheduler_buffer>",
"RequestBufferSize": <scheduler_buffer_size>,
"RefreshPolicy": "<refresh_policy>",
"RefreshMaxPostponed": 0,
"RefreshMaxPulledin": 0,
"RefreshManagement": false,
"Arbiter": "Simple",
"CmdMux": "Oldest",
"MaxActiveTransactions": 128,
"PowerDownPolicy": "NoPowerDown",
"RespQueue": "Fifo",
"Scheduler": "FrFcfs"
},
"memspec": {
"memarchitecturespec": {
"burstLength": 8,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfChannels": 1,
"nbrOfColumns": 1024,
"nbrOfDevices": 8,
"nbrOfRanks": 1,
"nbrOfRows": 16384,
"width": 8
},
"memoryId": "MICRON_1Gb_DDR3-1600_8bit_G",
"memoryType": "DDR3",
"mempowerspec": {
"idd0": 70.0,
"idd2n": 45.0,
"idd2p0": 12.0,
"idd2p1": 30.0,
"idd3n": 45.0,
"idd3p0": 35.0,
"idd3p1": 35.0,
"idd4r": 140.0,
"idd4w": 145.0,
"idd5": 170.0,
"idd6": 8.0,
"vdd": 1.5
},
"memtimingspec": {
"ACTPDEN": 1,
"AL": 0,
"CCD": 4,
"CKE": 3,
"CKESR": 4,
"CL": 10,
"DQSCK": 0,
"FAW": 24,
"PRPDEN": 1,
"RAS": 28,
"RC": 38,
"RCD": 10,
"REFI": 6240,
"REFPDEN": 1,
"RFC": 88,
"RL": 10,
"RP": 10,
"RRD": 5,
"RTP": 6,
"RTRS": 1,
"WL": 8,
"WR": 12,
"WTR": 6,
"XP": 6,
"XPDLL": 20,
"XS": 96,
"XSDLL": 512,
"clkMhz": 800
}
},
"simconfig": {
"AddressOffset": 0,
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"EnableWindowing": false,
"PowerAnalysis": false,
"SimulationName": "example",
"SimulationProgressBar": false,
"StoreMode": "NoStorage",
"UseMalloc": false,
"WindowSize": 1000
},
"simulationid": "ddr3-example",
"tracesetup": [
{
"clkMhz": 2000,
"type": "generator",
"name": "gen1",
"numRequests": 20000,
"rwRatio": 0.85,
"addressDistribution": "<pattern>"
}
]
}
}