109 lines
3.8 KiB
C++
109 lines
3.8 KiB
C++
/*
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* Copyright (c) 2019, RPTU Kaiserslautern-Landau
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Lukas Steiner
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*/
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#include "SchedulerFifo.h"
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#include "DRAMSys/controller/scheduler/BufferCounterBankwise.h"
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#include "DRAMSys/controller/scheduler/BufferCounterReadWrite.h"
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#include "DRAMSys/controller/scheduler/BufferCounterShared.h"
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using namespace tlm;
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namespace DRAMSys
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{
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SchedulerFifo::SchedulerFifo(const Configuration& config)
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{
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buffer = ControllerVector<Bank, std::deque<tlm_generic_payload*>>(config.memSpec->banksPerChannel);
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if (config.schedulerBuffer == Configuration::SchedulerBuffer::Bankwise)
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bufferCounter = std::make_unique<BufferCounterBankwise>(config.requestBufferSize, config.memSpec->banksPerChannel);
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else if (config.schedulerBuffer == Configuration::SchedulerBuffer::ReadWrite)
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bufferCounter = std::make_unique<BufferCounterReadWrite>(config.requestBufferSize);
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else if (config.schedulerBuffer == Configuration::SchedulerBuffer::Shared)
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bufferCounter = std::make_unique<BufferCounterShared>(config.requestBufferSize);
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}
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bool SchedulerFifo::hasBufferSpace() const
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{
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return bufferCounter->hasBufferSpace();
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}
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void SchedulerFifo::storeRequest(tlm_generic_payload& payload)
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{
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buffer[ControllerExtension::getBank(payload)].push_back(&payload);
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bufferCounter->storeRequest(payload);
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}
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void SchedulerFifo::removeRequest(tlm_generic_payload& payload)
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{
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buffer[ControllerExtension::getBank(payload)].pop_front();
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bufferCounter->removeRequest(payload);
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}
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tlm_generic_payload* SchedulerFifo::getNextRequest(const BankMachine& bankMachine) const
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{
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Bank bank = bankMachine.getBank();
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if (!buffer[bank].empty())
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return buffer[bank].front();
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else
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return nullptr;
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}
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bool SchedulerFifo::hasFurtherRowHit(Bank bank, Row row, tlm_command command) const
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{
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if (buffer[bank].size() >= 2)
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{
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tlm_generic_payload& nextRequest = *buffer[bank][1];
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if (ControllerExtension::getRow(nextRequest) == row)
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return true;
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}
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return false;
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}
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bool SchedulerFifo::hasFurtherRequest(Bank bank, tlm_command command) const
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{
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if (buffer[bank].size() >= 2)
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return true;
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else
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return false;
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}
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const std::vector<unsigned>& SchedulerFifo::getBufferDepth() const
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{
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return bufferCounter->getBufferDepth();
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}
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} // namespace DRAMSys
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