81 lines
2.1 KiB
JSON
81 lines
2.1 KiB
JSON
{
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"memspec": {
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"memarchitecturespec": {
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"burstLength": 16,
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"dataRate": 2,
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"nbrOfBankGroups": 8,
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"nbrOfBanks": 16,
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"nbrOfColumns": 1024,
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"nbrOfRanks": 1,
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"nbrOfDIMMRanks": 1,
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"nbrOfPhysicalRanks": 1,
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"nbrOfLogicalRanks": 1,
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"nbrOfRows": 65536,
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"width": 8,
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"nbrOfDevices": 4,
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"nbrOfChannels": 2,
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"cmdMode": 1,
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"refMode": 1,
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"RAAIMT" : 16,
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"RAAMMT" : 96,
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"RAADEC" : 16
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},
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"memoryId": "JEDEC_2x4x1Gbx8_DDR5-3200A",
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"memoryType": "DDR5",
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"memtimingspec": {
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"RCD": 22,
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"PPD": 2,
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"RP": 22,
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"RAS": 52,
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"RL": 22,
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"RTP": 12,
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"RPRE": 1,
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"RPST": 0,
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"RDDQS": 0,
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"WL": 20,
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"WPRE": 2,
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"WPST": 0,
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"WR": 48,
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"CCD_L_slr": 8,
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"CCD_L_WR_slr": 32,
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"CCD_L_WR2_slr": 16,
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"CCD_M_slr": 8,
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"CCD_M_WR_slr": 32,
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"CCD_S_slr": 8,
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"CCD_S_WR_slr": 8,
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"CCD_dlr": 0,
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"CCD_WR_dlr": 0,
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"CCD_WR_dpr": 0,
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"RRD_L_slr": 8,
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"RRD_S_slr": 8,
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"RRD_dlr": 0,
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"FAW_slr": 32,
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"FAW_dlr": 0,
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"WTR_L": 16,
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"WTR_M": 16,
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"WTR_S": 4,
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"RFC1_slr": 312,
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"RFC2_slr": 208,
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"RFC1_dlr": 0,
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"RFC2_dlr": 0,
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"RFC1_dpr": 0,
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"RFC2_dpr": 0,
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"RFCsb_slr": 184,
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"RFCsb_dlr": 0,
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"REFI1": 6240,
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"REFI2": 3120,
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"REFISB": 1560,
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"REFSBRD_slr": 48,
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"REFSBRD_dlr": 0,
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"RTRS": 2,
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"CPDED": 8,
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"PD": 12,
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"XP": 12,
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"ACTPDEN": 2,
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"PRPDEN": 2,
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"REFPDEN": 2,
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"tCK": 625
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}
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}
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}
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