365 lines
11 KiB
C++
365 lines
11 KiB
C++
/*
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* ControllerWrapper.h
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*
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* Created on: Mar 15, 2014
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* Author: gernhard
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*/
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#ifndef CONTROLLERWRAPPER_H_
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#define CONTROLLERWRAPPER_H_
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#include <tlm.h>
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#include <systemc.h>
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#include <tlm_utils/simple_target_socket.h>
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#include <tlm_utils/simple_initiator_socket.h>
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#include <tlm_utils/peq_with_cb_and_phase.h>
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#include <iostream>
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#include <map>
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#include <string>
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#include "../common/Utils.h"
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#include "../common/protocol.h"
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#include "../common/TlmRecorder.h"
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#include "../common/DebugManager.h"
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#include "../core/IWrapperConnector.h"
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#include "../core/Controller.h"
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#include "../scheduler/Scheduler.h"
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#include "../scheduler/Fifo.h"
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#include "../scheduler/Fr_Fcfs.h"
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using namespace std;
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using namespace tlm;
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using namespace core;
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using namespace scheduler;
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template<unsigned int BUSWIDTH = 128>
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struct ControllerWrapper: public sc_module, public IWrapperConnector
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{
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public:
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tlm_utils::simple_initiator_socket<ControllerWrapper, BUSWIDTH, tlm::tlm_base_protocol_types> iSocket;
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tlm_utils::simple_target_socket<ControllerWrapper, BUSWIDTH, tlm::tlm_base_protocol_types> tSocket;
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ControllerWrapper(sc_module_name name, TlmRecorder& recorder) :
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frontendPEQ(this, &ControllerWrapper::frontendPEQCallback), dramPEQ(this,
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&ControllerWrapper::dramPEQCallback), controllerPEQ(this,
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&ControllerWrapper::controllerPEQCallback), recorder(recorder), debugManager(
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DebugManager::getInstance())
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{
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controller = new Controller(*this, recorder, numberOfPayloads);
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scheduler = new Fifo(*controller);
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inputBufferDelay = controller->config.Timings.clk;
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iSocket.register_nb_transport_bw(this, &ControllerWrapper::nb_transport_bw);
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tSocket.register_nb_transport_fw(this, &ControllerWrapper::nb_transport_fw);
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}
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~ControllerWrapper()
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{
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delete controller;
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delete scheduler;
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}
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virtual void send(const ScheduledCommand& command, tlm_generic_payload& payload) override
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{
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assert(command.getStart() >= sc_time_stamp());
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switch (command.getCommand())
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{
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case Command::Read:
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dramPEQ.notify(payload, BEGIN_RD, command.getStart() - sc_time_stamp());
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dramPEQ.notify(payload, END_RD, command.getEnd() - sc_time_stamp());
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break;
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case Command::Write:
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dramPEQ.notify(payload, BEGIN_WR, command.getStart() - sc_time_stamp());
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dramPEQ.notify(payload, END_WR, command.getEnd() - sc_time_stamp());
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break;
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case Command::AutoRefresh:
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dramPEQ.notify(payload, BEGIN_AUTO_REFRESH, command.getStart() - sc_time_stamp());
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dramPEQ.notify(payload, END_AUTO_REFRESH, command.getEnd() - sc_time_stamp());
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break;
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case Command::Activate:
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dramPEQ.notify(payload, BEGIN_ACT, command.getStart() - sc_time_stamp());
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dramPEQ.notify(payload, END_ACT, command.getEnd() - sc_time_stamp());
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break;
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case Command::Precharge:
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dramPEQ.notify(payload, BEGIN_PRE, command.getStart() - sc_time_stamp());
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dramPEQ.notify(payload, END_PRE, command.getEnd() - sc_time_stamp());
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break;
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case Command::PrechargeAll:
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dramPEQ.notify(payload, BEGIN_PRE_ALL, command.getStart() - sc_time_stamp());
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dramPEQ.notify(payload, END_PRE_ALL, command.getEnd() - sc_time_stamp());
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break;
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case Command::PDNA:
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dramPEQ.notify(payload, BEGIN_PDNA, command.getStart() - sc_time_stamp());
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break;
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case Command::PDNP:
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dramPEQ.notify(payload, BEGIN_PDNP, command.getStart() - sc_time_stamp());
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break;
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case Command::SREF:
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dramPEQ.notify(payload, BEGIN_SREF, command.getStart() - sc_time_stamp());
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break;
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case Command::PDNAX:
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dramPEQ.notify(payload, END_PDNA, command.getStart() - sc_time_stamp());
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break;
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case Command::PDNPX:
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dramPEQ.notify(payload, END_PDNP, command.getStart() - sc_time_stamp());
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break;
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case Command::SREFX:
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dramPEQ.notify(payload, END_SREF, command.getStart() - sc_time_stamp());
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break;
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default:
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SC_REPORT_FATAL(0, "unsupported command in controller wrapper");
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break;
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}
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}
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virtual void send(Trigger trigger, sc_time time, tlm_generic_payload& payload) override
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{
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assert(time >= sc_time_stamp());
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sc_time delay = time - sc_time_stamp();
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if(trigger == Trigger::RefreshTrigger)
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{
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controllerPEQ.notify(payload, REFRESH_TRIGGER, delay);
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}
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else if(trigger == Trigger::WakeUpTrigger)
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{
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controllerPEQ.notify(payload, WAKEUP_TRIGGER, delay);
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}
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else
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{
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SC_REPORT_FATAL("controller wrapper", "unknown trigger");
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}
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}
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private:
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Controller* controller;
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Scheduler* scheduler;
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std::map<Bank, int> numberOfPayloads;
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tlm_utils::peq_with_cb_and_phase<ControllerWrapper> frontendPEQ;
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tlm_utils::peq_with_cb_and_phase<ControllerWrapper> dramPEQ;
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tlm_utils::peq_with_cb_and_phase<ControllerWrapper> controllerPEQ;
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sc_time inputBufferDelay;
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TlmRecorder& recorder;
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DebugManager& debugManager;
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void payloadEntersSystem(tlm_generic_payload& payload)
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{
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printDebugMessage("Transaction enters system");
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Bank bank = DramExtension::getExtension(payload).getBank();
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numberOfPayloads[bank] = numberOfPayloads[bank] + 1;
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scheduler->schedule(&payload);
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}
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void payloadLeavesSystem(tlm_generic_payload& payload)
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{
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Bank bank = DramExtension::getExtension(payload).getBank();
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numberOfPayloads[bank] = numberOfPayloads[bank] - 1;
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sc_assert(numberOfPayloads[bank] >= 0);
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if (numberOfPayloads[bank] == 0)
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controller->powerDownManager->sleep(bank, sc_time_stamp());
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}
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void scheduleNextPayload(Bank bank)
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{
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printDebugMessage("Try to schedule next payload on bank " + to_string(bank.ID()));
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if (scheduler->hasTransactionForBank(bank))
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{
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if (controller->isBusy(sc_time_stamp(), bank))
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{
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printDebugMessage("\t-> break: controller is busy");
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return;
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}
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if (controller->powerDownManager->isInPowerDown(bank))
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{
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controller->powerDownManager->wakeUp(bank, sc_time_stamp());
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printDebugMessage("\t-> break: wake up power down");
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return;
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}
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else if (controller->powerDownManager->isAwakeForRefresh(bank))
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{
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controller->powerDownManager->wakeUp(bank, sc_time_stamp());
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}
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tlm_generic_payload* nextTransaction = scheduler->getTransactionForBank(bank);
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if (controller->scheduleRequest(sc_time_stamp(), *nextTransaction))
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{
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scheduler->popTransactionForBank(bank);
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printDebugMessage("\t-> payload was scheduled by core");
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}
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else
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{
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printDebugMessage("\t-> break: payload was not scheduled by core (collision with refresh)");
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}
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}
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else
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{
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printDebugMessage("\t-> break: no transaction for bank");
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}
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}
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tlm_sync_enum nb_transport_bw(tlm_generic_payload& payload, tlm_phase& phase, sc_time& bwDelay)
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{
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return TLM_ACCEPTED;
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}
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// Initiated by dram frontend
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tlm_sync_enum nb_transport_fw(tlm_generic_payload& payload, tlm_phase& phase, sc_time& fwDelay)
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{
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DramExtension::getExtension(payload);
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recorder.recordPhase(payload, phase, sc_time_stamp());
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if (phase == BEGIN_REQ)
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{
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payload.acquire();
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payloadEntersSystem(payload);
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frontendPEQ.notify(payload, phase, inputBufferDelay);
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}
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else if (phase == END_RESP)
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{
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payloadLeavesSystem(payload);
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payload.release();
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}
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return TLM_ACCEPTED;
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}
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void frontendPEQCallback(tlm_generic_payload& payload, const tlm_phase& phase)
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{
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if (phase == BEGIN_REQ)
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{
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scheduleNextPayload(DramExtension::getExtension(payload).getBank());
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payload.set_response_status(tlm::TLM_OK_RESPONSE);
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recorder.recordPhase(payload, END_REQ, sc_time_stamp());
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sendToFrontend(payload, END_REQ, SC_ZERO_TIME);
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}
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else
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{
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SC_REPORT_FATAL(0,
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"Frontend PEQ event queue in controller wrapper was triggered with unknown phase");
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}
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}
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void dramPEQCallback(tlm_generic_payload& payload, const tlm_phase& phase)
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{
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recorder.recordPhase(payload, phase, sc_time_stamp());
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Bank bank = DramExtension::getExtension(payload).getBank();
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if (phase == BEGIN_RD || phase == BEGIN_WR)
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{
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scheduleNextPayload(bank);
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sendToDram(payload, phase, SC_ZERO_TIME);
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}
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else if (phase == END_RD || phase == END_WR)
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{
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recorder.recordPhase(payload, BEGIN_RESP, sc_time_stamp());
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sendToFrontend(payload, BEGIN_RESP, SC_ZERO_TIME);
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}
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else if (isIn(phase, {BEGIN_ACT, BEGIN_PRE, BEGIN_PRE_ALL }))
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{
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sendToDram(payload, phase, SC_ZERO_TIME);
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}
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else if(isIn(phase, {BEGIN_PDNA,
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BEGIN_PDNP, BEGIN_SREF}))
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{
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printDebugMessage("Entering PowerDown " + phaseNameToString(phase) + " on bank " + to_string(bank.ID()));
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sendToDram(payload, phase, SC_ZERO_TIME);
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}
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else if (isIn(phase, { END_PDNA, END_PDNP, END_SREF }))
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{
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printDebugMessage("Leaving PowerDown " + phaseNameToString(phase) + " on bank " + to_string(bank.ID()));
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sendToDram(payload, phase, SC_ZERO_TIME);
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if (phase == END_SREF)
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controller->refreshManager->reInitialize(payload, sc_time_stamp());
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scheduleNextPayload(bank);
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}
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else if(phase == BEGIN_AUTO_REFRESH)
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{
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printDebugMessage("Entering auto refresh on bank " + to_string(bank.ID()));
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sendToDram(payload, phase, SC_ZERO_TIME);
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}
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else if (phase == END_AUTO_REFRESH)
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{
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printDebugMessage("Finished auto refresh on bank " + to_string(bank.ID()));
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if (numberOfPayloads[bank] == 0)
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controller->powerDownManager->sleep(bank, sc_time_stamp());
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scheduleNextPayload(DramExtension::getExtension(payload).getBank());
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}
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else if (isIn(phase, { END_PRE, END_PRE_ALL, END_ACT }))
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{
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}
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else
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{
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ostringstream oss;
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oss << phase;
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string str = string(
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"dramPEQCallback queue in controller wrapper was triggered with unknown phase ")
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+ oss.str();
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SC_REPORT_FATAL(0, str.c_str());
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}
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}
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void controllerPEQCallback(tlm_generic_payload& payload, const tlm_phase& phase)
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{
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if (phase == REFRESH_TRIGGER)
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{
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controller->triggerRefresh(payload, sc_time_stamp());
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}
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else if (phase == WAKEUP_TRIGGER)
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{
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controller->triggerWakeUp(payload, sc_time_stamp());
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}
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else
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{
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SC_REPORT_FATAL(0,
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"controllerPEQCallback queue in controller wrapper was triggered with unknown phase");
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}
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}
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void sendToDram(tlm_generic_payload& payload, const tlm_phase& phase, const sc_time& delay)
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{
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DramExtension::getExtension(payload);
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tlm_phase TPhase = phase;
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sc_time TDelay = delay;
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iSocket->nb_transport_fw(payload, TPhase, TDelay);
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}
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void sendToFrontend(tlm_generic_payload& payload, const tlm_phase& phase, const sc_time& delay)
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{
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tlm_phase TPhase = phase;
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sc_time TDelay = delay;
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tSocket->nb_transport_bw(payload, TPhase, TDelay);
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}
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void printDebugMessage(string message, Importance importance = Importance::Info)
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{
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debugManager.printDebugMessage(message, Sender::DramWrapper, importance);
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}
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bool isIn(tlm_phase phase, std::vector<tlm_phase> phases)
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{
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for (tlm_phase p : phases)
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{
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if (p == phase)
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return true;
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}
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return false;
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}
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void stop()
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{
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for (Bank bank : controller->getBanks())
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{
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controller->powerDownManager->wakeUp(bank, sc_time_stamp());
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}
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}
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};
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#endif /* CONTROLLERWRAPPER_H_ */
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