0a992391d2
Show rgr related config during initialization. ORGR in traceAnalyzer. Submodule drampower set properly (point to rgr branch). New config for row increment (selective ref.). Specific simulations NO REF. and AR with close page policy. Simulation files ddr4 1, 2, 4 x mode open, close page policy, no ref, ar, rgr, orgr. New config for number of auto-ref. cmds in 64 ms. New traces for ddr4. New spec for dd4 16Gb after Christian's corrections. Initial offset for bankwise logic (if zeroed, for research). ORGR/RGR. Flex. ORGR/RGR. Bankwise flex. refresh. Small schanges. RGR flex test files. Doc updated.
250 lines
8.6 KiB
Prolog
250 lines
8.6 KiB
Prolog
TARGET = DRAMSys
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TEMPLATE = lib
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CONFIG += staticlib
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CONFIG += console
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CONFIG -= app_bundle
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CONFIG -= qt
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system(cd ../../DRAMSys/library/src/common/third_party/DRAMPower; make src/libdrampower.a;)
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systemc_home = $$(SYSTEMC_HOME)
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isEmpty(systemc_home) {
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systemc_home = /opt/systemc
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}
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# Check if PCT's SystemC should be used?
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dramsys_pct = $$(DRAMSYS_PCT)
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isEmpty(dramsys_pct) {
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dramsys_pct = false
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}
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$$eval(dramsys_pct) {
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# PCT:
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message(PCT Simulation Feature Enabled)
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systemc_home = /software/Synopsys_CoWare/K-2015.12-SP1/SLS/linux/common
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INCLUDEPATH += $${systemc_home}/include/tlm
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DEFINES += DRAMSYS_PCT
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}
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# Check if gem5 should be used
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gem5 = $$(GEM5)
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isEmpty(gem5) {
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message(GEM5 environment variable not found)
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message(Gem5 Simulation Disabled)
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} else {
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message(Gem5 Simulation Feature Enabled)
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message(Gem5 home is $${gem5})
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DEFINES += DRAMSYS_GEM5
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}
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message(SystemC home is $${systemc_home})
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systemc_target_arch = $$(SYSTEMC_TARGET_ARCH)
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isEmpty(systemc_target_arch) {
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systemc_target_arch = linux64
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}
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message(SystemC target architecture is $${systemc_target_arch})
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INCLUDEPATH += $${systemc_home}/include
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INCLUDEPATH += src/common/third_party/DRAMPower/src
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INCLUDEPATH += src/common/third_party/DRAMPower/src/libdrampower
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INCLUDEPATH += src/common/third_party/json/include
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DEFINES += TIXML_USE_STL
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DEFINES += SC_INCLUDE_DYNAMIC_PROCESSES
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unix:!macx {
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QMAKE_CXXFLAGS += -std=c++11 -O0 -g
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}
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macx: {
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CONFIG += c++11
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QMAKE_CXXFLAGS += -std=c++0x -stdlib=libc++ -O0 -g
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}
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QMAKE_CXXFLAGS += -isystem $${systemc_home}/include
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SOURCES += \
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src/common/third_party/tinyxml2/tinyxml2.cpp \
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src/common/xmlAddressdecoder.cpp \
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src/common/Utils.cpp \
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src/common/TlmRecorder.cpp \
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src/common/dramExtension.cpp \
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src/common/DebugManager.cpp \
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src/controller/core/configuration/Configuration.cpp \
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src/controller/core/powerdown/PowerDownManagerTimeout.cpp \
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src/controller/core/powerdown/PowerDownManagerBankwise.cpp \
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src/controller/core/powerdown/PowerDownManager.cpp \
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src/controller/scheduler/ThreadLoad.cpp \
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src/controller/scheduler/PARBS.cpp \
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src/controller/scheduler/Fr_Fcfs.cpp \
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src/controller/scheduler/Fifo.cpp \
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src/controller/scheduler/SMS.cpp \
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src/controller/core/refresh/RefreshManagerBankwise.cpp \
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src/controller/core/refresh/RefreshManager.cpp \
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src/controller/core/refresh/RGR.cpp \
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src/controller/core/scheduling/checker/WriteChecker.cpp \
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src/controller/core/scheduling/checker/RefreshChecker.cpp \
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src/controller/core/scheduling/checker/ReadChecker.cpp \
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src/controller/core/scheduling/checker/PrechargeChecker.cpp \
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src/controller/core/scheduling/checker/PrechargeAllChecker.cpp \
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src/controller/core/scheduling/checker/PowerDownChecker.cpp \
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src/controller/core/scheduling/checker/ActivateChecker.cpp \
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src/controller/core/scheduling/checker/PreBChecker.cpp \
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src/controller/core/scheduling/checker/ActBChecker.cpp \
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src/controller/core/scheduling/ScheduledCommand.cpp \
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src/controller/core/TimingCalculation.cpp \
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src/controller/core/Slots.cpp \
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src/controller/core/ControllerCore.cpp \
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src/simulation/MemoryManager.cpp \
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src/simulation/TemperatureController.cpp \
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src/controller/scheduler/readwritegrouper.cpp \
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src/controller/core/configuration/ConfigurationLoader.cpp \
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src/controller/core/powerdown/NoPowerDown.cpp \
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src/controller/Command.cpp \
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src/controller/ControllerState.cpp \
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src/controller/RowBufferStates.cpp \
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src/controller/scheduler/IScheduler.cpp \
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src/controller/scheduler/FifoStrict.cpp \
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src/error/errormodel.cpp \
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src/controller/Controller.cpp \
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src/simulation/TracePlayer.cpp \
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src/simulation/StlPlayer.cpp \
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src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.cpp \
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src/simulation/TraceSetup.cpp \
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src/simulation/DRAMSys.cpp \
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src/simulation/Setup.cpp \
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src/error/ECC/Bit.cpp \
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src/error/ECC/ECC.cpp \
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src/error/ECC/Word.cpp \
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src/error/eccbaseclass.cpp \
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src/error/ecchamming.cpp \
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src/controller/scheduler/Fr_Fcfs_read_priority.cpp \
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src/controller/scheduler/Fr_Fcfs_grouper.cpp \
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src/common/AddressDecoder.cpp \
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src/common/jsonAddressDecoder.cpp
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HEADERS += \
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src/common/third_party/tinyxml2/tinyxml2.h \
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src/common/xmlAddressdecoder.h \
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src/common/Utils.h \
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src/common/TlmRecorder.h \
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src/common/tlm2_base_protocol_checker.h \
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src/common/protocol.h \
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src/common/dramExtension.h \
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src/common/DebugManager.h \
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src/controller/core/configuration/Configuration.h \
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src/controller/core/powerdown/PowerDownManagerTimeout.h \
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src/controller/core/powerdown/PowerDownManagerBankwise.h \
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src/controller/core/powerdown/PowerDownManager.h \
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src/controller/scheduler/ThreadLoad.h \
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src/controller/scheduler/PARBS.h \
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src/controller/scheduler/Fr_Fcfs.h \
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src/controller/scheduler/Fifo.h \
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src/controller/scheduler/SMS.h \
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src/controller/Controller.h \
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src/controller/core/refresh/RefreshManagerBankwise.h \
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src/controller/core/refresh/RefreshManager.h \
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src/controller/core/refresh/IRefreshManager.h \
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src/controller/core/refresh/RGR.h \
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src/controller/core/scheduling/checker/WriteChecker.h \
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src/controller/core/scheduling/checker/RefreshChecker.h \
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src/controller/core/scheduling/checker/ReadChecker.h \
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src/controller/core/scheduling/checker/PrechargeChecker.h \
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src/controller/core/scheduling/checker/PrechargeAllChecker.h \
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src/controller/core/scheduling/checker/PowerDownChecker.h \
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src/controller/core/scheduling/checker/ICommandChecker.h \
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src/controller/core/scheduling/checker/ActivateChecker.h \
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src/controller/core/scheduling/checker/PreBChecker.h \
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src/controller/core/scheduling/checker/ActBChecker.h \
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src/controller/core/scheduling/Trigger.h \
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src/controller/core/scheduling/ScheduledCommand.h \
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src/controller/core/TimingCalculation.h \
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src/controller/core/Slots.h \
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src/controller/core/ControllerCore.h \
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src/simulation/TracePlayer.h \
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src/simulation/MemoryManager.h \
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src/simulation/Dram.h \
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src/simulation/Arbiter.h \
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src/common/libDRAMPower.h \
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src/controller/scheduler/readwritegrouper.h \
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src/simulation/ReorderBuffer.h \
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src/controller/core/configuration/MemSpec.h \
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src/controller/core/configuration/thermalSimConfig.h \
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src/simulation/StlPlayer.h \
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src/simulation/TracePlayerListener.h \
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src/simulation/TraceGenerator.h \
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src/simulation/TemperatureController.h \
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src/controller/core/powerdown/NoPowerDown.h \
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src/controller/Command.h \
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src/controller/RowBufferStates.h \
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src/controller/ControllerState.h \
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src/controller/core/powerdown/IPowerDownManager.h \
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src/controller/scheduler/IScheduler.h \
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src/controller/scheduler/FifoStrict.h \
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src/controller/IController.h \
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src/controller/core/configuration/ConfigurationLoader.h \
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src/error/errormodel.h \
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src/simulation/ExampleInitiator.h \
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src/controller/core/powerdown/PowerDownManagerTimeoutBankwise.h \
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src/simulation/TraceSetup.h \
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src/simulation/DRAMSys.h \
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src/simulation/Setup.h \
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src/error/ECC/Bit.h \
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src/error/ECC/ECC.h \
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src/error/ECC/Word.h \
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src/error/eccbaseclass.h \
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src/error/ecchamming.h \
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src/controller/scheduler/Fr_Fcfs_read_priority.h \
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src/controller/scheduler/Fr_Fcfs_grouper.h \
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src/simulation/IArbiter.h \
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src/simulation/SimpleArbiter.h \
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src/common/AddressDecoder.h \
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src/common/jsonAddressDecoder.h
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#src/common/third_party/json/include/nlohmann/json.hpp \
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thermalsim = $$(THERMALSIM)
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isEmpty(thermalsim) {
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thermalsim = false
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}
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$$eval(thermalsim) {
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message(Thermal Simulation Feature Enabled)
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libthreed_ice_home = $$(LIBTHREED_ICE_HOME)
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isEmpty(libthreed_ice_home) {
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libthreed_ice_home = /opt/3D-ICE/
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}
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message(LIBTHREED_ICE_HOME path is $${libthreed_ice_home})
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libsuperlu_home = $$(LIBSUPERLU_HOME)
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isEmpty(libsuperlu_home) {
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libsuperlu_home = /opt/SuperLU_4.3/
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}
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message(LIBSUPERLU_HOME path is $${libthreed_ice_home})
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LIBS += -L$${libthreed_ice_home}/lib -lthreed-ice-2.2.4
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LIBS += -L$${libsuperlu_home}/lib -lsuperlu_4.3
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LIBS += -lblas
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message(Libraries: $${LIBS})
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INCLUDEPATH += $${libthreed_ice_home}/include
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INCLUDEPATH += $${libsuperlu_home}/SRC
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INCLUDEPATH += $${systemc_home}/include
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message(Include paths: $${INCLUDEPATH})
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QMAKE_CXXFLAGS += -DTHERMALSIM
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message(Compiler flags: $${QMAKE_CXXFLAGS})
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} else {
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message(Thermal Simulation Feature Disabled)
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}
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# Additional Files:
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include(resources/resources.pri)
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DISTFILES += ../DRAMSys.astylerc
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