{
    "memspec": {
        "memarchitecturespec": {
            "burstLength": 16,
            "dataRate": 2,
            "nbrOfBankGroups": 8,
            "nbrOfBanks": 16,
            "nbrOfColumns": 2048,
            "nbrOfRanks": 1,
            "nbrOfDIMMRanks": 1,
            "nbrOfPhysicalRanks": 1,
            "nbrOfLogicalRanks": 1,
            "nbrOfRows": 65536,
            "width": 4,
            "nbrOfDevices": 8,
            "nbrOfChannels": 2,
            "cmdMode": 1,
            "refMode": 1,
            "RAAIMT" : 32,
            "RAAMMT" : 96,
            "RAADEC" : 16
        },
        "memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A",
        "memoryType": "DDR5",
        "memtimingspec": {
            "RCD": 22,
            "PPD": 2,
            "RP": 22,
            "RAS": 52,
            "RL": 22,
            "RTP": 12,
            "RPRE": 1,
            "RPST": 0,
            "RDDQS": 0,
            "WL": 20,
            "WPRE": 2,
            "WPST": 0,
            "WR": 48,
            "CCD_L_slr": 8,
            "CCD_L_WR_slr": 32,
            "CCD_L_WR2_slr": 16,
            "CCD_S_slr": 8,
            "CCD_S_WR_slr": 8,
            "CCD_dlr": 0,
            "CCD_WR_dlr": 0,
            "CCD_WR_dpr": 0,
            "RRD_L_slr": 8,
            "RRD_S_slr": 8,
            "RRD_dlr": 0,
            "FAW_slr": 32,
            "FAW_dlr": 0,
            "WTR_L": 16,
            "WTR_S": 4,
            "RFC1_slr": 312,
            "RFC2_slr": 208,
            "RFC1_dlr": 0,
            "RFC2_dlr": 0,
            "RFC1_dpr": 0,
            "RFC2_dpr": 0,
            "RFCsb_slr": 184,
            "RFCsb_dlr": 0,
            "REFI1": 6240,
            "REFI2": 3120,
            "REFISB": 1560,
            "REFSBRD_slr": 48,
            "REFSBRD_dlr": 0,
            "RTRS": 2,
            "CPDED": 8,
            "PD": 12,
            "XP": 12,
            "ACTPDEN": 2,
            "PRPDEN": 2,
            "REFPDEN": 2,
            "tCK": 625
        }
    }
}