{
    "memspec": {
        "memarchitecturespec": {
            "burstLength": 8,
            "dataRate": 4,
            "nbrOfBankGroups": 4,
            "nbrOfBanks": 16,
            "nbrOfColumns": 128,
            "nbrOfPseudoChannels": 2,
            "nbrOfStacks": 2,
            "nbrOfRows": 65536,
            "width": 32,
            "nbrOfDevices": 1,
            "nbrOfChannels": 1,
            "RAAIMT" : 16,
            "RAAMMT" : 96,
            "RAADEC" : 16,
            "maxBurstLength": 8
        },
        "memoryId": "",
        "memoryType": "HBM3",
        "memtimingspec": {
            "CCDL": 4,
            "CCDS": 2,
            "CCDR": 3,
            "CKE": 8,
            "DQSCK": 1,
            "FAW": 16, 
            "PL": 0,
            "PPD": 2,
            "RAS": 28,
            "RC": 42,
            "RCDRD": 12,
            "RCDWR": 6,
            "REFI": 3900,
            "REFIPB": 122,
            "RFC": 260,
            "RFCPB": 96,
            "RL": 17,
            "RP": 14,
            "RRDL": 6,
            "RRDS": 4,
            "RREFD": 8,
            "RTP": 5,
            "RTW": 18,
            "WL": 12,
            "WR": 23,
            "WTRL": 9,
            "WTRS": 4,
            "XP": 8,
            "XS": 260,
            "tCK": 625e-12
        }
    }
}