{ "memspec": { "memarchitecturespec": { "burstLength": 16, "dataRate": 2, "nbrOfBankGroups": 8, "nbrOfBanks": 16, "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfDIMMRanks": 1, "nbrOfPhysicalRanks": 1, "nbrOfLogicalRanks": 1, "nbrOfRows": 65536, "width": 8, "nbrOfDevices": 4, "nbrOfChannels": 2, "cmdMode": 1, "refMode": 1, "RAAIMT" : 16, "RAAMMT" : 96, "RAADEC" : 16 }, "memoryId": "JEDEC_2x4x1Gbx8_DDR5-6400A", "memoryType": "DDR5", "memtimingspec": { "RCD": 46, "PPD": 2, "RP": 46, "RAS": 103, "RL": 46, "RTP": 24, "RPRE": 1, "RPST": 0, "RDDQS": 0, "WL": 44, "WPRE": 2, "WPST": 0, "WR": 96, "CCD_L_slr": 16, "CCD_L_WR_slr": 64, "CCD_L_WR2_slr": 32, "CCD_M_slr": 16, "CCD_M_WR_slr": 64, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, "CCD_WR_dlr": 0, "CCD_WR_dpr": 0, "RRD_L_slr": 16, "RRD_S_slr": 8, "RRD_dlr": 0, "FAW_slr": 32, "FAW_dlr": 0, "WTR_L": 32, "WTR_M": 32, "WTR_S": 8, "RFC1_slr": 624, "RFC2_slr": 416, "RFC1_dlr": 0, "RFC2_dlr": 0, "RFC1_dpr": 0, "RFC2_dpr": 0, "RFCsb_slr": 368, "RFCsb_dlr": 0, "REFI1": 12480, "REFI2": 6240, "REFISB": 3120, "REFSBRD_slr": 96, "REFSBRD_dlr": 0, "RTRS": 2, "CPDED": 16, "PD": 24, "XP": 24, "ACTPDEN": 2, "PRPDEN": 2, "REFPDEN": 2, "clkMhz": 3200 } } }