{ "memspec": { "memarchitecturespec": { "burstLength": 16, "dataRate": 2, "nbrOfBankGroups": 8, "nbrOfBanks": 16, "nbrOfColumns": 1024, "nbrOfRanks": 1, "nbrOfDIMMRanks": 1, "nbrOfPhysicalRanks": 1, "nbrOfLogicalRanks": 1, "nbrOfRows": 65536, "width": 8, "nbrOfDevices": 4, "nbrOfChannels": 2, "cmdMode": 1, "refMode": 1, "RAAIMT" : 16, "RAAMMT" : 96, "RAADEC" : 16 }, "memoryId": "JEDEC_2x4x1Gbx8_DDR5-4800A", "memoryType": "DDR5", "memtimingspec": { "RCD": 34, "PPD": 2, "RP": 34, "RAS": 77, "RL": 34, "RTP": 18, "RPRE": 1, "RPST": 0, "RDDQS": 0, "WL": 32, "WPRE": 2, "WPST": 0, "WR": 72, "CCD_L_slr": 12, "CCD_L_WR_slr": 48, "CCD_L_WR2_slr": 24, "CCD_M_slr": 12, "CCD_M_WR_slr": 48, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, "CCD_WR_dlr": 0, "CCD_WR_dpr": 0, "RRD_L_slr": 12, "RRD_S_slr": 8, "RRD_dlr": 0, "FAW_slr": 32, "FAW_dlr": 0, "WTR_L": 24, "WTR_M": 24, "WTR_S": 6, "RFC1_slr": 468, "RFC2_slr": 312, "RFC1_dlr": 0, "RFC2_dlr": 0, "RFC1_dpr": 0, "RFC2_dpr": 0, "RFCsb_slr": 276, "RFCsb_dlr": 0, "REFI1": 9360, "REFI2": 4680, "REFISB": 2340, "REFSBRD_slr": 72, "REFSBRD_dlr": 0, "RTRS": 2, "CPDED": 12, "PD": 18, "XP": 18, "ACTPDEN": 2, "PRPDEN": 2, "REFPDEN": 2, "clkMhz": 2400 } } }