#include <gtest/gtest.h>
#include "core/scheduling/CommandGenerator.h"
#include "testUtils.h"
#include <vector>

using namespace controller;
using namespace common;
using namespace std;

constexpr unsigned int numberOfBanks = 8;

constexpr tlm::tlm_command READ = tlm::tlm_command::TLM_READ_COMMAND;
constexpr tlm::tlm_command WRITE = tlm::tlm_command::TLM_WRITE_COMMAND;

TEST(CommandGenerator, ReadAndWriteWithRowHit)
{
	ControllerState state(numberOfBanks);
	CommandGenerator generator(state);

	state.bankStates.openRowInRowBuffer(Bank(0), Row(3));

	auto hit_read = createDummyPayload(Thread(0), Bank(0), Row(3), Column(1), READ);
	auto hit_write = createDummyPayload(Thread(0), Bank(0), Row(3), Column(1), WRITE);


	vector<Command> expected_read ({Command::Read});
	vector<Command> expected_write ({Command::Write});

	EXPECT_EQ(expected_read, generator.generateCommandSequence(hit_read.get()));
	EXPECT_EQ(expected_write, generator.generateCommandSequence(hit_write.get()));
}

TEST(CommandGenerator, ReadAndWriteWithRowMiss)
{
	ControllerState state(numberOfBanks);
	CommandGenerator generator(state);

	state.bankStates.openRowInRowBuffer(Bank(0), Row(3));

	auto miss_read = createDummyPayload(Thread(0), Bank(0), Row(4), Column(1), READ);
	auto miss_write = createDummyPayload(Thread(0), Bank(0), Row(4), Column(1), WRITE);


	vector<Command> expected_read ({Command::Precharge, Command::Activate, Command::Read});
	vector<Command> expected_write ({Command::Precharge, Command::Activate, Command::Write});

	EXPECT_EQ(expected_read, generator.generateCommandSequence(miss_read.get()));
	EXPECT_EQ(expected_write, generator.generateCommandSequence(miss_write.get()));
}

TEST(CommandGenerator, ReadAndWriteWithBankMiss)
{
	ControllerState state(numberOfBanks);
	CommandGenerator generator(state);

	state.bankStates.openRowInRowBuffer(Bank(0), Row(3));

	auto miss_read = createDummyPayload(Thread(0), Bank(1), Row(4), Column(1), READ);
	auto miss_write = createDummyPayload(Thread(0), Bank(1), Row(4), Column(1), WRITE);


	vector<Command> expected_read ({Command::Activate, Command::Read});
	vector<Command> expected_write ({Command::Activate, Command::Write});

	EXPECT_EQ(expected_read, generator.generateCommandSequence(miss_read.get()));
	EXPECT_EQ(expected_write, generator.generateCommandSequence(miss_write.get()));
}