{
    "memspec": {
        "memarchitecturespec": {
            "burstLength": 16,
            "dataRate": 8,
            "nbrOfBankGroups": 4,
            "nbrOfBanks": 16,
            "nbrOfColumns": 1024,
            "nbrOfRows": 65536,
            "nbrOfRanks": 1,
            "nbrOfDevices": 1,
            "nbrOfChannels": 1,
            "width": 16,
            "per2BankOffset": 8,
            "WCKalwaysOn": false,
            "maxBurstLength": 16
        },
        "mempowerspec": {
            "vdd1": 1.2,
            "idd01": 1e-3,
            "idd2n1": 1e-3,
            "idd3n1": 1e-3,
            "idd4r1": 1e-3,
            "idd4w1": 1e-3,
            "idd51": 1e-3,
            "idd5pb1": 1e-3,
            "idd61": 1e-3,
            "idd6ds1": 1e-3,
            "idd2p1": 1e-3,
            "idd3p1": 1e-3,
            "vdd2h": 1.2,
            "idd02h": 1e-3,
            "idd2n2h": 1e-3,
            "idd3n2h": 1e-3,
            "idd4r2h": 1e-3,
            "idd4w2h": 1e-3,
            "idd52h": 1e-3,
            "idd5pb2h": 1e-3,
            "idd62h": 1e-3,
            "idd6ds2h": 1e-3,
            "idd2p2h": 1e-3,
            "idd3p2h": 1e-3,
            "vdd2l": 1.2,
            "idd02l": 1e-3,
            "idd2n2l": 1e-3,
            "idd3n2l": 1e-3,
            "idd4r2l": 1e-3,
            "idd4w2l": 1e-3,
            "idd52l": 1e-3,
            "idd5pb2l": 1e-3,
            "idd62l": 1e-3,
            "idd6ds2l": 1e-3,
            "idd2p2l": 1e-3,
            "idd3p2l": 1e-3,
            "vddq": 1.2,
            "iBeta_vdd1": 0.0,
            "iBeta_vdd2h": 0.0,
            "iBeta_vdd2l": 0.0
        },
        "bankwisespec": {
            "factRho": 1
        },
        "memimpedancespec": {
            "ck_termination": true,
            "ck_R_eq": 1e6,
            "ck_dyn_E": 1e-12,

            "ca_termination": true,
            "ca_R_eq": 1e6,
            "ca_dyn_E": 1e-12,

            "rdq_termination": true,
            "rdq_R_eq": 1e6,
            "rdq_dyn_E": 1e-12,
            "wdq_termination": true,
            "wdq_R_eq": 1e6,
            "wdq_dyn_E": 1e-12,

            "wck_termination": true,
            "wck_R_eq": 1e6,
            "wck_dyn_E": 1e-12,
            "rdqs_termination": true,
            "rdqs_R_eq": 1e6,
            "rdqs_dyn_E": 1e-12,

            "rdbi_termination": true,
            "rdbi_R_eq": 1e6,
            "rdbi_dyn_E": 1e-12,

            "wdbi_termination": true,
            "wdbi_R_eq": 1e6,
            "wdbi_dyn_E": 1e-12
        },
        "memoryId": "JEDEC_1Gbx16_BG_LPDDR5-6400",
        "memoryType": "LPDDR5",
        "memtimingspec": {
            "RCD_L": 15,
            "RCD_S": 15,
            "PPD": 2,
            "RPab": 17,
            "RPpb": 15,
            "RAS": 34,
            "RCab": 51,
            "RCpb": 48,
            "FAW": 16,
            "RRD": 4,
            "RL": 17,
            "WCK2CK": 2,
            "WCK2DQO": 1,
            "RBTP": 4,
            "RPRE": 0,
            "RPST": 0,
            "WL": 9,
            "WCK2DQI": 0,
            "WPRE": 0,
            "WPST": 0,
            "WR": 28,
            "WTR_L": 10,
            "WTR_S": 5,
            "CCDMW": 16,
            "REFI": 3124,
            "REFIpb": 390,
            "RFCab": 224,
            "RFCpb": 112,
            "RTRS": 1,
            "BL_n_min_16": 2,
            "BL_n_max_16": 4,
            "BL_n_L_16": 4,
            "BL_n_S_16": 2,
            "BL_n_min_32": 6,
            "BL_n_max_32": 8,
            "BL_n_L_32": 8,
            "BL_n_S_32": 2,
            "pbR2act": 6,
            "pbR2pbR": 72,
            "tCK": 1250e-12
        }
    }
}