{ "simulation": { "addressmapping": { "PSEUDOCHANNEL_BIT":[ 29 ], "BANKGROUP_BIT":[ 27, 28 ], "BANK_BIT": [ 25, 26 ], "BYTE_BIT": [ 0, 1 ], "COLUMN_BIT": [ 2, 3, 4, 5, 6, 7, 8 ], "ROW_BIT": [ 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24 ] }, "mcconfig": { "PagePolicy": "Open", "Scheduler": "Fifo", "RequestBufferSize": 8, "CmdMux": "Strict", "RespQueue": "Fifo", "RefreshPolicy": "PerBank", "RefreshMaxPostponed": 0, "RefreshMaxPulledin": 0, "PowerDownPolicy": "NoPowerDown", "PowerDownTimeout": 100 }, "memspec": { "memarchitecturespec": { "burstLength": 8, "dataRate": 4, "nbrOfBankGroups": 4, "nbrOfBanks": 16, "nbrOfColumns": 128, "nbrOfPseudoChannels": 2, "nbrOfStacks": 1, "nbrOfRows": 65536, "width": 32, "nbrOfDevices": 1, "nbrOfChannels": 1, "RAAIMT" : 16, "RAAMMT" : 96, "RAADEC" : 16, "maxBurstLength": 8 }, "memoryId": "", "memoryType": "HBM3", "memtimingspec": { "CCDL": 4, "CCDS": 2, "CCDR": 3, "CKE": 8, "DQSCK": 1, "FAW": 16, "PL": 0, "PPD": 2, "RAS": 28, "RC": 42, "RCDRD": 12, "RCDWR": 6, "REFI": 3900, "REFIPB": 122, "RFC": 260, "RFCPB": 96, "RL": 17, "RP": 14, "RRDL": 6, "RRDS": 4, "RREFD": 8, "RTP": 5, "RTW": 18, "WL": 12, "WR": 23, "WTRL": 9, "WTRS": 4, "XP": 8, "XS": 260, "tCK": 625e-12 } }, "simconfig": { "AddressOffset": 0, "CheckTLM2Protocol": false, "DatabaseRecording": true, "Debug": false, "ECCControllerMode": "Disabled", "EnableWindowing": false, "ErrorCSVFile": "", "ErrorChipSeed": 42, "PowerAnalysis": false, "SimulationName": "hbm3", "SimulationProgressBar": true, "StoreMode": "NoStorage", "ThermalSimulation": false, "UseMalloc": false, "WindowSize": 1000 }, "simulationid": "hbm3-example", "tracesetup": [ { "type": "player", "clkMhz": 1600, "dataLength": 32, "name": "traces/trace1_test4.stl" }, { "type": "player", "clkMhz": 1600, "dataLength": 32, "name": "traces/trace2_test4.stl" } ] } }