{
    "memspec": {
        "memarchitecturespec": {
            "burstLength": 4,
            "dataRate": 1,
            "nbrOfBanks": 4,
            "nbrOfColumns": 128,
            "nbrOfRanks": 1,
            "nbrOfRows": 4096,
            "width": 128,
            "nbrOfDevices": 1,
            "nbrOfChannels": 4,
            "maxBurstLength": 4
        },
        "memoryId": "JEDEC_256Mb_WIDEIO_SDR-200_128bit",
        "memoryType": "WIDEIO_SDR",
        "mempowerspec": {
            "idd0": 5.88e-3,
            "idd02": 21.18e-3,
            "idd2n": 0.13e-3,
            "idd2n2": 4.04e-3,
            "idd2p0": 0.05e-3,
            "idd2p02": 0.17e-3,
            "idd2p1": 0.05e-3,
            "idd2p12": 0.17e-3,
            "idd3n": 0.52e-3,
            "idd3n2": 6.55e-3,
            "idd3p0": 0.25e-3,
            "idd3p02": 1.49e-3,
            "idd3p1": 0.25e-3,
            "idd3p12": 1.49e-3,
            "idd4r": 1.41e-3,
            "idd4r2": 85.73e-3,
            "idd4w": 1.42e-3,
            "idd4w2": 60.79e-3,
            "idd5": 14.43e-3,
            "idd52": 48.17e-3,
            "idd6": 0.07e-3,
            "idd62": 0.27e-3,
            "vdd": 1.8,
            "vdd2": 1.2
        },
        "memtimingspec": {
            "AC": 1,
            "CCD_R": 2,
            "CCD_W": 1,
            "CKE": 3,
            "CKESR": 3,
            "DQSCK": 1,
            "RAS": 9,
            "RC": 12,
            "RCD": 4,
            "REFI": 3120,
            "RFC": 18,
            "RL": 3,
            "RP": 4,
            "RRD": 2,
            "TAW": 10,
            "WL": 1,
            "WR": 3,
            "WTR": 3,
            "XP": 2,
            "XSR": 20,
            "RTRS": 1,
            "tCK": 5000e-12
        }
    }
}