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60b2bcbffa
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Fix DDR5 write-to-write delay in TimingChecker
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2023-04-11 14:08:32 +02:00 |
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49954df6ee
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Add tCCD_M DDR5 timings, MemSpecs still incomplete
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2023-04-06 10:38:48 +02:00 |
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Lukas Steiner
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b086fa985d
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Change names of LPDDR5 timings from tRCDRD/tRCDWR to tRCD_L/tRCD_S.
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2023-03-30 15:06:17 +02:00 |
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5d7171e537
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Add LPDDR5X configurations and separate tRCD into tRCDRD and tRCDWR
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2023-03-29 16:49:15 +02:00 |
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Lukas Steiner
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b29c67481d
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Merge branch 'fix/plots' into 'develop'
Update plots python script to new database layout
See merge request ems/astdm/modeling.dram/dram.sys.5!11
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2023-03-24 13:24:49 +00:00 |
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6cb2128612
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Update plots python script to new database layout
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2023-03-24 09:18:06 +01:00 |
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Lukas Steiner
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bb99b9e883
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Add fix for LP5 rank2rank timings.
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2023-03-20 16:51:36 +01:00 |
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b3277b2e52
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Revert the design choice of making the PythonCaller a static singleton
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2023-03-07 11:39:16 +01:00 |
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Lukas Steiner
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e848d776cc
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Fix Trace Analyzer cmake.
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2023-02-22 17:11:17 +01:00 |
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Lukas Steiner
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fe08c833c8
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Make Trace Analyzer run again.
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2023-02-22 15:18:58 +01:00 |
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Lukas Steiner
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1bd6d61d23
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Adapt more paths.
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2023-02-22 15:18:17 +01:00 |
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Thomas Psota
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f434026ccd
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Added extension mechanism and ported DDR5, LPDDR5, HBM3, TraceAnalyzer
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2023-02-09 14:22:34 +01:00 |
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