|
|
0ec6ea79ad
|
Migrate from clkMhz to tCK entry in memspecs
|
2024-02-23 12:04:22 +01:00 |
|
|
|
b30df49d67
|
Use tCCDMW for masked write in LPDDR4
|
2023-08-21 09:26:05 +02:00 |
|
|
|
156c558e32
|
Resize sample HBM3 memspec and address mapping to 8 Gib
|
2023-04-21 11:14:41 +02:00 |
|
|
|
85f944fe58
|
Rename RAACDR to RAADEC
|
2023-04-21 11:10:09 +02:00 |
|
|
|
949cf944bc
|
Update tCCD_M timings in memspecs for DDR5
|
2023-04-11 14:27:26 +02:00 |
|
|
|
49954df6ee
|
Add tCCD_M DDR5 timings, MemSpecs still incomplete
|
2023-04-06 10:38:48 +02:00 |
|
Lukas Steiner
|
b086fa985d
|
Change names of LPDDR5 timings from tRCDRD/tRCDWR to tRCD_L/tRCD_S.
|
2023-03-30 15:06:17 +02:00 |
|
|
|
5d7171e537
|
Add LPDDR5X configurations and separate tRCD into tRCDRD and tRCDWR
|
2023-03-29 16:49:15 +02:00 |
|
Lukas Steiner
|
c4ca3d71d7
|
Reorganize config files, remove unused config.
|
2023-02-23 17:02:21 +01:00 |
|
