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49954df6ee
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Add tCCD_M DDR5 timings, MemSpecs still incomplete
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2023-04-06 10:38:48 +02:00 |
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Lukas Steiner
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b086fa985d
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Change names of LPDDR5 timings from tRCDRD/tRCDWR to tRCD_L/tRCD_S.
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2023-03-30 15:06:17 +02:00 |
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5d7171e537
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Add LPDDR5X configurations and separate tRCD into tRCDRD and tRCDWR
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2023-03-29 16:49:15 +02:00 |
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Lukas Steiner
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bb99b9e883
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Add fix for LP5 rank2rank timings.
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2023-03-20 16:51:36 +01:00 |
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Lukas Steiner
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1bd6d61d23
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Adapt more paths.
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2023-02-22 15:18:17 +01:00 |
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Thomas Psota
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f434026ccd
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Added extension mechanism and ported DDR5, LPDDR5, HBM3, TraceAnalyzer
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2023-02-09 14:22:34 +01:00 |
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