15 Commits

Author SHA1 Message Date
1ef2b3bd9c chore: update DRAMUtils version
Update the DRAMUtils version and fix all configs that now require DBI
parameters for the memimpedance spec.
2025-11-21 16:02:11 +01:00
591b5b65c2 Move closed-source standard configs to extensions 2025-08-06 08:44:15 +02:00
marcomoerz
4120e9c35b Integrate DRAMUtils and new DRAMPower 2025-05-09 16:45:54 +02:00
939fc90f98 Remove hard-coded subdirectory paths for configs
Previously, the subdirectories in which the sub-json files were searched
in were hardcoded. Now, DRAMSys simply searches in the directory of the
base config, making this approach more flexible.
2025-04-15 14:56:35 +02:00
6861576550 Implement tCCDR for HBM2 and fix bug with SID 2025-02-21 14:18:30 +01:00
7a8633d36e Implement stack ID for HBM3 2025-01-13 15:36:05 +01:00
0ec6ea79ad Migrate from clkMhz to tCK entry in memspecs 2024-02-23 12:04:22 +01:00
b30df49d67 Use tCCDMW for masked write in LPDDR4 2023-08-21 09:26:05 +02:00
156c558e32 Resize sample HBM3 memspec and address mapping to 8 Gib 2023-04-21 11:14:41 +02:00
85f944fe58 Rename RAACDR to RAADEC 2023-04-21 11:10:09 +02:00
949cf944bc Update tCCD_M timings in memspecs for DDR5 2023-04-11 14:27:26 +02:00
49954df6ee Add tCCD_M DDR5 timings, MemSpecs still incomplete 2023-04-06 10:38:48 +02:00
Lukas Steiner
b086fa985d Change names of LPDDR5 timings from tRCDRD/tRCDWR to tRCD_L/tRCD_S. 2023-03-30 15:06:17 +02:00
5d7171e537 Add LPDDR5X configurations and separate tRCD into tRCDRD and tRCDWR 2023-03-29 16:49:15 +02:00
Lukas Steiner
c4ca3d71d7 Reorganize config files, remove unused config. 2023-02-23 17:02:21 +01:00