From f74386a38ee622c61dbec96999a0e78640f0a02d Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Tue, 29 Jul 2014 15:18:12 +0200 Subject: [PATCH 1/9] Cleaned code --- dram/src/simulation/Dram.h | 1 - 1 file changed, 1 deletion(-) diff --git a/dram/src/simulation/Dram.h b/dram/src/simulation/Dram.h index 69c882ba..825764b7 100644 --- a/dram/src/simulation/Dram.h +++ b/dram/src/simulation/Dram.h @@ -41,7 +41,6 @@ struct Dram: sc_module tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw); MemorySpecification memSpec(MemSpecParser::getMemSpecFromXML(Configuration::getInstance().memspecUri)); - //MemorySpecification::getMemSpecFromXML(Configuration::getInstance().memspecUri)); DRAMPower = new libDRAMPower( memSpec, 1,1,1,0,0 ); } From d402933502c27d2e9721286163eacc4f6b558a18 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Tue, 29 Jul 2014 16:21:07 +0200 Subject: [PATCH 2/9] New metric "memory utilization" defined --- dram/resources/scripts/metrics.py | 33 ++++++++++++++++++++----------- 1 file changed, 22 insertions(+), 11 deletions(-) diff --git a/dram/resources/scripts/metrics.py b/dram/resources/scripts/metrics.py index 7f780cca..8f448db1 100644 --- a/dram/resources/scripts/metrics.py +++ b/dram/resources/scripts/metrics.py @@ -38,17 +38,17 @@ def getClock(connection): result = cursor.fetchone() return result[0] -@metric -def latency_histogram(connection): - cursor = connection.cursor() - cursor.execute("SELECT ((p2.PhaseEnd - p1.PhaseEnd)/1000) FROM Transactions t, Phases p1, Phases p2 WHERE t.id = p1.Transact and t.id = p2.Transact and p1.PhaseName = \"REQ\" and p2.PhaseName = \"RESP\" ") - result = cursor.fetchall() - #result.sort() - #print(max(result)[0]) - import matplotlib.pyplot as plt - plt.hist(result, bins=max(result)[0], histtype='barstacked') - plt.savefig('hist.png') - return "Saved as hist.png" +#@metric +#def latency_histogram(connection): +# cursor = connection.cursor() +# cursor.execute("SELECT ((p2.PhaseEnd - p1.PhaseEnd)/1000) FROM Transactions t, Phases p1, Phases p2 WHERE t.id = p1.Transact and t.id = p2.Transact and p1.PhaseName = \"REQ\" and p2.PhaseName = \"RESP\" ") +# result = cursor.fetchall() +# #result.sort() +# #print(max(result)[0]) +# import matplotlib.pyplot as plt +# plt.hist(result, bins=max(result)[0], histtype='barstacked') +# plt.savefig('hist.png') +# return "Saved as hist.png" @metric def average_response_latency_in_ns(connection): @@ -59,6 +59,17 @@ def average_response_latency_in_ns(connection): result = cursor.fetchone() return round(result[0],1) +@metric +def memory_utilisation(connection): + cursor = connection.cursor() + cursor.execute(""" SELECT sum(DataStrobeEnd - DataStrobeBegin) FROM transactions """) + active = cursor.fetchone() + cursor = connection.cursor() + cursor.execute(""" SELECT max(DataStrobeEnd) FROM Transactions """) + total = cursor.fetchone() + return str(active[0]/total[0]*100)+"%" + + def refreshMissDecision(connection,calculatedMetrics): cursor = connection.cursor() cursor.execute("""SELECT phases.ID,PhaseBegin,PhaseEnd,TBank FROM Phases INNER JOIN transactions on transactions.id = phases.transact WHERE PhaseName='AUTO_REFRESH' """) From 62e7c8e65ec9faa68b47db5c794427b631f32477 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Tue, 29 Jul 2014 16:21:59 +0200 Subject: [PATCH 3/9] Changed to the lates DRAMPower --- dram/src/simulation/Dram.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dram/src/simulation/Dram.h b/dram/src/simulation/Dram.h index 825764b7..f4995534 100644 --- a/dram/src/simulation/Dram.h +++ b/dram/src/simulation/Dram.h @@ -41,7 +41,7 @@ struct Dram: sc_module tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw); MemorySpecification memSpec(MemSpecParser::getMemSpecFromXML(Configuration::getInstance().memspecUri)); - DRAMPower = new libDRAMPower( memSpec, 1,1,1,0,0 ); + DRAMPower = new libDRAMPower( memSpec, 0 ); } ~Dram() From 76ab26e2d79fba9f525ed459f3c683f812fae072 Mon Sep 17 00:00:00 2001 From: Janik Schlemminger Date: Wed, 30 Jul 2014 03:01:06 +0200 Subject: [PATCH 4/9] refresh splitted in REFA REFB --- .../analyzer/businessObjects/phases/phase.cpp | 8 ++- .../analyzer/businessObjects/phases/phase.h | 19 ++++++ .../businessObjects/phases/phasefactory.cpp | 6 +- dram/dramSys/dramSys.pro | 14 ++-- dram/resources/configs/memconfigs/fifo.xml | 2 +- dram/resources/simulations/sim-batch.xml | 2 +- dram/src/common/TlmRecorder.cpp | 3 +- dram/src/common/protocol.h | 7 +- dram/src/controller/Controller.h | 16 +++-- dram/src/simulation/Dram.h | 66 +++++++++++-------- 10 files changed, 95 insertions(+), 48 deletions(-) diff --git a/analyzer/analyzer/businessObjects/phases/phase.cpp b/analyzer/analyzer/businessObjects/phases/phase.cpp index a3e467f4..71ebdcf3 100644 --- a/analyzer/analyzer/businessObjects/phases/phase.cpp +++ b/analyzer/analyzer/businessObjects/phases/phase.cpp @@ -28,7 +28,13 @@ void Phase::draw(QPainter *painter, const QwtScaleMap &xMap, const QwtScaleMap & painter->setPen(pen); } - drawPhaseSymbol(span.Begin(), span.End(), getYVal(drawingProperties), drawingProperties.drawText,getPhaseSymbol(), painter, xMap, yMap); + if(!isBankwise()) + { + for(unsigned int i=0; i PhaseFactory::CreatePhase(ID id, const QString& dbPhaseName,co return shared_ptr(new ACT(id, span,trans,{Timespan(span.Begin(),span.Begin()+clk)},std::shared_ptr())); else if(dbPhaseName == "PRE_ALL") return shared_ptr(new PRECHARGE_ALL(id,span,trans,{Timespan(span.Begin(),span.Begin()+clk)},std::shared_ptr())); - else if(dbPhaseName == "AUTO_REFRESH") - return shared_ptr(new AUTO_REFRESH(id, span,trans,{Timespan(span.Begin(),span.Begin()+clk)},std::shared_ptr())); + else if(dbPhaseName == "REFA") + return shared_ptr(new REFA(id, span,trans,{Timespan(span.Begin(),span.Begin()+clk)},std::shared_ptr())); + else if(dbPhaseName == "REFB") + return shared_ptr(new REFB(id, span,trans,{Timespan(span.Begin(),span.Begin()+clk)},std::shared_ptr())); else if(dbPhaseName == "RD") return shared_ptr(new RD(id, span,trans,{Timespan(span.Begin(),span.Begin()+clk)},std::shared_ptr(new Timespan(trans->SpanOnDataStrobe())))); diff --git a/dram/dramSys/dramSys.pro b/dram/dramSys/dramSys.pro index f0052a93..6e5bbe27 100644 --- a/dram/dramSys/dramSys.pro +++ b/dram/dramSys/dramSys.pro @@ -8,24 +8,24 @@ LIBS += -L/opt/systemc/lib-linux64 -lsystemc LIBS += -L/opt/boost/lib -lboost_filesystem -lboost_system LIBS += -L/opt/sqlite3/lib -lsqlite3 LIBS += -lpthread -LIBS += -lxerces-c -LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampowerxml -LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampower +#LIBS += -lxerces-c +#LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampowerxml +#LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampower INCLUDEPATH += /opt/systemc/include INCLUDEPATH += /opt/boost/include INCLUDEPATH += /opt/sqlite3/include -INCLUDEPATH += ../src/common/third_party/DRAMPower/src -INCLUDEPATH += ../src/common/third_party/DRAMPower/src/libdrampower +#INCLUDEPATH += ../src/common/third_party/DRAMPower/src +#INCLUDEPATH += ../src/common/third_party/DRAMPower/src/libdrampower DEFINES += TIXML_USE_STL DEFINES += SC_INCLUDE_DYNAMIC_PROCESSES -DEFINES += USE_XERCES=1 +#DEFINES += USE_XERCES=1 QMAKE_CXXFLAGS += -std=c++11 QMAKE_CXXFLAGS += -isystem /opt/systemc/include QMAKE_CXXFLAGS += -isystem /opt/boost/include -QMAKE_CXXFLAGS += -iquote ../src/common/third_party/DRAMPower/src/ +#QMAKE_CXXFLAGS += -iquote ../src/common/third_party/DRAMPower/src/ SOURCES += \ ../src/common/third_party/tinyxml2.cpp \ diff --git a/dram/resources/configs/memconfigs/fifo.xml b/dram/resources/configs/memconfigs/fifo.xml index 2e23e330..603049f2 100644 --- a/dram/resources/configs/memconfigs/fifo.xml +++ b/dram/resources/configs/memconfigs/fifo.xml @@ -1,6 +1,6 @@ - + diff --git a/dram/resources/simulations/sim-batch.xml b/dram/resources/simulations/sim-batch.xml index 7b793ec0..f1c7c731 100644 --- a/dram/resources/simulations/sim-batch.xml +++ b/dram/resources/simulations/sim-batch.xml @@ -16,7 +16,7 @@ - mediabench-epic_32.stl + chstone-sha_32.stl diff --git a/dram/src/common/TlmRecorder.cpp b/dram/src/common/TlmRecorder.cpp index e6bad2d4..089f24db 100644 --- a/dram/src/common/TlmRecorder.cpp +++ b/dram/src/common/TlmRecorder.cpp @@ -191,7 +191,8 @@ void TlmRecorder::createTables(string pathToURI) void TlmRecorder::setUpTransactionTerminatingPhases() { transactionTerminatingPhases.push_back(tlm::END_RESP); - transactionTerminatingPhases.push_back(static_cast(END_AUTO_REFRESH)); + transactionTerminatingPhases.push_back(static_cast(END_REFA)); + transactionTerminatingPhases.push_back(static_cast(END_REFB)); transactionTerminatingPhases.push_back(static_cast(END_PDNP)); transactionTerminatingPhases.push_back(static_cast(END_PDNA)); transactionTerminatingPhases.push_back(static_cast(END_SREF)); diff --git a/dram/src/common/protocol.h b/dram/src/common/protocol.h index 41e5daeb..8cebad64 100755 --- a/dram/src/common/protocol.h +++ b/dram/src/common/protocol.h @@ -11,8 +11,11 @@ DECLARE_EXTENDED_PHASE(END_PRE_ALL); DECLARE_EXTENDED_PHASE(BEGIN_ACT); DECLARE_EXTENDED_PHASE(END_ACT); -DECLARE_EXTENDED_PHASE(BEGIN_AUTO_REFRESH); -DECLARE_EXTENDED_PHASE(END_AUTO_REFRESH); +DECLARE_EXTENDED_PHASE(BEGIN_REFA); +DECLARE_EXTENDED_PHASE(END_REFA); + +DECLARE_EXTENDED_PHASE(BEGIN_REFB); +DECLARE_EXTENDED_PHASE(END_REFB); // Phases for Read and Write diff --git a/dram/src/controller/Controller.h b/dram/src/controller/Controller.h index 34a1c4e8..c8462a44 100644 --- a/dram/src/controller/Controller.h +++ b/dram/src/controller/Controller.h @@ -164,7 +164,13 @@ void Controller::send(const ScheduledCommand &command, tlm_generic_pay controllerCorePEQ.notify(payload, BEGIN_WRA, command.getStart() - sc_time_stamp()); break; case Command::AutoRefresh: - controllerCorePEQ.notify(payload, BEGIN_AUTO_REFRESH, command.getStart() - sc_time_stamp()); + if(!Configuration::getInstance().BankwiseLogic) + { + if(command.getBank() == Bank(0)) + controllerCorePEQ.notify(payload, BEGIN_REFA, command.getStart() - sc_time_stamp()); + } + else + controllerCorePEQ.notify(payload, BEGIN_REFB, command.getStart() - sc_time_stamp()); break; case Command::Activate: controllerCorePEQ.notify(payload, BEGIN_ACT, command.getStart() - sc_time_stamp()); @@ -238,8 +244,10 @@ void Controller::controllerCorePEQCallback(tlm_generic_payload &payloa if (phase == BEGIN_RD || phase == BEGIN_WR) scheduleNextPayload(); - else if (phase == BEGIN_AUTO_REFRESH) - printDebugMessage("Entering auto refresh on bank " + to_string(bank.ID())); + else if (phase == BEGIN_REFB) + printDebugMessage("Entering REFB on bank " + to_string(bank.ID())); + else if (phase == BEGIN_REFA) + printDebugMessage("Entering REFA"); else if (containsPhase(phase, { BEGIN_PDNA, BEGIN_PDNP, BEGIN_SREF })) printDebugMessage("Entering PowerDown " + phaseNameToString(phase) + " on bank " + to_string(bank.ID())); else if (containsPhase(phase, { END_PDNA, END_PDNP, END_SREF })) @@ -396,7 +404,7 @@ void Controller::dramPEQCallback(tlm_generic_payload &payload, const t sendToFrontend(payload, BEGIN_RESP, SC_ZERO_TIME); scheduleNextPayload(); } - else if (phase == END_AUTO_REFRESH) + else if (phase == END_REFA || phase == END_REFB)//TODO send all to sleep for REFA?? { printDebugMessage("Finished auto refresh on bank " + to_string(bank.ID())); if(numberOfPayloadsInSystem[bank] == 0) diff --git a/dram/src/simulation/Dram.h b/dram/src/simulation/Dram.h index 69c882ba..0770e22a 100644 --- a/dram/src/simulation/Dram.h +++ b/dram/src/simulation/Dram.h @@ -19,38 +19,38 @@ #include "../common/protocol.h" #include "../common/Utils.h" #include "../common/TlmRecorder.h" -#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" -#include "../common/third_party/DRAMPower/src/xmlparser/MemSpecParser.h" -#include "../common/third_party/DRAMPower/src/MemorySpecification.h" -#include "../common/third_party/DRAMPower/src/MemCommand.h" +//#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" +//#include "../common/third_party/DRAMPower/src/xmlparser/MemSpecParser.h" +//#include "../common/third_party/DRAMPower/src/MemorySpecification.h" +//#include "../common/third_party/DRAMPower/src/MemCommand.h" using namespace std; using namespace tlm; using namespace core; -using namespace Data; +//using namespace Data; template struct Dram: sc_module { tlm_utils::simple_target_socket tSocket; - libDRAMPower *DRAMPower; + //libDRAMPower *DRAMPower; SC_CTOR(Dram) : tSocket("socket") { tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw); - MemorySpecification memSpec(MemSpecParser::getMemSpecFromXML(Configuration::getInstance().memspecUri)); - //MemorySpecification::getMemSpecFromXML(Configuration::getInstance().memspecUri)); - DRAMPower = new libDRAMPower( memSpec, 1,1,1,0,0 ); +// MemorySpecification memSpec(MemSpecParser::getMemSpecFromXML(Configuration::getInstance().memspecUri)); +// MemorySpecification::getMemSpecFromXML(Configuration::getInstance().memspecUri)); +// DRAMPower = new libDRAMPower( memSpec, 1,1,1,0,0 ); } ~Dram() { - DRAMPower->updateCounters(true); - DRAMPower->getEnergy(); - cout << "Total Energy" << "\t" << DRAMPower->mpm.energy.total_energy << endl; - cout << "Average Power" << "\t" << DRAMPower->mpm.power.average_power << endl; +// DRAMPower->updateCounters(true); +// DRAMPower->getEnergy(); +// cout << "Total Energy" << "\t" << DRAMPower->mpm.energy.total_energy << endl; +// cout << "Average Power" << "\t" << DRAMPower->mpm.power.average_power << endl; } virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& payload, tlm::tlm_phase& phase, sc_time& delay) @@ -63,43 +63,49 @@ struct Dram: sc_module if (phase == BEGIN_PRE) { - DRAMPower->doCommand(MemCommand::PRE, bank, cycle); + //DRAMPower->doCommand(MemCommand::PRE, bank, cycle); sendToController(payload, END_PRE, delay + getExecutionTime(Command::Precharge, payload)); } else if (phase == BEGIN_PRE_ALL) { - DRAMPower->doCommand(MemCommand::PREA, bank, cycle); + //DRAMPower->doCommand(MemCommand::PREA, bank, cycle); sendToController(payload, END_PRE_ALL,delay + getExecutionTime(Command::PrechargeAll, payload)); } else if (phase == BEGIN_ACT) { - DRAMPower->doCommand(MemCommand::ACT, bank, cycle); + //DRAMPower->doCommand(MemCommand::ACT, bank, cycle); sendToController(payload, END_ACT, delay + getExecutionTime(Command::Activate, payload)); } else if (phase == BEGIN_WR) { - DRAMPower->doCommand(MemCommand::WR, bank, cycle); + //DRAMPower->doCommand(MemCommand::WR, bank, cycle); sendToController(payload, END_WR, delay + getExecutionTime(Command::Write, payload)); } else if (phase == BEGIN_RD) { - DRAMPower->doCommand(MemCommand::RD, bank, cycle); + //DRAMPower->doCommand(MemCommand::RD, bank, cycle); sendToController(payload, END_RD, delay + getExecutionTime(Command::Read, payload)); } else if (phase == BEGIN_WRA) { - DRAMPower->doCommand(MemCommand::WRA, bank, cycle); + //DRAMPower->doCommand(MemCommand::WRA, bank, cycle); sendToController(payload, END_WRA, delay + getExecutionTime(Command::WriteA, payload)); } else if (phase == BEGIN_RDA) { - DRAMPower->doCommand(MemCommand::RDA, bank, cycle); + //DRAMPower->doCommand(MemCommand::RDA, bank, cycle); sendToController(payload, END_RDA, delay + getExecutionTime(Command::ReadA, payload)); } - else if (phase == BEGIN_AUTO_REFRESH) + else if (phase == BEGIN_REFA) { - DRAMPower->doCommand(MemCommand::REF, bank, cycle); - sendToController(payload, END_AUTO_REFRESH, delay + getExecutionTime(Command::AutoRefresh, payload)); + //DRAMPower->doCommand(MemCommand::REF, bank, cycle); + sendToController(payload, END_REFA, delay + getExecutionTime(Command::AutoRefresh, payload)); + } + + else if (phase == BEGIN_REFB) + { + //DRAMPower->doCommand(MemCommand::REF, bank, cycle); + sendToController(payload, END_REFB, delay + getExecutionTime(Command::AutoRefresh, payload)); } //Powerdown phases have to be started and ended by the controller, because they do not have a fixed length @@ -109,7 +115,7 @@ struct Dram: sc_module { if(bank == 0) { - DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle); + //DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle); } } } @@ -119,7 +125,7 @@ struct Dram: sc_module { if(bank == 0) { - DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle); + //DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle); } } } @@ -129,7 +135,7 @@ struct Dram: sc_module { if(bank == 0) { - DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle); + //DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle); } } } @@ -139,17 +145,17 @@ struct Dram: sc_module { if(bank == 0) { - DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle); + //DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle); } } } else if (phase == BEGIN_SREF) { - DRAMPower->doCommand(MemCommand::SREN, bank, cycle); + //DRAMPower->doCommand(MemCommand::SREN, bank, cycle); } else if (phase == END_SREF) { - DRAMPower->doCommand(MemCommand::SREX, bank, cycle); + //DRAMPower->doCommand(MemCommand::SREX, bank, cycle); } else { @@ -172,4 +178,6 @@ struct Dram: sc_module }; + + #endif /* DRAM_H_ */ From 74456e530d344971ba88acd54754bc92b89a7fbc Mon Sep 17 00:00:00 2001 From: schlemmi Date: Wed, 30 Jul 2014 03:04:57 +0200 Subject: [PATCH 5/9] Update README.md --- README.md | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/README.md b/README.md index 4eabcd46..59e654e9 100644 --- a/README.md +++ b/README.md @@ -3,21 +3,9 @@ de.uni-kl.ems.dram.vp.system Generic DRAM controller -#Setup with Eclipse +#Setup with QTCreator -1. Start Eclipse ($eclipse) -2. -> Import - -> Git - -> Projects from Git - -> Existing Local Repository - -> Add Path to $dram.vp.system - -> Import Existing Projects - -> Finish - -3. Configure Eclipse: - -> Run Configurations - -> Environment - -> Variable: LD_LIBRARY_PATH = /opt/systemc/lib-linux64/:/opt/gcc/lib64 +needs update! From 2f9cd66a73343d1c0d2cd8c9b83082bc0ac2ef04 Mon Sep 17 00:00:00 2001 From: Janik Schlemminger Date: Wed, 30 Jul 2014 23:37:56 +0200 Subject: [PATCH 6/9] Powerdowns bankwise have own command in protocoll now. one command for all banks on bank 0. --- .../analyzer/businessObjects/phases/phase.cpp | 2 +- .../analyzer/businessObjects/phases/phase.h | 41 +++++++++-- .../businessObjects/phases/phasefactory.cpp | 11 ++- dram/resources/configs/memconfigs/fifo.xml | 2 +- dram/src/common/TlmRecorder.cpp | 3 + dram/src/controller/Controller.h | 70 +++++++++++++++---- dram/src/simulation/Dram.h | 64 ++++++++--------- 7 files changed, 135 insertions(+), 58 deletions(-) diff --git a/analyzer/analyzer/businessObjects/phases/phase.cpp b/analyzer/analyzer/businessObjects/phases/phase.cpp index 71ebdcf3..3a5827b7 100644 --- a/analyzer/analyzer/businessObjects/phases/phase.cpp +++ b/analyzer/analyzer/businessObjects/phases/phase.cpp @@ -97,7 +97,7 @@ Qt::BrushStyle Phase::getBrushStyle() const bool Phase::isSelected(traceTime time, double yVal, const TraceDrawingProperties& drawingproperties) const { - if (span.contains(time) && fabs(yVal-getYVal(drawingproperties))<=hexagonHeigth) + if (span.contains(time) && (!this->isBankwise() || fabs(yVal-getYVal(drawingproperties))<=hexagonHeigth)) return true; if (spanOnDataBus && spanOnDataBus->contains(time) && fabs(yVal-drawingproperties.yValDataBus)<=hexagonHeigth) return true; diff --git a/analyzer/analyzer/businessObjects/phases/phase.h b/analyzer/analyzer/businessObjects/phases/phase.h index 5b2be3de..8c643849 100644 --- a/analyzer/analyzer/businessObjects/phases/phase.h +++ b/analyzer/analyzer/businessObjects/phases/phase.h @@ -164,42 +164,71 @@ protected: virtual std::vector getTimesOnCommandBus() const {return {span.Begin()};} virtual QColor getColor(const TraceDrawingProperties &drawingProperties) const override {Q_UNUSED(drawingProperties) return getPhaseColor();} virtual QColor getPhaseColor() const override {return ColorGenerator::getColor(10);} + virtual bool isBankwise() const {return false;} }; -class PDNA : public Phase +class PDNAB : public Phase { public: using Phase::Phase; protected: - virtual QString Name() const override {return "PDNA";} + virtual QString Name() const override {return "PDNAB";} virtual Qt::BrushStyle getBrushStyle() const override {return Qt::Dense6Pattern;} virtual QColor getColor(const TraceDrawingProperties &drawingProperties) const override {Q_UNUSED(drawingProperties) return getPhaseColor();} virtual QColor getPhaseColor() const override {return QColor(Qt::black);} virtual Phase::PhaseSymbol getPhaseSymbol() const override {return PhaseSymbol::Rect;} }; -class PDNP : public Phase +class PDNA : public PDNAB +{ +public: + using PDNAB::PDNAB; +protected: + virtual QString Name() const override {return "PDNA";} + virtual bool isBankwise() const {return false;} +}; + +class PDNPB : public Phase { public: using Phase::Phase; protected: - virtual QString Name() const override {return "PDNP";} + virtual QString Name() const override {return "PDNPB";} virtual Qt::BrushStyle getBrushStyle() const override{return Qt::Dense4Pattern;} virtual QColor getColor(const TraceDrawingProperties &drawingProperties) const override {Q_UNUSED(drawingProperties) return getPhaseColor();} virtual QColor getPhaseColor() const override {return QColor(Qt::black);} virtual Phase::PhaseSymbol getPhaseSymbol() const override {return PhaseSymbol::Rect;} }; -class SREF : public Phase +class PDNP : public PDNPB +{ +public: + using PDNPB::PDNPB; +protected: + virtual QString Name() const override {return "PDNP";} + virtual bool isBankwise() const {return false;} +}; + +class SREFB : public Phase { public: using Phase::Phase; protected: - virtual QString Name() const final {return "SREF";} + virtual QString Name() const {return "SREFB";} virtual Qt::BrushStyle getBrushStyle() const {return Qt::Dense1Pattern;} virtual QColor getColor(const TraceDrawingProperties &drawingProperties) const override {Q_UNUSED(drawingProperties) return getPhaseColor();} virtual QColor getPhaseColor() const override {return QColor(Qt::black);} virtual Phase::PhaseSymbol getPhaseSymbol() const override {return PhaseSymbol::Rect;} }; +class SREF : public SREFB +{ +public: + using SREFB::SREFB; +protected: + virtual QString Name() const override {return "SREF";} + virtual bool isBankwise() const {return false;} +}; + + #endif // BANKPHASE_H diff --git a/analyzer/analyzer/businessObjects/phases/phasefactory.cpp b/analyzer/analyzer/businessObjects/phases/phasefactory.cpp index f5ebd1a4..efcf69da 100644 --- a/analyzer/analyzer/businessObjects/phases/phasefactory.cpp +++ b/analyzer/analyzer/businessObjects/phases/phasefactory.cpp @@ -35,13 +35,18 @@ shared_ptr PhaseFactory::CreatePhase(ID id, const QString& dbPhaseName,co return shared_ptr(new WR(id, span,trans,{Timespan(span.Begin(),span.Begin()+clk)},std::shared_ptr(new Timespan(trans->SpanOnDataStrobe())))); else if(dbPhaseName == "WRA") return shared_ptr(new WRA(id, span,trans,{Timespan(span.Begin(),span.Begin()+clk)},std::shared_ptr(new Timespan(trans->SpanOnDataStrobe())))); - - else if(dbPhaseName == "SREF") - return shared_ptr(new SREF(id, span, trans,{Timespan(span.Begin(),span.Begin()+clk),Timespan(span.End()-clk,span.End())},std::shared_ptr())); else if(dbPhaseName == "PDNA") return shared_ptr(new PDNA(id, span,trans, {Timespan(span.Begin(),span.Begin()+clk),Timespan(span.End()-clk,span.End())},std::shared_ptr())); + else if(dbPhaseName == "PDNAB") + return shared_ptr(new PDNAB(id, span,trans, {Timespan(span.Begin(),span.Begin()+clk),Timespan(span.End()-clk,span.End())},std::shared_ptr())); else if(dbPhaseName == "PDNP") return shared_ptr(new PDNP(id, span,trans, {Timespan(span.Begin(),span.Begin()+clk),Timespan(span.End()-clk,span.End())},std::shared_ptr())); + else if(dbPhaseName == "PDNPB") + return shared_ptr(new PDNPB(id, span,trans, {Timespan(span.Begin(),span.Begin()+clk),Timespan(span.End()-clk,span.End())},std::shared_ptr())); + else if(dbPhaseName == "SREF") + return shared_ptr(new SREF(id, span, trans,{Timespan(span.Begin(),span.Begin()+clk),Timespan(span.End()-clk,span.End())},std::shared_ptr())); + else if(dbPhaseName == "SREFB") + return shared_ptr(new SREFB(id, span, trans,{Timespan(span.Begin(),span.Begin()+clk),Timespan(span.End()-clk,span.End())},std::shared_ptr())); else throw std::runtime_error("DB phasename " + dbPhaseName.toStdString() + " unkown to phasefactory"); } diff --git a/dram/resources/configs/memconfigs/fifo.xml b/dram/resources/configs/memconfigs/fifo.xml index 2e23e330..603049f2 100644 --- a/dram/resources/configs/memconfigs/fifo.xml +++ b/dram/resources/configs/memconfigs/fifo.xml @@ -1,6 +1,6 @@ - + diff --git a/dram/src/common/TlmRecorder.cpp b/dram/src/common/TlmRecorder.cpp index 089f24db..7e2d3821 100644 --- a/dram/src/common/TlmRecorder.cpp +++ b/dram/src/common/TlmRecorder.cpp @@ -196,6 +196,9 @@ void TlmRecorder::setUpTransactionTerminatingPhases() transactionTerminatingPhases.push_back(static_cast(END_PDNP)); transactionTerminatingPhases.push_back(static_cast(END_PDNA)); transactionTerminatingPhases.push_back(static_cast(END_SREF)); + transactionTerminatingPhases.push_back(static_cast(END_PDNPB)); + transactionTerminatingPhases.push_back(static_cast(END_PDNAB)); + transactionTerminatingPhases.push_back(static_cast(END_SREFB)); } void TlmRecorder::prepareSqlStatements() diff --git a/dram/src/controller/Controller.h b/dram/src/controller/Controller.h index c8462a44..8a6b9115 100644 --- a/dram/src/controller/Controller.h +++ b/dram/src/controller/Controller.h @@ -179,27 +179,63 @@ void Controller::send(const ScheduledCommand &command, tlm_generic_pay controllerCorePEQ.notify(payload, BEGIN_PRE, command.getStart() - sc_time_stamp()); break; case Command::PrechargeAll: - controllerCorePEQ.notify(payload, BEGIN_PRE_ALL, command.getStart() - sc_time_stamp()); + if(command.getBank() == Bank(0)) + controllerCorePEQ.notify(payload, BEGIN_PRE_ALL, command.getStart() - sc_time_stamp()); break; case Command::PDNA: - controllerCorePEQ.notify(payload, BEGIN_PDNA, command.getStart() - sc_time_stamp()); - break; - case Command::PDNP: - controllerCorePEQ.notify(payload, BEGIN_PDNP, command.getStart() - sc_time_stamp()); - break; - case Command::SREF: - controllerCorePEQ.notify(payload, BEGIN_SREF, command.getStart() - sc_time_stamp()); + if(!Configuration::getInstance().BankwiseLogic) + { + if(command.getBank() == Bank(0)) + controllerCorePEQ.notify(payload, BEGIN_PDNA, command.getStart() - sc_time_stamp()); + } + else + controllerCorePEQ.notify(payload, BEGIN_PDNAB, command.getStart() - sc_time_stamp()); break; case Command::PDNAX: - controllerCorePEQ.notify(payload, END_PDNA, command.getEnd() - sc_time_stamp()); + if(!Configuration::getInstance().BankwiseLogic) + { + if(command.getBank() == Bank(0)) + controllerCorePEQ.notify(payload, END_PDNA, command.getStart() - sc_time_stamp()); + } + else + controllerCorePEQ.notify(payload, END_PDNAB, command.getStart() - sc_time_stamp()); + break; + case Command::PDNP: + if(!Configuration::getInstance().BankwiseLogic) + { + if(command.getBank() == Bank(0)) + controllerCorePEQ.notify(payload, BEGIN_PDNP, command.getStart() - sc_time_stamp()); + } + else + controllerCorePEQ.notify(payload, BEGIN_PDNPB, command.getStart() - sc_time_stamp()); break; case Command::PDNPX: - controllerCorePEQ.notify(payload, END_PDNP, command.getEnd() - sc_time_stamp()); + if(!Configuration::getInstance().BankwiseLogic) + { + if(command.getBank() == Bank(0)) + controllerCorePEQ.notify(payload, END_PDNP, command.getStart() - sc_time_stamp()); + } + else + controllerCorePEQ.notify(payload, END_PDNPB, command.getStart() - sc_time_stamp()); + break; + case Command::SREF: + if(!Configuration::getInstance().BankwiseLogic) + { + if(command.getBank() == Bank(0)) + controllerCorePEQ.notify(payload, BEGIN_SREF, command.getStart() - sc_time_stamp()); + } + else + controllerCorePEQ.notify(payload, BEGIN_SREFB, command.getStart() - sc_time_stamp()); break; case Command::SREFX: - controllerCorePEQ.notify(payload, END_SREF, command.getEnd() - sc_time_stamp()); + if(!Configuration::getInstance().BankwiseLogic) + { + if(command.getBank() == Bank(0)) + controllerCorePEQ.notify(payload, END_SREF, command.getStart() - sc_time_stamp()); + } + else + controllerCorePEQ.notify(payload, END_SREFB, command.getStart() - sc_time_stamp()); break; - default: SC_REPORT_FATAL(0, "unsupported command was sent by controller"); break; @@ -248,10 +284,14 @@ void Controller::controllerCorePEQCallback(tlm_generic_payload &payloa printDebugMessage("Entering REFB on bank " + to_string(bank.ID())); else if (phase == BEGIN_REFA) printDebugMessage("Entering REFA"); - else if (containsPhase(phase, { BEGIN_PDNA, BEGIN_PDNP, BEGIN_SREF })) + else if (containsPhase(phase, { BEGIN_PDNAB, BEGIN_PDNPB, BEGIN_SREFB })) printDebugMessage("Entering PowerDown " + phaseNameToString(phase) + " on bank " + to_string(bank.ID())); - else if (containsPhase(phase, { END_PDNA, END_PDNP, END_SREF })) + else if (containsPhase(phase, { END_PDNAB, END_PDNPB, END_SREFB })) printDebugMessage("Leaving PowerDown " + phaseNameToString(phase) + " on bank " + to_string(bank.ID())); + else if (containsPhase(phase, { BEGIN_PDNA, BEGIN_PDNP, BEGIN_SREF })) + printDebugMessage("Entering PowerDown " + phaseNameToString(phase) + " on all banks"); + else if (containsPhase(phase, { END_PDNA, END_PDNP, END_SREF })) + printDebugMessage("Leaving PowerDown " + phaseNameToString(phase) + " on all banks" ); else if (containsPhase(phase, { BEGIN_RD, BEGIN_WR, BEGIN_ACT, BEGIN_PRE, BEGIN_PRE_ALL, BEGIN_RDA, BEGIN_WRA })) { } @@ -404,7 +444,7 @@ void Controller::dramPEQCallback(tlm_generic_payload &payload, const t sendToFrontend(payload, BEGIN_RESP, SC_ZERO_TIME); scheduleNextPayload(); } - else if (phase == END_REFA || phase == END_REFB)//TODO send all to sleep for REFA?? + else if (phase == END_REFA || phase == END_REFB)//TODO send all to sleep for REFA cause we only send for bank 0 now??? { printDebugMessage("Finished auto refresh on bank " + to_string(bank.ID())); if(numberOfPayloadsInSystem[bank] == 0) diff --git a/dram/src/simulation/Dram.h b/dram/src/simulation/Dram.h index 7049ea86..e7f47677 100644 --- a/dram/src/simulation/Dram.h +++ b/dram/src/simulation/Dram.h @@ -108,45 +108,37 @@ struct Dram: sc_module } //Powerdown phases have to be started and ended by the controller, because they do not have a fixed length - else if (phase == BEGIN_PDNP) - { - if(Configuration::getInstance().BankwiseLogic == false) - { - if(bank == 0) - { - //DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle); - } - } - } - else if (phase == END_PDNP) - { - if(Configuration::getInstance().BankwiseLogic == false) - { - if(bank == 0) - { - //DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle); - } - } - } else if (phase == BEGIN_PDNA) { - if(Configuration::getInstance().BankwiseLogic == false) - { - if(bank == 0) - { //DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle); - } - } } else if (phase == END_PDNA) { - if(Configuration::getInstance().BankwiseLogic ==false) - { - if(bank == 0) - { //DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle); - } - } + } + else if (phase == BEGIN_PDNAB) + { + //DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle); + } + else if (phase == END_PDNAB) + { + //DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle); + } + else if (phase == BEGIN_PDNP) + { + //DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle); + } + else if (phase == END_PDNP) + { + //DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle); + } + else if (phase == BEGIN_PDNPB) + { + //DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle); + } + else if (phase == END_PDNPB) + { + //DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle); } else if (phase == BEGIN_SREF) { @@ -156,6 +148,14 @@ struct Dram: sc_module { //DRAMPower->doCommand(MemCommand::SREX, bank, cycle); } + else if (phase == BEGIN_SREFB) + { + //DRAMPower->doCommand(MemCommand::SREN, bank, cycle); + } + else if (phase == END_SREFB) + { + //DRAMPower->doCommand(MemCommand::SREX, bank, cycle); + } else { SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase"); From dc96ffd052adf09349ef00cc11d0c94e965cd26c Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Mon, 4 Aug 2014 13:02:52 +0200 Subject: [PATCH 7/9] metrics: memory utilization --- dram/resources/scripts/metrics.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/dram/resources/scripts/metrics.py b/dram/resources/scripts/metrics.py index 8f448db1..dfcf491a 100644 --- a/dram/resources/scripts/metrics.py +++ b/dram/resources/scripts/metrics.py @@ -60,14 +60,14 @@ def average_response_latency_in_ns(connection): return round(result[0],1) @metric -def memory_utilisation(connection): +def memory_utilisation_percent(connection): cursor = connection.cursor() cursor.execute(""" SELECT sum(DataStrobeEnd - DataStrobeBegin) FROM transactions """) active = cursor.fetchone() cursor = connection.cursor() cursor.execute(""" SELECT max(DataStrobeEnd) FROM Transactions """) total = cursor.fetchone() - return str(active[0]/total[0]*100)+"%" + return (active[0]/total[0])*100 def refreshMissDecision(connection,calculatedMetrics): From 6704dc2871f96106881b817a15d7b8b4a3cbcd96 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Mon, 4 Aug 2014 17:31:25 +0200 Subject: [PATCH 8/9] First approach for saving data, but there is an error with the memcopy in Dram.h --- dram/src/simulation/Dram.h | 137 ++++++++++++++++++++++-------- dram/src/simulation/TracePlayer.h | 23 ++++- 2 files changed, 123 insertions(+), 37 deletions(-) diff --git a/dram/src/simulation/Dram.h b/dram/src/simulation/Dram.h index e7f47677..bdb70e99 100644 --- a/dram/src/simulation/Dram.h +++ b/dram/src/simulation/Dram.h @@ -19,37 +19,90 @@ #include "../common/protocol.h" #include "../common/Utils.h" #include "../common/TlmRecorder.h" -//#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" -//#include "../common/third_party/DRAMPower/src/xmlparser/MemSpecParser.h" -//#include "../common/third_party/DRAMPower/src/MemorySpecification.h" -//#include "../common/third_party/DRAMPower/src/MemCommand.h" +#include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h" +#include "../common/third_party/DRAMPower/src/xmlparser/MemSpecParser.h" +#include "../common/third_party/DRAMPower/src/MemorySpecification.h" +#include "../common/third_party/DRAMPower/src/MemCommand.h" using namespace std; using namespace tlm; using namespace core; -//using namespace Data; +using namespace Data; + + +#define POWER + +#ifdef POWER + #define IFPOW(x) x +#else + #define IFPOW(x) +#endif + + +class column +{ + private: + + unsigned char * data; + unsigned int bytes; + + public: + + column() + { + bytes = 0; + data = NULL; + } + + column(int bytes) + { + bytes = bytes; + data = new unsigned char[bytes]; + } + + ~column() + { + //delete data; + } + + void set(unsigned char * payloadDataPtr) + { + printf("Dest: %p Source: %p\n",data,payloadDataPtr); + cout << "mem" ; + memcpy(data, payloadDataPtr, bytes); // XXX hier knallts + cout << "copy" << endl; + } + + void get(unsigned char * payloadDataPtr) + { + memcpy(payloadDataPtr, data, bytes); + } +}; template struct Dram: sc_module { tlm_utils::simple_target_socket tSocket; - //libDRAMPower *DRAMPower; + IFPOW(libDRAMPower *DRAMPower); + + map< unsigned long int, column * > memory; SC_CTOR(Dram) : tSocket("socket") { tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw); - //MemorySpecification memSpec(MemSpecParser::getMemSpecFromXML(Configuration::getInstance().memspecUri)); - //DRAMPower = new libDRAMPower( memSpec, 0 ); + IFPOW( MemorySpecification memSpec(MemSpecParser::getMemSpecFromXML(Configuration::getInstance().memspecUri)) ); + IFPOW( DRAMPower = new libDRAMPower( memSpec, 0 ) ); } ~Dram() { -// DRAMPower->updateCounters(true); -// DRAMPower->getEnergy(); -// cout << "Total Energy" << "\t" << DRAMPower->mpm.energy.total_energy << endl; -// cout << "Average Power" << "\t" << DRAMPower->mpm.power.average_power << endl; + IFPOW( DRAMPower->updateCounters(true)); + IFPOW( DRAMPower->getEnergy() ); + IFPOW( cout << "Total Energy" << "\t" << DRAMPower->mpm.energy.total_energy << endl); + IFPOW( cout << "Average Power" << "\t" << DRAMPower->mpm.power.average_power << endl ); + std::cout << "Simulated Memory Size: " << memory.size() << endl; } virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& payload, tlm::tlm_phase& phase, sc_time& delay) @@ -62,103 +115,119 @@ struct Dram: sc_module if (phase == BEGIN_PRE) { - //DRAMPower->doCommand(MemCommand::PRE, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::PRE, bank, cycle)); sendToController(payload, END_PRE, delay + getExecutionTime(Command::Precharge, payload)); } else if (phase == BEGIN_PRE_ALL) { - //DRAMPower->doCommand(MemCommand::PREA, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::PREA, bank, cycle)); sendToController(payload, END_PRE_ALL,delay + getExecutionTime(Command::PrechargeAll, payload)); } else if (phase == BEGIN_ACT) { - //DRAMPower->doCommand(MemCommand::ACT, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::ACT, bank, cycle)); sendToController(payload, END_ACT, delay + getExecutionTime(Command::Activate, payload)); } else if (phase == BEGIN_WR) { - //DRAMPower->doCommand(MemCommand::WR, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::WR, bank, cycle)); sendToController(payload, END_WR, delay + getExecutionTime(Command::Write, payload)); + + // Save: + column * c = new column(16); + c->set(payload.get_data_ptr()); // <-- hier drin knallts + memory[payload.get_address()] = c; } else if (phase == BEGIN_RD) { - //DRAMPower->doCommand(MemCommand::RD, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::RD, bank, cycle)); sendToController(payload, END_RD, delay + getExecutionTime(Command::Read, payload)); + + // Load: + //if(memory.count(payload.get_address()) == 1) + //{ + // column * c = memory[payload.get_address()]; + // c->get(payload.get_data_ptr()); + //} + //else + //{ + // SC_REPORT_WARNING ("DRAM", "Reading from an empty memory location"); + //} } else if (phase == BEGIN_WRA) { - //DRAMPower->doCommand(MemCommand::WRA, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::WRA, bank, cycle)); sendToController(payload, END_WRA, delay + getExecutionTime(Command::WriteA, payload)); } else if (phase == BEGIN_RDA) { - //DRAMPower->doCommand(MemCommand::RDA, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::RDA, bank, cycle)); sendToController(payload, END_RDA, delay + getExecutionTime(Command::ReadA, payload)); } else if (phase == BEGIN_REFA) { - //DRAMPower->doCommand(MemCommand::REF, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::REF, bank, cycle)); sendToController(payload, END_REFA, delay + getExecutionTime(Command::AutoRefresh, payload)); } else if (phase == BEGIN_REFB) { - //DRAMPower->doCommand(MemCommand::REF, bank, cycle); + IFPOW( SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported") ); sendToController(payload, END_REFB, delay + getExecutionTime(Command::AutoRefresh, payload)); } //Powerdown phases have to be started and ended by the controller, because they do not have a fixed length else if (phase == BEGIN_PDNA) { - //DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle)); } else if (phase == END_PDNA) { - //DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle)); } else if (phase == BEGIN_PDNAB) { - //DRAMPower->doCommand(MemCommand::PDN_S_ACT, bank, cycle); + IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported")); } else if (phase == END_PDNAB) { - //DRAMPower->doCommand(MemCommand::PUP_ACT, bank, cycle); + IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported")); } else if (phase == BEGIN_PDNP) { - //DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle)); } else if (phase == END_PDNP) { - //DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle)); } else if (phase == BEGIN_PDNPB) { - //DRAMPower->doCommand(MemCommand::PDN_S_PRE, bank, cycle); + IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported")); } else if (phase == END_PDNPB) { - //DRAMPower->doCommand(MemCommand::PUP_PRE, bank, cycle); + IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported")); } else if (phase == BEGIN_SREF) { - //DRAMPower->doCommand(MemCommand::SREN, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::SREN, bank, cycle)); } else if (phase == END_SREF) { - //DRAMPower->doCommand(MemCommand::SREX, bank, cycle); + IFPOW(DRAMPower->doCommand(MemCommand::SREX, bank, cycle)); } else if (phase == BEGIN_SREFB) { - //DRAMPower->doCommand(MemCommand::SREN, bank, cycle); + IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported")); } else if (phase == END_SREFB) { - //DRAMPower->doCommand(MemCommand::SREX, bank, cycle); + IFPOW(SC_REPORT_FATAL("DRAM", "Power calculation for bankwise logic not supported")); } else { - SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase"); + IFPOW(SC_REPORT_FATAL("DRAM", "DRAM PEQ was called with unknown phase")); } return tlm::TLM_ACCEPTED; } diff --git a/dram/src/simulation/TracePlayer.h b/dram/src/simulation/TracePlayer.h index 42b589da..5581ed6c 100644 --- a/dram/src/simulation/TracePlayer.h +++ b/dram/src/simulation/TracePlayer.h @@ -87,11 +87,11 @@ void TracePlayer::generateNextPayload() { if (file) { - string time, command, address; + string time, command, address, data; file >> time >> command >> address; //if there is a newline at the end of the .stl - if (time.empty() || command.empty() || address.empty()) + if (time.empty() || command.empty() || address.empty() ) return; long parsedAdress = std::stoi(address.c_str(), 0, 16); @@ -99,6 +99,13 @@ void TracePlayer::generateNextPayload() gp* payload = memoryManager.allocate(); payload->set_address(parsedAdress); + // Set data pointer + unsigned char * dataElement = new unsigned char[16]; // TODO: column / burst breite + payload->set_data_length(16); // TODO: column / burst breite + payload->set_data_ptr(dataElement); + for(int i = 0; i < 16; i++) // TODO: column / burst breite + dataElement[i] = 0; + if (command == "read") { payload->set_command(TLM_READ_COMMAND); @@ -106,6 +113,17 @@ void TracePlayer::generateNextPayload() else if (command == "write") { payload->set_command(TLM_WRITE_COMMAND); + + // Parse and set data + file >> data; + unsigned int counter = 0; + for(int i = 0; i < 16*2-2; i=i+2) // TODO column / burst breite + { + std::string byteString = "0x"; + byteString.append(data.substr(i+2, 2)); + //cout << byteString << " " << std::stoi(byteString.c_str(), 0, 16) << endl; + dataElement[counter++] = std::stoi(byteString.c_str(), 0, 16); + } } else { @@ -113,7 +131,6 @@ void TracePlayer::generateNextPayload() (string("Corrupted tracefile, command ") + command + string(" unknown")).c_str()); } - payload->set_data_length(BUSWIDTH / 8); payload->set_response_status(TLM_INCOMPLETE_RESPONSE); payload->set_dmi_allowed(false); payload->set_byte_enable_length(0); From fe9f9ad23304d4b95bf32e00cec724681d42cee7 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Mon, 4 Aug 2014 17:46:29 +0200 Subject: [PATCH 9/9] changes on project file --- dram/dramSys/dramSys.pro | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/dram/dramSys/dramSys.pro b/dram/dramSys/dramSys.pro index e8e8ffa7..61f4c916 100644 --- a/dram/dramSys/dramSys.pro +++ b/dram/dramSys/dramSys.pro @@ -8,24 +8,25 @@ LIBS += -L/opt/systemc/lib-linux64 -lsystemc LIBS += -L/opt/boost/lib -lboost_filesystem -lboost_system LIBS += -L/opt/sqlite3/lib -lsqlite3 LIBS += -lpthread -#LIBS += -lxerces-c -#LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampowerxml -#LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampower +LIBS += -lxerces-c +LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampowerxml +LIBS += -L../src/common/third_party/DRAMPower/src/ -ldrampower INCLUDEPATH += /opt/systemc/include INCLUDEPATH += /opt/boost/include INCLUDEPATH += /opt/sqlite3/include -#INCLUDEPATH += ../src/common/third_party/DRAMPower/src -#INCLUDEPATH += ../src/common/third_party/DRAMPower/src/libdrampower +INCLUDEPATH += ../src/common/third_party/DRAMPower/src +INCLUDEPATH += ../src/common/third_party/DRAMPower/src/libdrampower DEFINES += TIXML_USE_STL DEFINES += SC_INCLUDE_DYNAMIC_PROCESSES -#DEFINES += USE_XERCES=1 +DEFINES += USE_XERCES=1 +DEFINES += NDEBUG QMAKE_CXXFLAGS += -std=c++11 QMAKE_CXXFLAGS += -isystem /opt/systemc/include QMAKE_CXXFLAGS += -isystem /opt/boost/include -#QMAKE_CXXFLAGS += -iquote ../src/common/third_party/DRAMPower/src/ +QMAKE_CXXFLAGS += -iquote ../src/common/third_party/DRAMPower/src/ SOURCES += \ ../src/common/third_party/tinyxml2.cpp \