diff --git a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp index c635bbc1..945252f5 100644 --- a/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/library/src/controller/core/configuration/ConfigurationLoader.cpp @@ -181,7 +181,7 @@ void ConfigurationLoader::loadCommons(Configuration &config, XMLElement *xmlSpec // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); memSpec->NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); - //memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); memSpec->BurstLength = queryUIntParameter(architecture, "burstLength"); memSpec->DataRate = queryUIntParameter(architecture, "dataRate"); memSpec->NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); @@ -216,8 +216,8 @@ void ConfigurationLoader::loadDDR3(Configuration &config, XMLElement *xmlSpec) SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); // MemArchitecture - XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + //XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + //memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); memSpec->NumberOfBankGroups = 1; memSpec->nActivate = 4; memSpec->DLL = true; @@ -284,7 +284,7 @@ void ConfigurationLoader::loadDDR4(Configuration &config, XMLElement *xmlSpec) // MemArchitecture XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + //memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); memSpec->NumberOfBankGroups = queryUIntParameter(architecture, "nbrOfBankGroups"); memSpec->nActivate = 4; memSpec->DLL = true; @@ -359,8 +359,8 @@ void ConfigurationLoader::loadLPDDR4(Configuration &config, XMLElement *xmlSpec) SC_REPORT_FATAL("ConfigurationLoader", "Wrong MemSpec chosen"); // MemArchitecture: - XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); - memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + //XMLElement *architecture = xmlSpec->FirstChildElement("memarchitecturespec"); + //memSpec->NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); memSpec->NumberOfBankGroups = 1; memSpec->nActivate = 4; memSpec->DLL = false; // TODO: Correct? @@ -431,8 +431,8 @@ void ConfigurationLoader::loadWideIO(Configuration &config, XMLElement *memspec) // MemSpecification //XMLElement *architecture = memspec->FirstChildElement("memarchitecturespec"); + //memSpec->NumberOfRanks = 1; // TODO: is part of some memspecs for WideIO memSpec->NumberOfBankGroups = 1; - memSpec->NumberOfRanks = 1; // TODO: is part of some memspecs for WideIO memSpec->nActivate = 2; memSpec->DLL = false; memSpec->termination = false; diff --git a/DRAMSys/library/src/controller/core/configuration/MemSpec.h b/DRAMSys/library/src/controller/core/configuration/MemSpec.h index 09f91b76..abbf49a7 100644 --- a/DRAMSys/library/src/controller/core/configuration/MemSpec.h +++ b/DRAMSys/library/src/controller/core/configuration/MemSpec.h @@ -108,7 +108,7 @@ struct MemSpec sc_time tNAW_old; // n activate window, TAW (two bank) in WideIO, FAW (four bank) else sc_time tRP_old; // precharge-time (pre -> act same bank) sc_time tRFC_old; // min ref->act delay 1X mode - // TODO: only available in DDR4? Remove in DramDDR3 and DramWideIO! + // TODO: used in DDR4 and LPDDR4, remove in DramDDR3 and DramWideIO or everywhere sc_time tRFC2; // min ref->act delay 2X mode sc_time tRFC4; // min ref->act delay 4X mode sc_time tREFI_old; // auto refresh must be issued at an average periodic interval tREFI @@ -197,7 +197,7 @@ struct MemSpecDDR4 : public MemSpec sc_time tXSDLL; // Returns the execution time for commands that have a fixed execution time - sc_time getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const; + virtual sc_time getExecutionTime(Command command, tlm::tlm_generic_payload &payload) const override; }; struct MemSpecWideIO : public MemSpec diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h index 37c26250..28baca01 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.h @@ -18,8 +18,7 @@ public: } virtual ~CheckerDDR3() {} - virtual void delayToSatisfyConstraints(ScheduledCommand &command) const - override; + virtual void delayToSatisfyConstraints(ScheduledCommand &command) const override; private: MemSpecDDR3 *memSpec; diff --git a/DRAMSys/library/src/simulation/Dram.cpp b/DRAMSys/library/src/simulation/Dram.cpp index a380ceea..88383062 100644 --- a/DRAMSys/library/src/simulation/Dram.cpp +++ b/DRAMSys/library/src/simulation/Dram.cpp @@ -69,6 +69,103 @@ Dram::Dram(sc_module_name) : tSocket("socket") tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw); tSocket.register_transport_dbg(this, &Dram::transport_dbg); + + MemSpec *memSpec = Configuration::getInstance().memSpec; + sc_time clk = memSpec->clk; + + MemArchitectureSpec memArchSpec; + memArchSpec.burstLength = memSpec->BurstLength; + memArchSpec.dataRate = memSpec->DataRate; + memArchSpec.nbrOfRows = memSpec->NumberOfRows; + memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; + memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; + memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; + memArchSpec.width = memSpec->bitWidth; + memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; + memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); + memArchSpec.dll = memSpec->DLL; + + MemTimingSpec memTimingSpec; + memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; + memTimingSpec.RASB = Configuration::getInstance().trasbclk; + memTimingSpec.RCB = Configuration::getInstance().trcbclk; + memTimingSpec.RPB = Configuration::getInstance().trpbclk; + memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; + memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; + memTimingSpec.AL = memSpec->tAL / clk; + memTimingSpec.CCD = memSpec->tCCD_S_old / clk; + memTimingSpec.CCD_L = memSpec->tCCD_L_old / clk; + memTimingSpec.CCD_S = memSpec->tCCD_S_old / clk; + memTimingSpec.CKE = memSpec->tCKE / clk; + memTimingSpec.CKESR = memSpec->tCKESR / clk; + memTimingSpec.clkMhz = memSpec->clkMHz; + // See also MemTimingSpec.cc in DRAMPower + memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; + memTimingSpec.DQSCK = memSpec->tDQSCK / clk; + memTimingSpec.FAW = memSpec->tNAW_old / clk; + memTimingSpec.RAS = memSpec->tRAS / clk; + memTimingSpec.RC = memSpec->tRC / clk; + memTimingSpec.RCD = memSpec->tRCD / clk; + memTimingSpec.REFI = memSpec->tREFI_old / clk; + unsigned m = Configuration::getInstance().getRefMode(); + if (m == 4) + memTimingSpec.RFC = memSpec->tRFC4 / clk; + else if (m == 2) + memTimingSpec.RFC = memSpec->tRFC2 / clk; + else + memTimingSpec.RFC = memSpec->tRFC_old / clk; + memTimingSpec.RL = memSpec->tRL / clk; + memTimingSpec.RP = memSpec->tRP_old / clk; + memTimingSpec.RRD = memSpec->tRRD_S_old / clk; + memTimingSpec.RRD_L = memSpec->tRRD_L_old / clk; + memTimingSpec.RRD_S = memSpec->tRRD_S_old / clk; + memTimingSpec.RTP = memSpec->tRTP / clk; + memTimingSpec.TAW = memSpec->tNAW_old / clk; + memTimingSpec.WL = memSpec->tWL / clk; + memTimingSpec.WR = memSpec->tWR / clk; + memTimingSpec.WTR = memSpec->tWTR_S_old / clk; + memTimingSpec.WTR_L = memSpec->tWTR_L_old / clk; + memTimingSpec.WTR_S = memSpec->tWTR_S_old / clk; + memTimingSpec.XP = memSpec->tXP / clk; + memTimingSpec.XPDLL = memSpec->tXPDLL_old / clk; + memTimingSpec.XS = memSpec->tXS / clk; + memTimingSpec.XSDLL = memSpec->tXSDLL_old / clk; + + MemPowerSpec memPowerSpec; + memPowerSpec.idd0 = memSpec->iDD0; + memPowerSpec.idd02 = memSpec->iDD02; + memPowerSpec.idd2p0 = memSpec->iDD2P0; + memPowerSpec.idd2p02 = memSpec->iDD2P02; + memPowerSpec.idd2p1 = memSpec->iDD2P1; + memPowerSpec.idd2p12 = memSpec->iDD2P12; + memPowerSpec.idd2n = memSpec->iDD2N; + memPowerSpec.idd2n2 = memSpec->iDD2N2; + memPowerSpec.idd3p0 = memSpec->iDD3P0; + memPowerSpec.idd3p02 = memSpec->iDD3P02; + memPowerSpec.idd3p1 = memSpec->iDD3P1; + memPowerSpec.idd3p12 = memSpec->iDD3P12; + memPowerSpec.idd3n = memSpec->iDD3N; + memPowerSpec.idd3n2 = memSpec->iDD3N2; + memPowerSpec.idd4r = memSpec->iDD4R; + memPowerSpec.idd4r2 = memSpec->iDD4R2; + memPowerSpec.idd4w = memSpec->iDD4W; + memPowerSpec.idd4w2 = memSpec->iDD4W2; + memPowerSpec.idd5 = memSpec->iDD5; + memPowerSpec.idd52 = memSpec->iDD52; + memPowerSpec.idd6 = memSpec->iDD6; + memPowerSpec.idd62 = memSpec->iDD62; + memPowerSpec.vdd = memSpec->vDD; + memPowerSpec.vdd2 = memSpec->vDD2; + + MemorySpecification powerSpec; + powerSpec.id = memSpec->MemoryId; + powerSpec.memoryType = memSpec->MemoryType; + powerSpec.memTimingSpec = memTimingSpec; + powerSpec.memPowerSpec = memPowerSpec; + powerSpec.memArchSpec = memArchSpec; + + DRAMPower = new libDRAMPower(powerSpec, 0); } Dram::~Dram() diff --git a/DRAMSys/library/src/simulation/DramDDR3.cpp b/DRAMSys/library/src/simulation/DramDDR3.cpp index 2e7daef2..c75aebe2 100644 --- a/DRAMSys/library/src/simulation/DramDDR3.cpp +++ b/DRAMSys/library/src/simulation/DramDDR3.cpp @@ -49,99 +49,5 @@ DramDDR3::DramDDR3(sc_module_name name) : Dram(name) if (memSpec == nullptr) SC_REPORT_FATAL("DramDDR4", "Wrong MemSpec chosen"); - sc_time clk = memSpec->clk; - - MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = memSpec->BurstLength; - memArchSpec.dataRate = memSpec->DataRate; - memArchSpec.nbrOfRows = memSpec->NumberOfRows; - memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; - memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; - memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; - memArchSpec.width = memSpec->bitWidth; - memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; - memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); - memArchSpec.dll = memSpec->DLL; - - MemTimingSpec memTimingSpec; - memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; - memTimingSpec.RASB = Configuration::getInstance().trasbclk; - memTimingSpec.RCB = Configuration::getInstance().trcbclk; - memTimingSpec.RPB = Configuration::getInstance().trpbclk; - memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; - memTimingSpec.AL = memSpec->tAL / clk; - memTimingSpec.CCD = memSpec->tCCD_S_old / clk; - memTimingSpec.CCD_L = memSpec->tCCD_L_old / clk; - memTimingSpec.CCD_S = memSpec->tCCD_S_old / clk; - memTimingSpec.CKE = memSpec->tCKE / clk; - memTimingSpec.CKESR = memSpec->tCKESR / clk; - memTimingSpec.clkMhz = memSpec->clkMHz; - // See also MemTimingSpec.cc in DRAMPower - memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; - memTimingSpec.DQSCK = memSpec->tDQSCK / clk; - memTimingSpec.FAW = memSpec->tNAW_old / clk; - memTimingSpec.RAS = memSpec->tRAS / clk; - memTimingSpec.RC = memSpec->tRC / clk; - memTimingSpec.RCD = memSpec->tRCD / clk; - memTimingSpec.REFI = memSpec->tREFI_old / clk; - unsigned m = Configuration::getInstance().getRefMode(); - if (m == 4) - memTimingSpec.RFC = memSpec->tRFC4 / clk; - else if (m == 2) - memTimingSpec.RFC = memSpec->tRFC2 / clk; - else - memTimingSpec.RFC = memSpec->tRFC_old / clk; - memTimingSpec.RL = memSpec->tRL / clk; - memTimingSpec.RP = memSpec->tRP_old / clk; - memTimingSpec.RRD = memSpec->tRRD_S_old / clk; - memTimingSpec.RRD_L = memSpec->tRRD_L_old / clk; - memTimingSpec.RRD_S = memSpec->tRRD_S_old / clk; - memTimingSpec.RTP = memSpec->tRTP / clk; - memTimingSpec.TAW = memSpec->tNAW_old / clk; - memTimingSpec.WL = memSpec->tWL / clk; - memTimingSpec.WR = memSpec->tWR / clk; - memTimingSpec.WTR = memSpec->tWTR_S_old / clk; - memTimingSpec.WTR_L = memSpec->tWTR_L_old / clk; - memTimingSpec.WTR_S = memSpec->tWTR_S_old / clk; - memTimingSpec.XP = memSpec->tXP / clk; - memTimingSpec.XPDLL = memSpec->tXPDLL_old / clk; - memTimingSpec.XS = memSpec->tXS / clk; - memTimingSpec.XSDLL = memSpec->tXSDLL_old / clk; - - MemPowerSpec memPowerSpec; - memPowerSpec.idd0 = memSpec->iDD0; - memPowerSpec.idd02 = memSpec->iDD02; - memPowerSpec.idd2p0 = memSpec->iDD2P0; - memPowerSpec.idd2p02 = memSpec->iDD2P02; - memPowerSpec.idd2p1 = memSpec->iDD2P1; - memPowerSpec.idd2p12 = memSpec->iDD2P12; - memPowerSpec.idd2n = memSpec->iDD2N; - memPowerSpec.idd2n2 = memSpec->iDD2N2; - memPowerSpec.idd3p0 = memSpec->iDD3P0; - memPowerSpec.idd3p02 = memSpec->iDD3P02; - memPowerSpec.idd3p1 = memSpec->iDD3P1; - memPowerSpec.idd3p12 = memSpec->iDD3P12; - memPowerSpec.idd3n = memSpec->iDD3N; - memPowerSpec.idd3n2 = memSpec->iDD3N2; - memPowerSpec.idd4r = memSpec->iDD4R; - memPowerSpec.idd4r2 = memSpec->iDD4R2; - memPowerSpec.idd4w = memSpec->iDD4W; - memPowerSpec.idd4w2 = memSpec->iDD4W2; - memPowerSpec.idd5 = memSpec->iDD5; - memPowerSpec.idd52 = memSpec->iDD52; - memPowerSpec.idd6 = memSpec->iDD6; - memPowerSpec.idd62 = memSpec->iDD62; - memPowerSpec.vdd = memSpec->vDD; - memPowerSpec.vdd2 = memSpec->vDD2; - - MemorySpecification powerSpec; - powerSpec.id = memSpec->MemoryId; - powerSpec.memoryType = memSpec->MemoryType; - powerSpec.memTimingSpec = memTimingSpec; - powerSpec.memPowerSpec = memPowerSpec; - powerSpec.memArchSpec = memArchSpec; - - DRAMPower = new libDRAMPower(powerSpec, 0); + // TODO: Specific configuration of DRAMPower } diff --git a/DRAMSys/library/src/simulation/DramDDR4.cpp b/DRAMSys/library/src/simulation/DramDDR4.cpp index 8a098d7c..e3bc459b 100644 --- a/DRAMSys/library/src/simulation/DramDDR4.cpp +++ b/DRAMSys/library/src/simulation/DramDDR4.cpp @@ -49,99 +49,5 @@ DramDDR4::DramDDR4(sc_module_name name) : Dram(name) if (memSpec == nullptr) SC_REPORT_FATAL("DramDDR4", "Wrong MemSpec chosen"); - sc_time clk = memSpec->clk; - - MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = memSpec->BurstLength; - memArchSpec.dataRate = memSpec->DataRate; - memArchSpec.nbrOfRows = memSpec->NumberOfRows; - memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; - memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; - memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; - memArchSpec.width = memSpec->bitWidth; - memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; - memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); - memArchSpec.dll = memSpec->DLL; - - MemTimingSpec memTimingSpec; - memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; - memTimingSpec.RASB = Configuration::getInstance().trasbclk; - memTimingSpec.RCB = Configuration::getInstance().trcbclk; - memTimingSpec.RPB = Configuration::getInstance().trpbclk; - memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; - memTimingSpec.AL = memSpec->tAL / clk; - memTimingSpec.CCD = memSpec->tCCD_S_old / clk; - memTimingSpec.CCD_L = memSpec->tCCD_L_old / clk; - memTimingSpec.CCD_S = memSpec->tCCD_S_old / clk; - memTimingSpec.CKE = memSpec->tCKE / clk; - memTimingSpec.CKESR = memSpec->tCKESR / clk; - memTimingSpec.clkMhz = memSpec->clkMHz; - // See also MemTimingSpec.cc in DRAMPower - memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; - memTimingSpec.DQSCK = memSpec->tDQSCK / clk; - memTimingSpec.FAW = memSpec->tNAW_old / clk; - memTimingSpec.RAS = memSpec->tRAS / clk; - memTimingSpec.RC = memSpec->tRC / clk; - memTimingSpec.RCD = memSpec->tRCD / clk; - memTimingSpec.REFI = memSpec->tREFI_old / clk; - unsigned m = Configuration::getInstance().getRefMode(); - if (m == 4) - memTimingSpec.RFC = memSpec->tRFC4 / clk; - else if (m == 2) - memTimingSpec.RFC = memSpec->tRFC2 / clk; - else - memTimingSpec.RFC = memSpec->tRFC_old / clk; - memTimingSpec.RL = memSpec->tRL / clk; - memTimingSpec.RP = memSpec->tRP_old / clk; - memTimingSpec.RRD = memSpec->tRRD_S_old / clk; - memTimingSpec.RRD_L = memSpec->tRRD_L_old / clk; - memTimingSpec.RRD_S = memSpec->tRRD_S_old / clk; - memTimingSpec.RTP = memSpec->tRTP / clk; - memTimingSpec.TAW = memSpec->tNAW_old / clk; - memTimingSpec.WL = memSpec->tWL / clk; - memTimingSpec.WR = memSpec->tWR / clk; - memTimingSpec.WTR = memSpec->tWTR_S_old / clk; - memTimingSpec.WTR_L = memSpec->tWTR_L_old / clk; - memTimingSpec.WTR_S = memSpec->tWTR_S_old / clk; - memTimingSpec.XP = memSpec->tXP / clk; - memTimingSpec.XPDLL = memSpec->tXPDLL_old / clk; - memTimingSpec.XS = memSpec->tXS / clk; - memTimingSpec.XSDLL = memSpec->tXSDLL_old / clk; - - MemPowerSpec memPowerSpec; - memPowerSpec.idd0 = memSpec->iDD0; - memPowerSpec.idd02 = memSpec->iDD02; - memPowerSpec.idd2p0 = memSpec->iDD2P0; - memPowerSpec.idd2p02 = memSpec->iDD2P02; - memPowerSpec.idd2p1 = memSpec->iDD2P1; - memPowerSpec.idd2p12 = memSpec->iDD2P12; - memPowerSpec.idd2n = memSpec->iDD2N; - memPowerSpec.idd2n2 = memSpec->iDD2N2; - memPowerSpec.idd3p0 = memSpec->iDD3P0; - memPowerSpec.idd3p02 = memSpec->iDD3P02; - memPowerSpec.idd3p1 = memSpec->iDD3P1; - memPowerSpec.idd3p12 = memSpec->iDD3P12; - memPowerSpec.idd3n = memSpec->iDD3N; - memPowerSpec.idd3n2 = memSpec->iDD3N2; - memPowerSpec.idd4r = memSpec->iDD4R; - memPowerSpec.idd4r2 = memSpec->iDD4R2; - memPowerSpec.idd4w = memSpec->iDD4W; - memPowerSpec.idd4w2 = memSpec->iDD4W2; - memPowerSpec.idd5 = memSpec->iDD5; - memPowerSpec.idd52 = memSpec->iDD52; - memPowerSpec.idd6 = memSpec->iDD6; - memPowerSpec.idd62 = memSpec->iDD62; - memPowerSpec.vdd = memSpec->vDD; - memPowerSpec.vdd2 = memSpec->vDD2; - - MemorySpecification powerSpec; - powerSpec.id = memSpec->MemoryId; - powerSpec.memoryType = memSpec->MemoryType; - powerSpec.memTimingSpec = memTimingSpec; - powerSpec.memPowerSpec = memPowerSpec; - powerSpec.memArchSpec = memArchSpec; - - DRAMPower = new libDRAMPower(powerSpec, 0);; + // TODO: Specific configuration of DRAMPower } diff --git a/DRAMSys/library/src/simulation/DramRecordable.cpp b/DRAMSys/library/src/simulation/DramRecordable.cpp index 56c5e27e..ccf101b1 100644 --- a/DRAMSys/library/src/simulation/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/DramRecordable.cpp @@ -56,7 +56,7 @@ DramRecordable::DramRecordable(sc_module_name name, TlmRecorder *tlmRe template DramRecordable::~DramRecordable() { - BaseDram::DRAMPower->calcEnergy(); + this->DRAMPower->calcEnergy(); recordPower(); tlmRecorder->closeConnection(); } diff --git a/DRAMSys/library/src/simulation/DramWideIO.cpp b/DRAMSys/library/src/simulation/DramWideIO.cpp index e6da902b..459396e9 100644 --- a/DRAMSys/library/src/simulation/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/DramWideIO.cpp @@ -67,101 +67,7 @@ DramWideIO::DramWideIO(sc_module_name name) : Dram(name) if (memSpec == nullptr) SC_REPORT_FATAL("DramWideIO", "Wrong MemSpec chosen"); - sc_time clk = memSpec->clk; - - MemArchitectureSpec memArchSpec; - memArchSpec.burstLength = memSpec->BurstLength; - memArchSpec.dataRate = memSpec->DataRate; - memArchSpec.nbrOfRows = memSpec->NumberOfRows; - memArchSpec.nbrOfBanks = memSpec->NumberOfBanks; - memArchSpec.nbrOfColumns = memSpec->NumberOfColumns; - memArchSpec.nbrOfRanks = memSpec->NumberOfRanks; - memArchSpec.width = memSpec->bitWidth; - memArchSpec.nbrOfBankGroups = memSpec->NumberOfBankGroups; - memArchSpec.twoVoltageDomains = ((memSpec->vDD2 == 0) ? false : true); - memArchSpec.dll = memSpec->DLL; - - MemTimingSpec memTimingSpec; - memTimingSpec.FAWB = Configuration::getInstance().tfawbclk; - memTimingSpec.RASB = Configuration::getInstance().trasbclk; - memTimingSpec.RCB = Configuration::getInstance().trcbclk; - memTimingSpec.RPB = Configuration::getInstance().trpbclk; - memTimingSpec.RRDB = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_L = Configuration::getInstance().trrdblclk; - memTimingSpec.RRDB_S = Configuration::getInstance().trrdblclk; - memTimingSpec.AL = memSpec->tAL / clk; - memTimingSpec.CCD = memSpec->tCCD_S_old / clk; - memTimingSpec.CCD_L = memSpec->tCCD_L_old / clk; - memTimingSpec.CCD_S = memSpec->tCCD_S_old / clk; - memTimingSpec.CKE = memSpec->tCKE / clk; - memTimingSpec.CKESR = memSpec->tCKESR / clk; - memTimingSpec.clkMhz = memSpec->clkMHz; - // See also MemTimingSpec.cc in DRAMPower - memTimingSpec.clkPeriod = 1000.0 / memSpec->clkMHz; - memTimingSpec.DQSCK = memSpec->tDQSCK / clk; - memTimingSpec.FAW = memSpec->tNAW_old / clk; - memTimingSpec.RAS = memSpec->tRAS / clk; - memTimingSpec.RC = memSpec->tRC / clk; - memTimingSpec.RCD = memSpec->tRCD / clk; - memTimingSpec.REFI = memSpec->tREFI_old / clk; - unsigned m = Configuration::getInstance().getRefMode(); - if (m == 4) - memTimingSpec.RFC = memSpec->tRFC4 / clk; - else if (m == 2) - memTimingSpec.RFC = memSpec->tRFC2 / clk; - else - memTimingSpec.RFC = memSpec->tRFC_old / clk; - memTimingSpec.RL = memSpec->tRL / clk; - memTimingSpec.RP = memSpec->tRP_old / clk; - memTimingSpec.RRD = memSpec->tRRD_S_old / clk; - memTimingSpec.RRD_L = memSpec->tRRD_L_old / clk; - memTimingSpec.RRD_S = memSpec->tRRD_S_old / clk; - memTimingSpec.RTP = memSpec->tRTP / clk; - memTimingSpec.TAW = memSpec->tNAW_old / clk; - memTimingSpec.WL = memSpec->tWL / clk; - memTimingSpec.WR = memSpec->tWR / clk; - memTimingSpec.WTR = memSpec->tWTR_S_old / clk; - memTimingSpec.WTR_L = memSpec->tWTR_L_old / clk; - memTimingSpec.WTR_S = memSpec->tWTR_S_old / clk; - memTimingSpec.XP = memSpec->tXP / clk; - memTimingSpec.XPDLL = memSpec->tXPDLL_old / clk; - memTimingSpec.XS = memSpec->tXS / clk; - memTimingSpec.XSDLL = memSpec->tXSDLL_old / clk; - - MemPowerSpec memPowerSpec; - memPowerSpec.idd0 = memSpec->iDD0; - memPowerSpec.idd02 = memSpec->iDD02; - memPowerSpec.idd2p0 = memSpec->iDD2P0; - memPowerSpec.idd2p02 = memSpec->iDD2P02; - memPowerSpec.idd2p1 = memSpec->iDD2P1; - memPowerSpec.idd2p12 = memSpec->iDD2P12; - memPowerSpec.idd2n = memSpec->iDD2N; - memPowerSpec.idd2n2 = memSpec->iDD2N2; - memPowerSpec.idd3p0 = memSpec->iDD3P0; - memPowerSpec.idd3p02 = memSpec->iDD3P02; - memPowerSpec.idd3p1 = memSpec->iDD3P1; - memPowerSpec.idd3p12 = memSpec->iDD3P12; - memPowerSpec.idd3n = memSpec->iDD3N; - memPowerSpec.idd3n2 = memSpec->iDD3N2; - memPowerSpec.idd4r = memSpec->iDD4R; - memPowerSpec.idd4r2 = memSpec->iDD4R2; - memPowerSpec.idd4w = memSpec->iDD4W; - memPowerSpec.idd4w2 = memSpec->iDD4W2; - memPowerSpec.idd5 = memSpec->iDD5; - memPowerSpec.idd52 = memSpec->iDD52; - memPowerSpec.idd6 = memSpec->iDD6; - memPowerSpec.idd62 = memSpec->iDD62; - memPowerSpec.vdd = memSpec->vDD; - memPowerSpec.vdd2 = memSpec->vDD2; - - MemorySpecification powerSpec; - powerSpec.id = memSpec->MemoryId; - powerSpec.memoryType = memSpec->MemoryType; - powerSpec.memTimingSpec = memTimingSpec; - powerSpec.memPowerSpec = memPowerSpec; - powerSpec.memArchSpec = memArchSpec; - - DRAMPower = new libDRAMPower(powerSpec, 0); + // TODO: Specific configuration of DRAMPower } DramWideIO::~DramWideIO()