diff --git a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rfm.json b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rfm.json
index 706d280f..b7f10a63 100644
--- a/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rfm.json
+++ b/DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_rfm.json
@@ -1,6 +1,6 @@
 {
     "mcconfig": {
-        "PagePolicy": "Open",
+        "PagePolicy": "Closed",
         "Scheduler": "FrFcfs",
         "SchedulerBuffer": "Bankwise",
         "RequestBufferSize": 8,
diff --git a/DRAMSys/library/resources/simulations/ddr5-rfm.json b/DRAMSys/library/resources/simulations/ddr5-rfm.json
index 7c8754df..eee91152 100644
--- a/DRAMSys/library/resources/simulations/ddr5-rfm.json
+++ b/DRAMSys/library/resources/simulations/ddr5-rfm.json
@@ -11,7 +11,7 @@
                 "clkMhz": 2000,
                 "type": "generator",
                 "name": "gen0",
-                "numRequests": 4000,
+                "numRequests": 126000,
                 "rwRatio": 0.85,
                 "addressDistribution": "random",
                 "seed": 123456,
diff --git a/DRAMSys/library/src/common/utils.cpp b/DRAMSys/library/src/common/utils.cpp
index c507aa2a..8427a84a 100644
--- a/DRAMSys/library/src/common/utils.cpp
+++ b/DRAMSys/library/src/common/utils.cpp
@@ -86,56 +86,72 @@ json parseJSON(const std::string &path)
         throw std::invalid_argument("Failed to open file '" + path + "'.");
 }
 
-bool parseBool(json &obj, const std::string &name)
+bool parseBool(json &spec, const std::string &name)
 {
-    if (!obj.empty())
+    json param = spec[name];
+    if (!param.empty())
     {
-        if (obj.is_boolean())
-            return obj;
+        if (param.is_boolean())
+            return param;
         else
             throw std::invalid_argument("Expected type for parameter '" + name + "': bool");
     }
     else
-        throw std::invalid_argument("Parameter '" + name + "' does not exist.");
+    {
+        SC_REPORT_WARNING("utils", ("Parameter '" + name + "' does not exist, default is false.").c_str());
+        return false;
+    }
 }
 
-unsigned int parseUint(json &obj, const std::string &name)
+unsigned int parseUint(json &spec, const std::string &name)
 {
-    if (!obj.empty())
+    json param = spec[name];
+    if (!param.empty())
     {
-        if (obj.is_number_unsigned())
-            return obj;
+        if (param.is_number_unsigned())
+            return param;
         else
             throw std::invalid_argument("Expected type for parameter '" + name + "': unsigned int");
     }
     else
-        throw std::invalid_argument("Parameter '" + name + "' does not exist.");
+    {
+        SC_REPORT_WARNING("utils", ("Parameter '" + name + "' does not exist, default is 1.").c_str());
+        return 1;
+    }
 }
 
-double parseUdouble(json &obj, const std::string &name)
+double parseUdouble(json &spec, const std::string &name)
 {
-    if (!obj.empty())
+    json param = spec[name];
+    if (!param.empty())
     {
-        if (obj.is_number() && (obj > 0))
-            return obj;
+        if (param.is_number() && (param > 0))
+            return param;
         else
             throw std::invalid_argument("Expected type for parameter '" + name + "': positive double");
     }
     else
-        throw std::invalid_argument("Parameter '" + name + "' does not exist.");
+    {
+        SC_REPORT_WARNING("utils", ("Parameter '" + name + "' does not exist, default is 1.").c_str());
+        return 1;
+    }
 }
 
-std::string parseString(json &obj, const std::string &name)
+std::string parseString(json &spec, const std::string &name)
 {
-    if (!obj.empty())
+    json param = spec[name];
+    if (!param.empty())
     {
-        if (obj.is_string())
-            return obj;
+        if (param.is_string())
+            return param;
         else
             throw std::invalid_argument("Expected type for parameter '" + name + "': string");
     }
     else
-        throw std::invalid_argument("Parameter '" + name + "' does not exist.");
+    {
+        SC_REPORT_WARNING("utils", ("Parameter '" + name + "' does not exist.").c_str());
+        return {};
+    }
 }
 
 void setUpDummy(tlm_generic_payload &payload, uint64_t channelPayloadID, Rank rank, BankGroup bankGroup, Bank bank)
diff --git a/DRAMSys/library/src/common/utils.h b/DRAMSys/library/src/common/utils.h
index 85fedc9d..184b6efe 100644
--- a/DRAMSys/library/src/common/utils.h
+++ b/DRAMSys/library/src/common/utils.h
@@ -64,10 +64,10 @@ constexpr const char headline[] =
 std::string getPhaseName(const tlm::tlm_phase &phase);
 
 nlohmann::json parseJSON(const std::string &path);
-bool parseBool(nlohmann::json &obj, const std::string &name);
-unsigned int parseUint(nlohmann::json &obj, const std::string &name);
-double parseUdouble(nlohmann::json &obj, const std::string &name);
-std::string parseString(nlohmann::json &obj, const std::string &name);
+bool parseBool(nlohmann::json &spec, const std::string &name);
+unsigned int parseUint(nlohmann::json &spec, const std::string &name);
+double parseUdouble(nlohmann::json &spec, const std::string &name);
+std::string parseString(nlohmann::json &spec, const std::string &name);
 
 void setUpDummy(tlm::tlm_generic_payload &payload, uint64_t channelPayloadID,
                 Rank rank = Rank(0), BankGroup bankGroup = BankGroup(0), Bank bank = Bank(0));
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp
index 7929150d..e22eb7f1 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp
@@ -53,16 +53,16 @@ MemSpec::MemSpec(json &memspec, MemoryType memoryType,
       numberOfBanks(numberOfBanks),
       numberOfBankGroups(numberOfBankGroups),
       numberOfDevicesOnDIMM(numberOfDevicesOnDIMM),
-      numberOfRows(parseUint(memspec["memarchitecturespec"]["nbrOfRows"],"nbrOfRows")),
-      numberOfColumns(parseUint(memspec["memarchitecturespec"]["nbrOfColumns"],"nbrOfColumns")),
-      burstLength(parseUint(memspec["memarchitecturespec"]["burstLength"],"burstLength")),
-      dataRate(parseUint(memspec["memarchitecturespec"]["dataRate"],"dataRate")),
-      bitWidth(parseUint(memspec["memarchitecturespec"]["width"],"width")),
+      numberOfRows(parseUint(memspec["memarchitecturespec"], "nbrOfRows")),
+      numberOfColumns(parseUint(memspec["memarchitecturespec"], "nbrOfColumns")),
+      burstLength(parseUint(memspec["memarchitecturespec"], "burstLength")),
+      dataRate(parseUint(memspec["memarchitecturespec"], "dataRate")),
+      bitWidth(parseUint(memspec["memarchitecturespec"], "width")),
       dataBusWidth(bitWidth * numberOfDevicesOnDIMM),
       bytesPerBurst((burstLength * dataBusWidth) / 8),
-      fCKMHz(parseUdouble(memspec["memtimingspec"]["clkMhz"], "clkMhz")),
+      fCKMHz(parseUdouble(memspec["memtimingspec"], "clkMhz")),
       tCK(sc_time(1.0 / fCKMHz, SC_US)),
-      memoryId(parseString(memspec["memoryId"], "memoryId")),
+      memoryId(parseString(memspec, "memoryId")),
       memoryType(memoryType),
       burstDuration(tCK * (static_cast<double>(burstLength) / dataRate)),
       memorySizeBytes(0)
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp
index 020b0b9f..fde1ea69 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp
@@ -44,54 +44,54 @@ using json = nlohmann::json;
 
 MemSpecDDR3::MemSpecDDR3(json &memspec)
     : MemSpec(memspec, MemoryType::DDR3,
-      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfChannels"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
       1,
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
-          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfDevicesOnDIMM"],"nbrOfDevicesOnDIMM")),
-      tCKE     (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
+          * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfDevicesOnDIMM")),
+      tCKE     (tCK * parseUint(memspec["memtimingspec"], "CKE")),
       tPD      (tCKE),
-      tCKESR   (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")),
-      tDQSCK   (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),
-      tRAS     (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
-      tRC      (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
-      tRCD     (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")),
-      tRL      (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")),
-      tRTP     (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
-      tWL      (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
-      tWR      (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
-      tXP      (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
-      tXS      (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")),
-      tCCD     (tCK * parseUint(memspec["memtimingspec"]["CCD"], "CCD")),
-      tFAW     (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
-      tREFI    (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")),
-      tRFC     (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")),
-      tRP      (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
-      tRRD     (tCK * parseUint(memspec["memtimingspec"]["RRD"], "RRD")),
-      tWTR     (tCK * parseUint(memspec["memtimingspec"]["WTR"], "WTR")),
-      tAL      (tCK * parseUint(memspec["memtimingspec"]["AL"], "AL")),
-      tXPDLL   (tCK * parseUint(memspec["memtimingspec"]["XPDLL"], "XPDLL")),
-      tXSDLL   (tCK * parseUint(memspec["memtimingspec"]["XSDLL"], "XSDLL")),
-      tACTPDEN (tCK * parseUint(memspec["memtimingspec"]["ACTPDEN"], "ACTPDEN")),
-      tPRPDEN  (tCK * parseUint(memspec["memtimingspec"]["PRPDEN"], "PRPDEN")),
-      tREFPDEN (tCK * parseUint(memspec["memtimingspec"]["REFPDEN"], "REFPDEN")),
-      tRTRS    (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS")),
-      iDD0     (parseUdouble(memspec["mempowerspec"]["idd0"], "idd0")),
-      iDD2N    (parseUdouble(memspec["mempowerspec"]["idd2n"], "idd2n")),
-      iDD3N    (parseUdouble(memspec["mempowerspec"]["idd3n"], "idd3n")),
-      iDD4R    (parseUdouble(memspec["mempowerspec"]["idd4r"], "idd4r")),
-      iDD4W    (parseUdouble(memspec["mempowerspec"]["idd4w"], "idd4w")),
-      iDD5     (parseUdouble(memspec["mempowerspec"]["idd5"], "idd5")),
-      iDD6     (parseUdouble(memspec["mempowerspec"]["idd6"], "idd6")),
-      vDD      (parseUdouble(memspec["mempowerspec"]["vdd"], "vdd")),
-      iDD2P0   (parseUdouble(memspec["mempowerspec"]["idd2p0"], "idd2p0")),
-      iDD2P1   (parseUdouble(memspec["mempowerspec"]["idd2p1"], "idd2p1")),
-      iDD3P0   (parseUdouble(memspec["mempowerspec"]["idd3p0"], "idd3p0")),
-      iDD3P1   (parseUdouble(memspec["mempowerspec"]["idd3p1"], "idd3p1"))
+      tCKESR   (tCK * parseUint(memspec["memtimingspec"], "CKESR")),
+      tDQSCK   (tCK * parseUint(memspec["memtimingspec"], "DQSCK")),
+      tRAS     (tCK * parseUint(memspec["memtimingspec"], "RAS")),
+      tRC      (tCK * parseUint(memspec["memtimingspec"], "RC")),
+      tRCD     (tCK * parseUint(memspec["memtimingspec"], "RCD")),
+      tRL      (tCK * parseUint(memspec["memtimingspec"], "RL")),
+      tRTP     (tCK * parseUint(memspec["memtimingspec"], "RTP")),
+      tWL      (tCK * parseUint(memspec["memtimingspec"], "WL")),
+      tWR      (tCK * parseUint(memspec["memtimingspec"], "WR")),
+      tXP      (tCK * parseUint(memspec["memtimingspec"], "XP")),
+      tXS      (tCK * parseUint(memspec["memtimingspec"], "XS")),
+      tCCD     (tCK * parseUint(memspec["memtimingspec"], "CCD")),
+      tFAW     (tCK * parseUint(memspec["memtimingspec"], "FAW")),
+      tREFI    (tCK * parseUint(memspec["memtimingspec"], "REFI")),
+      tRFC     (tCK * parseUint(memspec["memtimingspec"], "RFC")),
+      tRP      (tCK * parseUint(memspec["memtimingspec"], "RP")),
+      tRRD     (tCK * parseUint(memspec["memtimingspec"], "RRD")),
+      tWTR     (tCK * parseUint(memspec["memtimingspec"], "WTR")),
+      tAL      (tCK * parseUint(memspec["memtimingspec"], "AL")),
+      tXPDLL   (tCK * parseUint(memspec["memtimingspec"], "XPDLL")),
+      tXSDLL   (tCK * parseUint(memspec["memtimingspec"], "XSDLL")),
+      tACTPDEN (tCK * parseUint(memspec["memtimingspec"], "ACTPDEN")),
+      tPRPDEN  (tCK * parseUint(memspec["memtimingspec"], "PRPDEN")),
+      tREFPDEN (tCK * parseUint(memspec["memtimingspec"], "REFPDEN")),
+      tRTRS    (tCK * parseUint(memspec["memtimingspec"], "RTRS")),
+      iDD0     (parseUdouble(memspec["mempowerspec"], "idd0")),
+      iDD2N    (parseUdouble(memspec["mempowerspec"], "idd2n")),
+      iDD3N    (parseUdouble(memspec["mempowerspec"], "idd3n")),
+      iDD4R    (parseUdouble(memspec["mempowerspec"], "idd4r")),
+      iDD4W    (parseUdouble(memspec["mempowerspec"], "idd4w")),
+      iDD5     (parseUdouble(memspec["mempowerspec"], "idd5")),
+      iDD6     (parseUdouble(memspec["mempowerspec"], "idd6")),
+      vDD      (parseUdouble(memspec["mempowerspec"], "vdd")),
+      iDD2P0   (parseUdouble(memspec["mempowerspec"], "idd2p0")),
+      iDD2P1   (parseUdouble(memspec["mempowerspec"], "idd2p1")),
+      iDD3P0   (parseUdouble(memspec["mempowerspec"], "idd3p0")),
+      iDD3P1   (parseUdouble(memspec["mempowerspec"], "idd3p1"))
 {
     uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
     uint64_t deviceSizeBytes = deviceSizeBits / 8;
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp
index 25c5970a..6f29e509 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp
@@ -44,72 +44,72 @@ using json = nlohmann::json;
 
 MemSpecDDR4::MemSpecDDR4(json &memspec)
     : MemSpec(memspec, MemoryType::DDR4,
-      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
-          / parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
-          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups")
-          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfDevicesOnDIMM"],"nbrOfDevicesOnDIMM")),
-      tCKE     (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
+      parseUint(memspec["memarchitecturespec"],"nbrOfChannels"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
+      parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
+          / parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
+          * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups")
+          * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfDevicesOnDIMM")),
+      tCKE     (tCK * parseUint(memspec["memtimingspec"], "CKE")),
       tPD      (tCKE),
-      tCKESR   (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")),
-      tRAS     (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
-      tRC      (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
-      tRCD     (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")),
-      tRL      (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")),
-      tRPRE    (tCK * parseUint(memspec["memtimingspec"]["RPRE"], "RPRE")),
-      tRTP     (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
-      tWL      (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
-      tWPRE    (tCK * parseUint(memspec["memtimingspec"]["WPRE"], "WPRE")),
-      tWR      (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
-      tXP      (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
-      tXS      (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")),
-      tREFI    ((parseUint(memspec["memtimingspec"]["REFM"], "REFM") == 4) ?
-                   (tCK * (static_cast<double>(parseUint(memspec["memtimingspec"]["REFI"], "REFI")) / 4)) :
-                   ((parseUint(memspec["memtimingspec"]["REFM"], "REFM") == 2) ?
-                   (tCK * (static_cast<double>(parseUint(memspec["memtimingspec"]["REFI"], "REFI")) / 2)) :
-                   (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")))),
-      tRFC     ((parseUint(memspec["memtimingspec"]["REFM"], "REFM") == 4) ?
-                   (tCK * parseUint(memspec["memtimingspec"]["RFC4"], "RFC4")) :
-                   ((parseUint(memspec["memtimingspec"]["REFM"], "REFM") == 2) ?
-                   (tCK * parseUint(memspec["memtimingspec"]["RFC2"], "RFC2")) :
-                   (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")))),
-      tRP      (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
-      tDQSCK   (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),
-      tCCD_S   (tCK * parseUint(memspec["memtimingspec"]["CCD_S"], "CCD_S")),
-      tCCD_L   (tCK * parseUint(memspec["memtimingspec"]["CCD_L"], "CCD_L")),
-      tFAW     (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
-      tRRD_S   (tCK * parseUint(memspec["memtimingspec"]["RRD_S"], "RRD_S")),
-      tRRD_L   (tCK * parseUint(memspec["memtimingspec"]["RRD_L"], "RRD_L")),
-      tWTR_S   (tCK * parseUint(memspec["memtimingspec"]["WTR_S"], "WTR_S")),
-      tWTR_L   (tCK * parseUint(memspec["memtimingspec"]["WTR_L"], "WTR_L")),
-      tAL      (tCK * parseUint(memspec["memtimingspec"]["AL"], "AL")),
-      tXPDLL   (tCK * parseUint(memspec["memtimingspec"]["XPDLL"], "XPDLL")),
-      tXSDLL   (tCK * parseUint(memspec["memtimingspec"]["XSDLL"], "XSDLL")),
-      tACTPDEN (tCK * parseUint(memspec["memtimingspec"]["ACTPDEN"], "ACTPDEN")),
-      tPRPDEN  (tCK * parseUint(memspec["memtimingspec"]["PRPDEN"], "PRPDEN")),
-      tREFPDEN (tCK * parseUint(memspec["memtimingspec"]["REFPDEN"], "REFPDEN")),
-      tRTRS    (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS")),
-      iDD0     (parseUdouble(memspec["mempowerspec"]["idd0"], "idd0")),
-      iDD2N    (parseUdouble(memspec["mempowerspec"]["idd2n"], "idd2n")),
-      iDD3N    (parseUdouble(memspec["mempowerspec"]["idd3n"], "idd3n")),
-      iDD4R    (parseUdouble(memspec["mempowerspec"]["idd4r"], "idd4r")),
-      iDD4W    (parseUdouble(memspec["mempowerspec"]["idd4w"], "idd4w")),
-      iDD5     (parseUdouble(memspec["mempowerspec"]["idd5"], "idd5")),
-      iDD6     (parseUdouble(memspec["mempowerspec"]["idd6"], "idd6")),
-      vDD      (parseUdouble(memspec["mempowerspec"]["vdd"], "vdd")),
-      iDD02    (parseUdouble(memspec["mempowerspec"]["idd02"], "idd02")),
-      iDD2P0   (parseUdouble(memspec["mempowerspec"]["idd2p0"], "idd2p0")),
-      iDD2P1   (parseUdouble(memspec["mempowerspec"]["idd2p1"], "idd2p1")),
-      iDD3P0   (parseUdouble(memspec["mempowerspec"]["idd3p0"], "idd3p0")),
-      iDD3P1   (parseUdouble(memspec["mempowerspec"]["idd3p1"], "idd3p1")),
-      iDD62    (parseUdouble(memspec["mempowerspec"]["idd62"], "idd62")),
-      vDD2     (parseUdouble(memspec["mempowerspec"]["vdd2"], "vdd2"))
+      tCKESR   (tCK * parseUint(memspec["memtimingspec"], "CKESR")),
+      tRAS     (tCK * parseUint(memspec["memtimingspec"], "RAS")),
+      tRC      (tCK * parseUint(memspec["memtimingspec"], "RC")),
+      tRCD     (tCK * parseUint(memspec["memtimingspec"], "RCD")),
+      tRL      (tCK * parseUint(memspec["memtimingspec"], "RL")),
+      tRPRE    (tCK * parseUint(memspec["memtimingspec"], "RPRE")),
+      tRTP     (tCK * parseUint(memspec["memtimingspec"], "RTP")),
+      tWL      (tCK * parseUint(memspec["memtimingspec"], "WL")),
+      tWPRE    (tCK * parseUint(memspec["memtimingspec"], "WPRE")),
+      tWR      (tCK * parseUint(memspec["memtimingspec"], "WR")),
+      tXP      (tCK * parseUint(memspec["memtimingspec"], "XP")),
+      tXS      (tCK * parseUint(memspec["memtimingspec"], "XS")),
+      tREFI    ((parseUint(memspec["memtimingspec"], "REFM") == 4) ?
+                   (tCK * (static_cast<double>(parseUint(memspec["memtimingspec"], "REFI")) / 4)) :
+                   ((parseUint(memspec["memtimingspec"], "REFM") == 2) ?
+                   (tCK * (static_cast<double>(parseUint(memspec["memtimingspec"], "REFI")) / 2)) :
+                   (tCK * parseUint(memspec["memtimingspec"], "REFI")))),
+      tRFC     ((parseUint(memspec["memtimingspec"], "REFM") == 4) ?
+                   (tCK * parseUint(memspec["memtimingspec"], "RFC4")) :
+                   ((parseUint(memspec["memtimingspec"], "REFM") == 2) ?
+                   (tCK * parseUint(memspec["memtimingspec"], "RFC2")) :
+                   (tCK * parseUint(memspec["memtimingspec"], "RFC")))),
+      tRP      (tCK * parseUint(memspec["memtimingspec"], "RP")),
+      tDQSCK   (tCK * parseUint(memspec["memtimingspec"], "DQSCK")),
+      tCCD_S   (tCK * parseUint(memspec["memtimingspec"], "CCD_S")),
+      tCCD_L   (tCK * parseUint(memspec["memtimingspec"], "CCD_L")),
+      tFAW     (tCK * parseUint(memspec["memtimingspec"], "FAW")),
+      tRRD_S   (tCK * parseUint(memspec["memtimingspec"], "RRD_S")),
+      tRRD_L   (tCK * parseUint(memspec["memtimingspec"], "RRD_L")),
+      tWTR_S   (tCK * parseUint(memspec["memtimingspec"], "WTR_S")),
+      tWTR_L   (tCK * parseUint(memspec["memtimingspec"], "WTR_L")),
+      tAL      (tCK * parseUint(memspec["memtimingspec"], "AL")),
+      tXPDLL   (tCK * parseUint(memspec["memtimingspec"], "XPDLL")),
+      tXSDLL   (tCK * parseUint(memspec["memtimingspec"], "XSDLL")),
+      tACTPDEN (tCK * parseUint(memspec["memtimingspec"], "ACTPDEN")),
+      tPRPDEN  (tCK * parseUint(memspec["memtimingspec"], "PRPDEN")),
+      tREFPDEN (tCK * parseUint(memspec["memtimingspec"], "REFPDEN")),
+      tRTRS    (tCK * parseUint(memspec["memtimingspec"], "RTRS")),
+      iDD0     (parseUdouble(memspec["mempowerspec"], "idd0")),
+      iDD2N    (parseUdouble(memspec["mempowerspec"], "idd2n")),
+      iDD3N    (parseUdouble(memspec["mempowerspec"], "idd3n")),
+      iDD4R    (parseUdouble(memspec["mempowerspec"], "idd4r")),
+      iDD4W    (parseUdouble(memspec["mempowerspec"], "idd4w")),
+      iDD5     (parseUdouble(memspec["mempowerspec"], "idd5")),
+      iDD6     (parseUdouble(memspec["mempowerspec"], "idd6")),
+      vDD      (parseUdouble(memspec["mempowerspec"], "vdd")),
+      iDD02    (parseUdouble(memspec["mempowerspec"], "idd02")),
+      iDD2P0   (parseUdouble(memspec["mempowerspec"], "idd2p0")),
+      iDD2P1   (parseUdouble(memspec["mempowerspec"], "idd2p1")),
+      iDD3P0   (parseUdouble(memspec["mempowerspec"], "idd3p0")),
+      iDD3P1   (parseUdouble(memspec["mempowerspec"], "idd3p1")),
+      iDD62    (parseUdouble(memspec["mempowerspec"], "idd62")),
+      vDD2     (parseUdouble(memspec["mempowerspec"], "vdd2"))
 {
     uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
     uint64_t deviceSizeBytes = deviceSizeBits / 8;
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp
index 1a2b4a45..ba3de486 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp
@@ -44,76 +44,76 @@ using json = nlohmann::json;
 
 MemSpecDDR5::MemSpecDDR5(json &memspec)
     : MemSpec(memspec, MemoryType::DDR5,
-      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
-              / parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
-              * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups")
-              * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfDevicesOnDIMM"],"nbrOfDevicesOnDIMM")),
-      numberOfDIMMRanks(parseUint(memspec["memarchitecturespec"]["nbrOfDIMMRanks"], "nbrOfDIMMRanks")),
-      physicalRanksPerDIMMRank(parseUint(memspec["memarchitecturespec"]["nbrOfPhysicalRanks"], "nbrOfPhysicalRanks")),
+      parseUint(memspec["memarchitecturespec"], "nbrOfChannels"),
+      parseUint(memspec["memarchitecturespec"], "nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"], "nbrOfBanks"),
+      parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
+              / parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
+              * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups")
+              * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfDevicesOnDIMM")),
+      numberOfDIMMRanks(parseUint(memspec["memarchitecturespec"], "nbrOfDIMMRanks")),
+      physicalRanksPerDIMMRank(parseUint(memspec["memarchitecturespec"], "nbrOfPhysicalRanks")),
       numberOfPhysicalRanks(physicalRanksPerDIMMRank * numberOfDIMMRanks),
-      logicalRanksPerPhysicalRank(parseUint(memspec["memarchitecturespec"]["nbrOfLogicalRanks"], "nbrOfLogicalRanks")),
+      logicalRanksPerPhysicalRank(parseUint(memspec["memarchitecturespec"], "nbrOfLogicalRanks")),
       numberOfLogicalRanks(logicalRanksPerPhysicalRank * numberOfPhysicalRanks),
-      cmdMode(parseUint(memspec["memarchitecturespec"]["cmdMode"], "cmdMode")),
-      refMode(parseUint(memspec["memarchitecturespec"]["refMode"], "refMode")),
-      RAAIMT(parseUint(memspec["memarchitecturespec"]["RAAIMT"], "RAAIMT")),
-      RAAMMT(parseUint(memspec["memarchitecturespec"]["RAAMMT"], "RAAMMT")),
-      RAACDR(parseUint(memspec["memarchitecturespec"]["RAACDR"], "RAACDR")),
-      tRCD           (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")),
-      tPPD           (tCK * parseUint(memspec["memtimingspec"]["PPD"], "PPD")),
-      tRP            (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
-      tRAS           (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
+      cmdMode(parseUint(memspec["memarchitecturespec"], "cmdMode")),
+      refMode(parseUint(memspec["memarchitecturespec"], "refMode")),
+      RAAIMT(parseUint(memspec["memarchitecturespec"], "RAAIMT")),
+      RAAMMT(parseUint(memspec["memarchitecturespec"], "RAAMMT")),
+      RAACDR(parseUint(memspec["memarchitecturespec"], "RAACDR")),
+      tRCD           (tCK * parseUint(memspec["memtimingspec"], "RCD")),
+      tPPD           (tCK * parseUint(memspec["memtimingspec"], "PPD")),
+      tRP            (tCK * parseUint(memspec["memtimingspec"], "RP")),
+      tRAS           (tCK * parseUint(memspec["memtimingspec"], "RAS")),
       tRC            (tRAS + tRP),
-      tRL            (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")),
-      tRTP           (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
-      tRPRE          (tCK * parseUint(memspec["memtimingspec"]["RPRE"], "RPRE")),
-      tRPST          (tCK * parseUint(memspec["memtimingspec"]["RPST"], "RPST")),
-      tRDDQS         (tCK * parseUint(memspec["memtimingspec"]["RDDQS"], "RDDQS")),
-      tWL            (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
-      tWPRE          (tCK * parseUint(memspec["memtimingspec"]["WPRE"], "WPRE")),
-      tWPST          (tCK * parseUint(memspec["memtimingspec"]["WPST"], "WPST")),
-      tWR            (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
-      tCCD_L_slr     (tCK * parseUint(memspec["memtimingspec"]["CCD_L_slr"], "CCD_L_slr")),
-      tCCD_L_WR_slr  (tCK * parseUint(memspec["memtimingspec"]["CCD_L_WR_slr"], "CCD_L_WR_slr")),
-      tCCD_L_WR2_slr (tCK * parseUint(memspec["memtimingspec"]["CCD_L_WR2_slr"], "CCD_L_WR2_slr")),
-      tCCD_S_slr     (tCK * parseUint(memspec["memtimingspec"]["CCD_S_slr"], "CCD_S_slr")),
-      tCCD_S_WR_slr  (tCK * parseUint(memspec["memtimingspec"]["CCD_S_WR_slr"], "CCD_S_WR_slr")),
-      tCCD_dlr       (tCK * parseUint(memspec["memtimingspec"]["CCD_dlr"], "CCD_dlr")),
-      tCCD_WR_dlr    (tCK * parseUint(memspec["memtimingspec"]["CCD_WR_dlr"], "CCD_WR_dlr")),
-      tCCD_WR_dpr    (tCK * parseUint(memspec["memtimingspec"]["CCD_WR_dpr"], "CCD_WR_dpr")),
-      tRRD_L_slr     (tCK * parseUint(memspec["memtimingspec"]["RRD_L_slr"], "RRD_L_slr")),
-      tRRD_S_slr     (tCK * parseUint(memspec["memtimingspec"]["RRD_S_slr"], "RRD_S_slr")),
-      tRRD_dlr       (tCK * parseUint(memspec["memtimingspec"]["RRD_dlr"], "RRD_dlr")),
-      tFAW_slr       (tCK * parseUint(memspec["memtimingspec"]["FAW_slr"], "FAW_slr")),
-      tFAW_dlr       (tCK * parseUint(memspec["memtimingspec"]["FAW_dlr"], "FAW_dlr")),
-      tWTR_L         (tCK * parseUint(memspec["memtimingspec"]["WTR_L"], "WTR_L")),
-      tWTR_S         (tCK * parseUint(memspec["memtimingspec"]["WTR_S"], "WTR_S")),
-      tRFC_slr       ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"]["RFC1_slr"], "RFC1_slr")
-                             : tCK * parseUint(memspec["memtimingspec"]["RFC2_slr"], "RFC2_slr")),
-      tRFC_dlr       ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"]["RFC1_dlr"], "RFC1_dlr")
-                             : tCK * parseUint(memspec["memtimingspec"]["RFC2_dlr"], "RFC2_dlr")),
-      tRFC_dpr       ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"]["RFC1_dpr"], "RFC1_dpr")
-                             : tCK * parseUint(memspec["memtimingspec"]["RFC2_dpr"], "RFC2_dpr")),
-      tRFCsb_slr     (tCK * parseUint(memspec["memtimingspec"]["RFCsb_slr"], "RFCsb_slr")),
-      tRFCsb_dlr     (tCK * parseUint(memspec["memtimingspec"]["RFCsb_dlr"], "RFCsb_dlr")),
-      tREFI          ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"]["REFI1"], "REFI1")
-                             : tCK * parseUint(memspec["memtimingspec"]["REFI2"], "REFI2")),
-      tREFIsb        (tCK * parseUint(memspec["memtimingspec"]["REFISB"], "REFISB")),
-      tREFSBRD_slr   (tCK * parseUint(memspec["memtimingspec"]["REFSBRD_slr"], "REFSBRD_slr")),
-      tREFSBRD_dlr   (tCK * parseUint(memspec["memtimingspec"]["REFSBRD_dlr"], "REFSBRD_dlr")),
-      tRTRS          (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS")),
-      tCPDED         (tCK * parseUint(memspec["memtimingspec"]["CPDED"], "CPDED")),
-      tPD            (tCK * parseUint(memspec["memtimingspec"]["PD"], "PD")),
-      tXP            (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
-      tACTPDEN       (tCK * parseUint(memspec["memtimingspec"]["ACTPDEN"], "ACTPDEN")),
-      tPRPDEN        (tCK * parseUint(memspec["memtimingspec"]["PRPDEN"], "PRPDEN")),
-      tREFPDEN       (tCK * parseUint(memspec["memtimingspec"]["REFPDEN"], "REFPDEN")),
+      tRL            (tCK * parseUint(memspec["memtimingspec"], "RL")),
+      tRTP           (tCK * parseUint(memspec["memtimingspec"], "RTP")),
+      tRPRE          (tCK * parseUint(memspec["memtimingspec"], "RPRE")),
+      tRPST          (tCK * parseUint(memspec["memtimingspec"], "RPST")),
+      tRDDQS         (tCK * parseUint(memspec["memtimingspec"], "RDDQS")),
+      tWL            (tCK * parseUint(memspec["memtimingspec"], "WL")),
+      tWPRE          (tCK * parseUint(memspec["memtimingspec"], "WPRE")),
+      tWPST          (tCK * parseUint(memspec["memtimingspec"], "WPST")),
+      tWR            (tCK * parseUint(memspec["memtimingspec"], "WR")),
+      tCCD_L_slr     (tCK * parseUint(memspec["memtimingspec"], "CCD_L_slr")),
+      tCCD_L_WR_slr  (tCK * parseUint(memspec["memtimingspec"], "CCD_L_WR_slr")),
+      tCCD_L_WR2_slr (tCK * parseUint(memspec["memtimingspec"], "CCD_L_WR2_slr")),
+      tCCD_S_slr     (tCK * parseUint(memspec["memtimingspec"], "CCD_S_slr")),
+      tCCD_S_WR_slr  (tCK * parseUint(memspec["memtimingspec"], "CCD_S_WR_slr")),
+      tCCD_dlr       (tCK * parseUint(memspec["memtimingspec"], "CCD_dlr")),
+      tCCD_WR_dlr    (tCK * parseUint(memspec["memtimingspec"], "CCD_WR_dlr")),
+      tCCD_WR_dpr    (tCK * parseUint(memspec["memtimingspec"], "CCD_WR_dpr")),
+      tRRD_L_slr     (tCK * parseUint(memspec["memtimingspec"], "RRD_L_slr")),
+      tRRD_S_slr     (tCK * parseUint(memspec["memtimingspec"], "RRD_S_slr")),
+      tRRD_dlr       (tCK * parseUint(memspec["memtimingspec"], "RRD_dlr")),
+      tFAW_slr       (tCK * parseUint(memspec["memtimingspec"], "FAW_slr")),
+      tFAW_dlr       (tCK * parseUint(memspec["memtimingspec"], "FAW_dlr")),
+      tWTR_L         (tCK * parseUint(memspec["memtimingspec"], "WTR_L")),
+      tWTR_S         (tCK * parseUint(memspec["memtimingspec"], "WTR_S")),
+      tRFC_slr       ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"], "RFC1_slr")
+                             : tCK * parseUint(memspec["memtimingspec"], "RFC2_slr")),
+      tRFC_dlr       ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"], "RFC1_dlr")
+                             : tCK * parseUint(memspec["memtimingspec"], "RFC2_dlr")),
+      tRFC_dpr       ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"], "RFC1_dpr")
+                             : tCK * parseUint(memspec["memtimingspec"], "RFC2_dpr")),
+      tRFCsb_slr     (tCK * parseUint(memspec["memtimingspec"], "RFCsb_slr")),
+      tRFCsb_dlr     (tCK * parseUint(memspec["memtimingspec"], "RFCsb_dlr")),
+      tREFI          ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"], "REFI1")
+                             : tCK * parseUint(memspec["memtimingspec"], "REFI2")),
+      tREFIsb        (tCK * parseUint(memspec["memtimingspec"], "REFISB")),
+      tREFSBRD_slr   (tCK * parseUint(memspec["memtimingspec"], "REFSBRD_slr")),
+      tREFSBRD_dlr   (tCK * parseUint(memspec["memtimingspec"], "REFSBRD_dlr")),
+      tRTRS          (tCK * parseUint(memspec["memtimingspec"], "RTRS")),
+      tCPDED         (tCK * parseUint(memspec["memtimingspec"], "CPDED")),
+      tPD            (tCK * parseUint(memspec["memtimingspec"], "PD")),
+      tXP            (tCK * parseUint(memspec["memtimingspec"], "XP")),
+      tACTPDEN       (tCK * parseUint(memspec["memtimingspec"], "ACTPDEN")),
+      tPRPDEN        (tCK * parseUint(memspec["memtimingspec"], "PRPDEN")),
+      tREFPDEN       (tCK * parseUint(memspec["memtimingspec"], "REFPDEN")),
       shortCmdOffset (cmdMode == 2 ? 1 * tCK : 0 * tCK),
       longCmdOffset  (cmdMode == 2 ? 3 * tCK : 1 * tCK),
       tBURST16(tCK * 8),
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp
index 83efd921..b681ac06 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp
@@ -44,51 +44,51 @@ using json = nlohmann::json;
 
 MemSpecGDDR5::MemSpecGDDR5(json &memspec)
     : MemSpec(memspec, MemoryType::GDDR5,
-      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
-          / parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
-          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups")
-          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfChannels"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
+      parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
+          / parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
+          * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups")
+          * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
       1),
-      tRP        (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
-      tRAS       (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
-      tRC        (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
-      tRCDRD     (tCK * parseUint(memspec["memtimingspec"]["RCDRD"], "RCDRD")),
-      tRCDWR     (tCK * parseUint(memspec["memtimingspec"]["RCDWR"], "RCDWR")),
-      tRTP       (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
-      tRRDS      (tCK * parseUint(memspec["memtimingspec"]["RRDS"], "RRDS")),
-      tRRDL      (tCK * parseUint(memspec["memtimingspec"]["RRDL"], "RRDL")),
-      tCCDS      (tCK * parseUint(memspec["memtimingspec"]["CCDS"], "CCDS")),
-      tCCDL      (tCK * parseUint(memspec["memtimingspec"]["CCDL"], "CCDL")),
-      tCL        (tCK * parseUint(memspec["memtimingspec"]["CL"], "CL")),
-      tWCK2CKPIN (tCK * parseUint(memspec["memtimingspec"]["WCK2CKPIN"], "WCK2CKPIN")),
-      tWCK2CK    (tCK * parseUint(memspec["memtimingspec"]["WCK2CK"], "WCK2CK")),
-      tWCK2DQO   (tCK * parseUint(memspec["memtimingspec"]["WCK2DQO"], "WCK2DQO")),
-      tRTW       (tCK * parseUint(memspec["memtimingspec"]["RTW"], "RTW")),
-      tWL        (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
-      tWCK2DQI   (tCK * parseUint(memspec["memtimingspec"]["WCK2DQI"], "WCK2DQI")),
-      tWR        (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
-      tWTRS      (tCK * parseUint(memspec["memtimingspec"]["WTRS"], "WTRS")),
-      tWTRL      (tCK * parseUint(memspec["memtimingspec"]["WTRL"], "WTRL")),
-      tCKE       (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
-      tPD        (tCK * parseUint(memspec["memtimingspec"]["PD"], "PD")),
-      tXPN       (tCK * parseUint(memspec["memtimingspec"]["XPN"], "XPN")),
-      tREFI      (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")),
-      tREFIPB    (tCK * parseUint(memspec["memtimingspec"]["REFIPB"], "REFIPB")),
-      tRFC       (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")),
-      tRFCPB     (tCK * parseUint(memspec["memtimingspec"]["RFCPB"], "RFCPB")),
-      tRREFD     (tCK * parseUint(memspec["memtimingspec"]["RREFD"], "RREFD")),
-      tXS        (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")),
-      tFAW       (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
-      t32AW      (tCK * parseUint(memspec["memtimingspec"]["32AW"], "32AW")),
-      tPPD       (tCK * parseUint(memspec["memtimingspec"]["PPD"], "PPD")),
-      tLK        (tCK * parseUint(memspec["memtimingspec"]["LK"], "LK")),
-      tRTRS      (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS"))
+      tRP        (tCK * parseUint(memspec["memtimingspec"], "RP")),
+      tRAS       (tCK * parseUint(memspec["memtimingspec"], "RAS")),
+      tRC        (tCK * parseUint(memspec["memtimingspec"], "RC")),
+      tRCDRD     (tCK * parseUint(memspec["memtimingspec"], "RCDRD")),
+      tRCDWR     (tCK * parseUint(memspec["memtimingspec"], "RCDWR")),
+      tRTP       (tCK * parseUint(memspec["memtimingspec"], "RTP")),
+      tRRDS      (tCK * parseUint(memspec["memtimingspec"], "RRDS")),
+      tRRDL      (tCK * parseUint(memspec["memtimingspec"], "RRDL")),
+      tCCDS      (tCK * parseUint(memspec["memtimingspec"], "CCDS")),
+      tCCDL      (tCK * parseUint(memspec["memtimingspec"], "CCDL")),
+      tCL        (tCK * parseUint(memspec["memtimingspec"], "CL")),
+      tWCK2CKPIN (tCK * parseUint(memspec["memtimingspec"], "WCK2CKPIN")),
+      tWCK2CK    (tCK * parseUint(memspec["memtimingspec"], "WCK2CK")),
+      tWCK2DQO   (tCK * parseUint(memspec["memtimingspec"], "WCK2DQO")),
+      tRTW       (tCK * parseUint(memspec["memtimingspec"], "RTW")),
+      tWL        (tCK * parseUint(memspec["memtimingspec"], "WL")),
+      tWCK2DQI   (tCK * parseUint(memspec["memtimingspec"], "WCK2DQI")),
+      tWR        (tCK * parseUint(memspec["memtimingspec"], "WR")),
+      tWTRS      (tCK * parseUint(memspec["memtimingspec"], "WTRS")),
+      tWTRL      (tCK * parseUint(memspec["memtimingspec"], "WTRL")),
+      tCKE       (tCK * parseUint(memspec["memtimingspec"], "CKE")),
+      tPD        (tCK * parseUint(memspec["memtimingspec"], "PD")),
+      tXPN       (tCK * parseUint(memspec["memtimingspec"], "XPN")),
+      tREFI      (tCK * parseUint(memspec["memtimingspec"], "REFI")),
+      tREFIPB    (tCK * parseUint(memspec["memtimingspec"], "REFIPB")),
+      tRFC       (tCK * parseUint(memspec["memtimingspec"], "RFC")),
+      tRFCPB     (tCK * parseUint(memspec["memtimingspec"], "RFCPB")),
+      tRREFD     (tCK * parseUint(memspec["memtimingspec"], "RREFD")),
+      tXS        (tCK * parseUint(memspec["memtimingspec"], "XS")),
+      tFAW       (tCK * parseUint(memspec["memtimingspec"], "FAW")),
+      t32AW      (tCK * parseUint(memspec["memtimingspec"], "32AW")),
+      tPPD       (tCK * parseUint(memspec["memtimingspec"], "PPD")),
+      tLK        (tCK * parseUint(memspec["memtimingspec"], "LK")),
+      tRTRS      (tCK * parseUint(memspec["memtimingspec"], "RTRS"))
 {
     uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
     uint64_t deviceSizeBytes = deviceSizeBits / 8;
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp
index 3481c139..fe396212 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp
@@ -43,51 +43,51 @@ using json = nlohmann::json;
 
 MemSpecGDDR5X::MemSpecGDDR5X(json &memspec)
     : MemSpec(memspec, MemoryType::GDDR5X,
-      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
-          / parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
-          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups")
-          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfChannels"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
+      parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
+          / parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
+          * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups")
+          * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
       1),
-      tRP        (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
-      tRAS       (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
-      tRC        (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
-      tRCDRD     (tCK * parseUint(memspec["memtimingspec"]["RCDRD"], "RCDRD")),
-      tRCDWR     (tCK * parseUint(memspec["memtimingspec"]["RCDWR"], "RCDWR")),
-      tRTP       (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
-      tRRDS      (tCK * parseUint(memspec["memtimingspec"]["RRDS"], "RRDS")),
-      tRRDL      (tCK * parseUint(memspec["memtimingspec"]["RRDL"], "RRDL")),
-      tCCDS      (tCK * parseUint(memspec["memtimingspec"]["CCDS"], "CCDS")),
-      tCCDL      (tCK * parseUint(memspec["memtimingspec"]["CCDL"], "CCDL")),
-      tRL        (tCK * parseUint(memspec["memtimingspec"]["CL"], "CL")),
-      tWCK2CKPIN (tCK * parseUint(memspec["memtimingspec"]["WCK2CKPIN"], "WCK2CKPIN")),
-      tWCK2CK    (tCK * parseUint(memspec["memtimingspec"]["WCK2CK"], "WCK2CK")),
-      tWCK2DQO   (tCK * parseUint(memspec["memtimingspec"]["WCK2DQO"], "WCK2DQO")),
-      tRTW       (tCK * parseUint(memspec["memtimingspec"]["RTW"], "RTW")),
-      tWL        (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
-      tWCK2DQI   (tCK * parseUint(memspec["memtimingspec"]["WCK2DQI"], "WCK2DQI")),
-      tWR        (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
-      tWTRS      (tCK * parseUint(memspec["memtimingspec"]["WTRS"], "WTRS")),
-      tWTRL      (tCK * parseUint(memspec["memtimingspec"]["WTRL"], "WTRL")),
-      tCKE       (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
-      tPD        (tCK * parseUint(memspec["memtimingspec"]["PD"], "PD")),
-      tXP        (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
-      tREFI      (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")),
-      tREFIPB    (tCK * parseUint(memspec["memtimingspec"]["REFIPB"], "REFIPB")),
-      tRFC       (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")),
-      tRFCPB     (tCK * parseUint(memspec["memtimingspec"]["RFCPB"], "RFCPB")),
-      tRREFD     (tCK * parseUint(memspec["memtimingspec"]["RREFD"], "RREFD")),
-      tXS        (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")),
-      tFAW       (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
-      t32AW      (tCK * parseUint(memspec["memtimingspec"]["32AW"], "32AW")),
-      tPPD       (tCK * parseUint(memspec["memtimingspec"]["PPD"], "PPD")),
-      tLK        (tCK * parseUint(memspec["memtimingspec"]["LK"], "LK")),
-      tRTRS      (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS"))
+      tRP        (tCK * parseUint(memspec["memtimingspec"], "RP")),
+      tRAS       (tCK * parseUint(memspec["memtimingspec"], "RAS")),
+      tRC        (tCK * parseUint(memspec["memtimingspec"], "RC")),
+      tRCDRD     (tCK * parseUint(memspec["memtimingspec"], "RCDRD")),
+      tRCDWR     (tCK * parseUint(memspec["memtimingspec"], "RCDWR")),
+      tRTP       (tCK * parseUint(memspec["memtimingspec"], "RTP")),
+      tRRDS      (tCK * parseUint(memspec["memtimingspec"], "RRDS")),
+      tRRDL      (tCK * parseUint(memspec["memtimingspec"], "RRDL")),
+      tCCDS      (tCK * parseUint(memspec["memtimingspec"], "CCDS")),
+      tCCDL      (tCK * parseUint(memspec["memtimingspec"], "CCDL")),
+      tRL        (tCK * parseUint(memspec["memtimingspec"], "CL")),
+      tWCK2CKPIN (tCK * parseUint(memspec["memtimingspec"], "WCK2CKPIN")),
+      tWCK2CK    (tCK * parseUint(memspec["memtimingspec"], "WCK2CK")),
+      tWCK2DQO   (tCK * parseUint(memspec["memtimingspec"], "WCK2DQO")),
+      tRTW       (tCK * parseUint(memspec["memtimingspec"], "RTW")),
+      tWL        (tCK * parseUint(memspec["memtimingspec"], "WL")),
+      tWCK2DQI   (tCK * parseUint(memspec["memtimingspec"], "WCK2DQI")),
+      tWR        (tCK * parseUint(memspec["memtimingspec"], "WR")),
+      tWTRS      (tCK * parseUint(memspec["memtimingspec"], "WTRS")),
+      tWTRL      (tCK * parseUint(memspec["memtimingspec"], "WTRL")),
+      tCKE       (tCK * parseUint(memspec["memtimingspec"], "CKE")),
+      tPD        (tCK * parseUint(memspec["memtimingspec"], "PD")),
+      tXP        (tCK * parseUint(memspec["memtimingspec"], "XP")),
+      tREFI      (tCK * parseUint(memspec["memtimingspec"], "REFI")),
+      tREFIPB    (tCK * parseUint(memspec["memtimingspec"], "REFIPB")),
+      tRFC       (tCK * parseUint(memspec["memtimingspec"], "RFC")),
+      tRFCPB     (tCK * parseUint(memspec["memtimingspec"], "RFCPB")),
+      tRREFD     (tCK * parseUint(memspec["memtimingspec"], "RREFD")),
+      tXS        (tCK * parseUint(memspec["memtimingspec"], "XS")),
+      tFAW       (tCK * parseUint(memspec["memtimingspec"], "FAW")),
+      t32AW      (tCK * parseUint(memspec["memtimingspec"], "32AW")),
+      tPPD       (tCK * parseUint(memspec["memtimingspec"], "PPD")),
+      tLK        (tCK * parseUint(memspec["memtimingspec"], "LK")),
+      tRTRS      (tCK * parseUint(memspec["memtimingspec"], "RTRS"))
 {
     uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
     uint64_t deviceSizeBytes = deviceSizeBits / 8;
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp
index 15748eda..76087278 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp
@@ -44,53 +44,53 @@ using json = nlohmann::json;
 
 MemSpecGDDR6::MemSpecGDDR6(json &memspec)
     : MemSpec(memspec, MemoryType::GDDR6,
-      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
-          / parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
-          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups")
-          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfChannels"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
+      parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
+          / parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
+          * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups")
+          * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
       1),
-      tRP        (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
-      tRAS       (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
-      tRC        (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
-      tRCDRD     (tCK * parseUint(memspec["memtimingspec"]["RCDRD"], "RCDRD")),
-      tRCDWR     (tCK * parseUint(memspec["memtimingspec"]["RCDWR"], "RCDWR")),
-      tRTP       (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
-      tRRDS      (tCK * parseUint(memspec["memtimingspec"]["RRDS"], "RRDS")),
-      tRRDL      (tCK * parseUint(memspec["memtimingspec"]["RRDL"], "RRDL")),
-      tCCDS      (tCK * parseUint(memspec["memtimingspec"]["CCDS"], "CCDS")),
-      tCCDL      (tCK * parseUint(memspec["memtimingspec"]["CCDL"], "CCDL")),
-      tRL        (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")),
-      tWCK2CKPIN (tCK * parseUint(memspec["memtimingspec"]["WCK2CKPIN"], "WCK2CKPIN")),
-      tWCK2CK    (tCK * parseUint(memspec["memtimingspec"]["WCK2CK"], "WCK2CK")),
-      tWCK2DQO   (tCK * parseUint(memspec["memtimingspec"]["WCK2DQO"], "WCK2DQO")),
-      tRTW       (tCK * parseUint(memspec["memtimingspec"]["RTW"], "RTW")),
-      tWL        (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
-      tWCK2DQI   (tCK * parseUint(memspec["memtimingspec"]["WCK2DQI"], "WCK2DQI")),
-      tWR        (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
-      tWTRS      (tCK * parseUint(memspec["memtimingspec"]["WTRS"], "WTRS")),
-      tWTRL      (tCK * parseUint(memspec["memtimingspec"]["WTRL"], "WTRL")),
-      tPD        (tCK * parseUint(memspec["memtimingspec"]["PD"], "PD")),
-      tCKESR     (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")),
-      tXP        (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
-      tREFI      (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")),
-      tREFIPB    (tCK * parseUint(memspec["memtimingspec"]["REFIPB"], "REFIPB")),
-      tRFC       (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")),
-      tRFCPB     (tCK * parseUint(memspec["memtimingspec"]["RFCPB"], "RFCPB")),
-      tRREFD     (tCK * parseUint(memspec["memtimingspec"]["RREFD"], "RREFD")),
-      tXS        (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")),
-      tFAW       (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
-      tPPD       (tCK * parseUint(memspec["memtimingspec"]["PPD"], "PPD")),
-      tLK        (tCK * parseUint(memspec["memtimingspec"]["LK"], "LK")),
-      tACTPDE    (tCK * parseUint(memspec["memtimingspec"]["ACTPDE"], "ACTPDE")),
-      tPREPDE    (tCK * parseUint(memspec["memtimingspec"]["PREPDE"], "PREPDE")),
-      tREFPDE    (tCK * parseUint(memspec["memtimingspec"]["REFPDE"], "REFPDE")),
-      tRTRS      (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS"))
+      tRP        (tCK * parseUint(memspec["memtimingspec"], "RP")),
+      tRAS       (tCK * parseUint(memspec["memtimingspec"], "RAS")),
+      tRC        (tCK * parseUint(memspec["memtimingspec"], "RC")),
+      tRCDRD     (tCK * parseUint(memspec["memtimingspec"], "RCDRD")),
+      tRCDWR     (tCK * parseUint(memspec["memtimingspec"], "RCDWR")),
+      tRTP       (tCK * parseUint(memspec["memtimingspec"], "RTP")),
+      tRRDS      (tCK * parseUint(memspec["memtimingspec"], "RRDS")),
+      tRRDL      (tCK * parseUint(memspec["memtimingspec"], "RRDL")),
+      tCCDS      (tCK * parseUint(memspec["memtimingspec"], "CCDS")),
+      tCCDL      (tCK * parseUint(memspec["memtimingspec"], "CCDL")),
+      tRL        (tCK * parseUint(memspec["memtimingspec"], "RL")),
+      tWCK2CKPIN (tCK * parseUint(memspec["memtimingspec"], "WCK2CKPIN")),
+      tWCK2CK    (tCK * parseUint(memspec["memtimingspec"], "WCK2CK")),
+      tWCK2DQO   (tCK * parseUint(memspec["memtimingspec"], "WCK2DQO")),
+      tRTW       (tCK * parseUint(memspec["memtimingspec"], "RTW")),
+      tWL        (tCK * parseUint(memspec["memtimingspec"], "WL")),
+      tWCK2DQI   (tCK * parseUint(memspec["memtimingspec"], "WCK2DQI")),
+      tWR        (tCK * parseUint(memspec["memtimingspec"], "WR")),
+      tWTRS      (tCK * parseUint(memspec["memtimingspec"], "WTRS")),
+      tWTRL      (tCK * parseUint(memspec["memtimingspec"], "WTRL")),
+      tPD        (tCK * parseUint(memspec["memtimingspec"], "PD")),
+      tCKESR     (tCK * parseUint(memspec["memtimingspec"], "CKESR")),
+      tXP        (tCK * parseUint(memspec["memtimingspec"], "XP")),
+      tREFI      (tCK * parseUint(memspec["memtimingspec"], "REFI")),
+      tREFIPB    (tCK * parseUint(memspec["memtimingspec"], "REFIPB")),
+      tRFC       (tCK * parseUint(memspec["memtimingspec"], "RFC")),
+      tRFCPB     (tCK * parseUint(memspec["memtimingspec"], "RFCPB")),
+      tRREFD     (tCK * parseUint(memspec["memtimingspec"], "RREFD")),
+      tXS        (tCK * parseUint(memspec["memtimingspec"], "XS")),
+      tFAW       (tCK * parseUint(memspec["memtimingspec"], "FAW")),
+      tPPD       (tCK * parseUint(memspec["memtimingspec"], "PPD")),
+      tLK        (tCK * parseUint(memspec["memtimingspec"], "LK")),
+      tACTPDE    (tCK * parseUint(memspec["memtimingspec"], "ACTPDE")),
+      tPREPDE    (tCK * parseUint(memspec["memtimingspec"], "PREPDE")),
+      tREFPDE    (tCK * parseUint(memspec["memtimingspec"], "REFPDE")),
+      tRTRS      (tCK * parseUint(memspec["memtimingspec"], "RTRS"))
 {
     uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
     uint64_t deviceSizeBytes = deviceSizeBits / 8;
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp
index d6c28cf1..a07fa30f 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp
@@ -44,46 +44,46 @@ using json = nlohmann::json;
 
 MemSpecHBM2::MemSpecHBM2(json &memspec)
     : MemSpec(memspec, MemoryType::HBM2,
-      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
-          / parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
-          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBankGroups"], "nbrOfBankGroups")
-          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfChannels"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
+      parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
+          / parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
+          * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups")
+          * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
       1),
-      tDQSCK  (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),
-      tRC     (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
-      tRAS    (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
-      tRCDRD  (tCK * parseUint(memspec["memtimingspec"]["RCDRD"], "RCDRD")),
-      tRCDWR  (tCK * parseUint(memspec["memtimingspec"]["RCDWR"], "RCDWR")),
-      tRRDL   (tCK * parseUint(memspec["memtimingspec"]["RRDL"], "RRDL")),
-      tRRDS   (tCK * parseUint(memspec["memtimingspec"]["RRDS"], "RRDS")),
-      tFAW    (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
-      tRTP    (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
-      tRP     (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
-      tRL     (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")),
-      tWL     (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
-      tPL     (tCK * parseUint(memspec["memtimingspec"]["PL"], "PL")),
-      tWR     (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
-      tCCDL   (tCK * parseUint(memspec["memtimingspec"]["CCDL"], "CCDL")),
-      tCCDS   (tCK * parseUint(memspec["memtimingspec"]["CCDS"], "CCDS")),
-      tWTRL   (tCK * parseUint(memspec["memtimingspec"]["WTRL"], "WTRL")),
-      tWTRS   (tCK * parseUint(memspec["memtimingspec"]["WTRS"], "WTRS")),
-      tRTW    (tCK * parseUint(memspec["memtimingspec"]["RTW"], "RTW")),
-      tXP     (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
-      tCKE    (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
+      tDQSCK  (tCK * parseUint(memspec["memtimingspec"], "DQSCK")),
+      tRC     (tCK * parseUint(memspec["memtimingspec"], "RC")),
+      tRAS    (tCK * parseUint(memspec["memtimingspec"], "RAS")),
+      tRCDRD  (tCK * parseUint(memspec["memtimingspec"], "RCDRD")),
+      tRCDWR  (tCK * parseUint(memspec["memtimingspec"], "RCDWR")),
+      tRRDL   (tCK * parseUint(memspec["memtimingspec"], "RRDL")),
+      tRRDS   (tCK * parseUint(memspec["memtimingspec"], "RRDS")),
+      tFAW    (tCK * parseUint(memspec["memtimingspec"], "FAW")),
+      tRTP    (tCK * parseUint(memspec["memtimingspec"], "RTP")),
+      tRP     (tCK * parseUint(memspec["memtimingspec"], "RP")),
+      tRL     (tCK * parseUint(memspec["memtimingspec"], "RL")),
+      tWL     (tCK * parseUint(memspec["memtimingspec"], "WL")),
+      tPL     (tCK * parseUint(memspec["memtimingspec"], "PL")),
+      tWR     (tCK * parseUint(memspec["memtimingspec"], "WR")),
+      tCCDL   (tCK * parseUint(memspec["memtimingspec"], "CCDL")),
+      tCCDS   (tCK * parseUint(memspec["memtimingspec"], "CCDS")),
+      tWTRL   (tCK * parseUint(memspec["memtimingspec"], "WTRL")),
+      tWTRS   (tCK * parseUint(memspec["memtimingspec"], "WTRS")),
+      tRTW    (tCK * parseUint(memspec["memtimingspec"], "RTW")),
+      tXP     (tCK * parseUint(memspec["memtimingspec"], "XP")),
+      tCKE    (tCK * parseUint(memspec["memtimingspec"], "CKE")),
       tPD     (tCKE),
       tCKESR  (tCKE + tCK),
-      tXS     (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")),
-      tRFC    (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")),
-      tRFCSB  (tCK * parseUint(memspec["memtimingspec"]["RFCSB"], "RFCSB")),
-      tRREFD  (tCK * parseUint(memspec["memtimingspec"]["RREFD"], "RREFD")),
-      tREFI   (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")),
-      tREFISB (tCK * parseUint(memspec["memtimingspec"]["REFISB"], "REFISB"))
+      tXS     (tCK * parseUint(memspec["memtimingspec"], "XS")),
+      tRFC    (tCK * parseUint(memspec["memtimingspec"], "RFC")),
+      tRFCSB  (tCK * parseUint(memspec["memtimingspec"], "RFCSB")),
+      tRREFD  (tCK * parseUint(memspec["memtimingspec"], "RREFD")),
+      tREFI   (tCK * parseUint(memspec["memtimingspec"], "REFI")),
+      tREFISB (tCK * parseUint(memspec["memtimingspec"], "REFISB"))
 {
     commandLengthInCycles[Command::ACT] = 2;
 
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp
index 8a21c901..1e4c63b8 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp
@@ -44,46 +44,46 @@ using json = nlohmann::json;
 
 MemSpecLPDDR4::MemSpecLPDDR4(json &memspec)
     : MemSpec(memspec, MemoryType::LPDDR4,
-      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfChannels"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
       1,
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
-          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
+          * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
       1),
-      tREFI   (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")),
-      tREFIpb (tCK * parseUint(memspec["memtimingspec"]["REFIPB"], "REFIPB")),
-      tRFCab  (tCK * parseUint(memspec["memtimingspec"]["RFCAB"], "RFCAB")),
-      tRFCpb  (tCK * parseUint(memspec["memtimingspec"]["RFCPB"], "RFCPB")),
-      tRPab   (tCK * parseUint(memspec["memtimingspec"]["RPAB"], "RPAB")),
-      tRPpb   (tCK * parseUint(memspec["memtimingspec"]["RPPB"], "RPPB")),
-      tRCab   (tCK * parseUint(memspec["memtimingspec"]["RCAB"], "RCAB")),
-      tRCpb   (tCK * parseUint(memspec["memtimingspec"]["RCPB"], "RCPB")),
-      tPPD    (tCK * parseUint(memspec["memtimingspec"]["PPD"], "PPD")),
-      tRAS    (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
-      tRCD    (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")),
-      tFAW    (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
-      tRRD    (tCK * parseUint(memspec["memtimingspec"]["RRD"], "RRD")),
-      tCCD    (tCK * parseUint(memspec["memtimingspec"]["CCD"], "CCD")),
-      tRL     (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")),
-      tRPST   (tCK * parseUint(memspec["memtimingspec"]["RPST"], "RPST")),
-      tDQSCK  (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),
-      tRTP    (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
-      tWL     (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
-      tDQSS   (tCK * parseUint(memspec["memtimingspec"]["DQSS"], "DQSS")),
-      tDQS2DQ (tCK * parseUint(memspec["memtimingspec"]["DQS2DQ"], "DQS2DQ")),
-      tWR     (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
-      tWPRE   (tCK * parseUint(memspec["memtimingspec"]["WPRE"], "WPRE")),
-      tWTR    (tCK * parseUint(memspec["memtimingspec"]["WTR"], "WTR")),
-      tXP     (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
-      tSR     (tCK * parseUint(memspec["memtimingspec"]["SR"], "SR")),
-      tXSR    (tCK * parseUint(memspec["memtimingspec"]["XSR"], "XSR")),
-      tESCKE  (tCK * parseUint(memspec["memtimingspec"]["ESCKE"], "ESCKE")),
-      tCKE    (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
-      tCMDCKE (tCK * parseUint(memspec["memtimingspec"]["CMDCKE"], "CMDCKE")),
-      tRTRS   (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS"))
+      tREFI   (tCK * parseUint(memspec["memtimingspec"], "REFI")),
+      tREFIpb (tCK * parseUint(memspec["memtimingspec"], "REFIPB")),
+      tRFCab  (tCK * parseUint(memspec["memtimingspec"], "RFCAB")),
+      tRFCpb  (tCK * parseUint(memspec["memtimingspec"], "RFCPB")),
+      tRPab   (tCK * parseUint(memspec["memtimingspec"], "RPAB")),
+      tRPpb   (tCK * parseUint(memspec["memtimingspec"], "RPPB")),
+      tRCab   (tCK * parseUint(memspec["memtimingspec"], "RCAB")),
+      tRCpb   (tCK * parseUint(memspec["memtimingspec"], "RCPB")),
+      tPPD    (tCK * parseUint(memspec["memtimingspec"], "PPD")),
+      tRAS    (tCK * parseUint(memspec["memtimingspec"], "RAS")),
+      tRCD    (tCK * parseUint(memspec["memtimingspec"], "RCD")),
+      tFAW    (tCK * parseUint(memspec["memtimingspec"], "FAW")),
+      tRRD    (tCK * parseUint(memspec["memtimingspec"], "RRD")),
+      tCCD    (tCK * parseUint(memspec["memtimingspec"], "CCD")),
+      tRL     (tCK * parseUint(memspec["memtimingspec"], "RL")),
+      tRPST   (tCK * parseUint(memspec["memtimingspec"], "RPST")),
+      tDQSCK  (tCK * parseUint(memspec["memtimingspec"], "DQSCK")),
+      tRTP    (tCK * parseUint(memspec["memtimingspec"], "RTP")),
+      tWL     (tCK * parseUint(memspec["memtimingspec"], "WL")),
+      tDQSS   (tCK * parseUint(memspec["memtimingspec"], "DQSS")),
+      tDQS2DQ (tCK * parseUint(memspec["memtimingspec"], "DQS2DQ")),
+      tWR     (tCK * parseUint(memspec["memtimingspec"], "WR")),
+      tWPRE   (tCK * parseUint(memspec["memtimingspec"], "WPRE")),
+      tWTR    (tCK * parseUint(memspec["memtimingspec"], "WTR")),
+      tXP     (tCK * parseUint(memspec["memtimingspec"], "XP")),
+      tSR     (tCK * parseUint(memspec["memtimingspec"], "SR")),
+      tXSR    (tCK * parseUint(memspec["memtimingspec"], "XSR")),
+      tESCKE  (tCK * parseUint(memspec["memtimingspec"], "ESCKE")),
+      tCKE    (tCK * parseUint(memspec["memtimingspec"], "CKE")),
+      tCMDCKE (tCK * parseUint(memspec["memtimingspec"], "CMDCKE")),
+      tRTRS   (tCK * parseUint(memspec["memtimingspec"], "RTRS"))
 {
     commandLengthInCycles[Command::ACT] = 4;
     commandLengthInCycles[Command::PRE] = 2;
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp
index d721fe7f..f9b24fe9 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecSTTMRAM.cpp
@@ -44,39 +44,39 @@ using json = nlohmann::json;
 
 MemSpecSTTMRAM::MemSpecSTTMRAM(json &memspec)
     : MemSpec(memspec, MemoryType::STTMRAM,
-      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfChannels"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
       1,
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
-          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfDevicesOnDIMM"],"nbrOfDevicesOnDIMM")),
-      tCKE     (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
+          * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfDevicesOnDIMM")),
+      tCKE     (tCK * parseUint(memspec["memtimingspec"], "CKE")),
       tPD      (tCKE),
-      tCKESR   (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")),
-      tDQSCK   (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),
-      tRAS     (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
-      tRC      (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
-      tRCD     (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")),
-      tRL      (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")),
-      tRTP     (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
-      tWL      (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
-      tWR      (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
-      tXP      (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
-      tXS      (tCK * parseUint(memspec["memtimingspec"]["XS"], "XS")),
-      tCCD     (tCK * parseUint(memspec["memtimingspec"]["CCD"], "CCD")),
-      tFAW     (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
-      tRP      (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
-      tRRD     (tCK * parseUint(memspec["memtimingspec"]["RRD"], "RRD")),
-      tWTR     (tCK * parseUint(memspec["memtimingspec"]["WTR"], "WTR")),
-      tAL      (tCK * parseUint(memspec["memtimingspec"]["AL"], "AL")),
-      tXPDLL   (tCK * parseUint(memspec["memtimingspec"]["XPDLL"], "XPDLL")),
-      tXSDLL   (tCK * parseUint(memspec["memtimingspec"]["XSDLL"], "XSDLL")),
-      tACTPDEN (tCK * parseUint(memspec["memtimingspec"]["ACTPDEN"], "ACTPDEN")),
-      tPRPDEN  (tCK * parseUint(memspec["memtimingspec"]["PRPDEN"], "PRPDEN")),
-      tRTRS    (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS"))
+      tCKESR   (tCK * parseUint(memspec["memtimingspec"], "CKESR")),
+      tDQSCK   (tCK * parseUint(memspec["memtimingspec"], "DQSCK")),
+      tRAS     (tCK * parseUint(memspec["memtimingspec"], "RAS")),
+      tRC      (tCK * parseUint(memspec["memtimingspec"], "RC")),
+      tRCD     (tCK * parseUint(memspec["memtimingspec"], "RCD")),
+      tRL      (tCK * parseUint(memspec["memtimingspec"], "RL")),
+      tRTP     (tCK * parseUint(memspec["memtimingspec"], "RTP")),
+      tWL      (tCK * parseUint(memspec["memtimingspec"], "WL")),
+      tWR      (tCK * parseUint(memspec["memtimingspec"], "WR")),
+      tXP      (tCK * parseUint(memspec["memtimingspec"], "XP")),
+      tXS      (tCK * parseUint(memspec["memtimingspec"], "XS")),
+      tCCD     (tCK * parseUint(memspec["memtimingspec"], "CCD")),
+      tFAW     (tCK * parseUint(memspec["memtimingspec"], "FAW")),
+      tRP      (tCK * parseUint(memspec["memtimingspec"], "RP")),
+      tRRD     (tCK * parseUint(memspec["memtimingspec"], "RRD")),
+      tWTR     (tCK * parseUint(memspec["memtimingspec"], "WTR")),
+      tAL      (tCK * parseUint(memspec["memtimingspec"], "AL")),
+      tXPDLL   (tCK * parseUint(memspec["memtimingspec"], "XPDLL")),
+      tXSDLL   (tCK * parseUint(memspec["memtimingspec"], "XSDLL")),
+      tACTPDEN (tCK * parseUint(memspec["memtimingspec"], "ACTPDEN")),
+      tPRPDEN  (tCK * parseUint(memspec["memtimingspec"], "PRPDEN")),
+      tRTRS    (tCK * parseUint(memspec["memtimingspec"], "RTRS"))
 {
     uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
     uint64_t deviceSizeBytes = deviceSizeBits / 8;
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp
index 7a7694d1..ede42e5c 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp
@@ -44,60 +44,60 @@ using json = nlohmann::json;
 
 MemSpecWideIO::MemSpecWideIO(json &memspec)
     : MemSpec(memspec, MemoryType::WideIO,
-      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfChannels"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
       1,
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
-          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
+          * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
       1),
-      tCKE    (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
-      tCKESR  (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")),
-      tDQSCK  (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),
-      tAC     (tCK * parseUint(memspec["memtimingspec"]["AC"], "AC")),
-      tRAS    (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
-      tRC     (tCK * parseUint(memspec["memtimingspec"]["RC"], "RC")),
-      tRCD    (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")),
-      tRL     (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")),
-      tWL     (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
-      tWR     (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
-      tXP     (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
-      tXSR    (tCK * parseUint(memspec["memtimingspec"]["XSR"], "XSR")),
-      tCCD_R  (tCK * parseUint(memspec["memtimingspec"]["CCD_R"], "CCD_R")),
-      tCCD_W  (tCK * parseUint(memspec["memtimingspec"]["CCD_W"], "CCD_W")),
-      tREFI   (tCK * parseUint(memspec["memtimingspec"]["REFI"], "REFI")),
-      tRFC    (tCK * parseUint(memspec["memtimingspec"]["RFC"], "RFC")),
-      tRP     (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")),
-      tRRD    (tCK * parseUint(memspec["memtimingspec"]["RRD"], "RRD")),
-      tTAW    (tCK * parseUint(memspec["memtimingspec"]["TAW"], "TAW")),
-      tWTR    (tCK * parseUint(memspec["memtimingspec"]["WTR"], "WTR")),
-      tRTRS   (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS")),
-      iDD0    (parseUdouble(memspec["mempowerspec"]["idd0"], "idd0")),
-      iDD2N   (parseUdouble(memspec["mempowerspec"]["idd2n"], "idd2n")),
-      iDD3N   (parseUdouble(memspec["mempowerspec"]["idd3n"], "idd3n")),
-      iDD4R   (parseUdouble(memspec["mempowerspec"]["idd4r"], "idd4r")),
-      iDD4W   (parseUdouble(memspec["mempowerspec"]["idd4w"], "idd4w")),
-      iDD5    (parseUdouble(memspec["mempowerspec"]["idd5"], "idd5")),
-      iDD6    (parseUdouble(memspec["mempowerspec"]["idd6"], "idd6")),
-      vDD     (parseUdouble(memspec["mempowerspec"]["vdd"], "vdd")),
-      iDD02   (parseUdouble(memspec["mempowerspec"]["idd02"], "idd02")),
-      iDD2P0  (parseUdouble(memspec["mempowerspec"]["idd2p0"], "idd2p0")),
-      iDD2P02 (parseUdouble(memspec["mempowerspec"]["idd2p02"], "idd2p02")),
-      iDD2P1  (parseUdouble(memspec["mempowerspec"]["idd2p1"], "idd2p1")),
-      iDD2P12 (parseUdouble(memspec["mempowerspec"]["idd2p12"], "idd2p12")),
-      iDD2N2  (parseUdouble(memspec["mempowerspec"]["idd2n2"], "idd2n2")),
-      iDD3P0  (parseUdouble(memspec["mempowerspec"]["idd3p0"], "idd3p0")),
-      iDD3P02 (parseUdouble(memspec["mempowerspec"]["idd3p02"], "idd3p02")),
-      iDD3P1  (parseUdouble(memspec["mempowerspec"]["idd3p1"], "idd3p1")),
-      iDD3P12 (parseUdouble(memspec["mempowerspec"]["idd3p12"], "idd3p12")),
-      iDD3N2  (parseUdouble(memspec["mempowerspec"]["idd3n2"], "idd3n2")),
-      iDD4R2  (parseUdouble(memspec["mempowerspec"]["idd4r2"], "idd4r2")),
-      iDD4W2  (parseUdouble(memspec["mempowerspec"]["idd4w2"], "idd4w2")),
-      iDD52   (parseUdouble(memspec["mempowerspec"]["idd52"], "idd52")),
-      iDD62   (parseUdouble(memspec["mempowerspec"]["idd62"], "idd62")),
-      vDD2    (parseUdouble(memspec["mempowerspec"]["vdd2"], "vdd2"))
+      tCKE    (tCK * parseUint(memspec["memtimingspec"], "CKE")),
+      tCKESR  (tCK * parseUint(memspec["memtimingspec"], "CKESR")),
+      tDQSCK  (tCK * parseUint(memspec["memtimingspec"], "DQSCK")),
+      tAC     (tCK * parseUint(memspec["memtimingspec"], "AC")),
+      tRAS    (tCK * parseUint(memspec["memtimingspec"], "RAS")),
+      tRC     (tCK * parseUint(memspec["memtimingspec"], "RC")),
+      tRCD    (tCK * parseUint(memspec["memtimingspec"], "RCD")),
+      tRL     (tCK * parseUint(memspec["memtimingspec"], "RL")),
+      tWL     (tCK * parseUint(memspec["memtimingspec"], "WL")),
+      tWR     (tCK * parseUint(memspec["memtimingspec"], "WR")),
+      tXP     (tCK * parseUint(memspec["memtimingspec"], "XP")),
+      tXSR    (tCK * parseUint(memspec["memtimingspec"], "XSR")),
+      tCCD_R  (tCK * parseUint(memspec["memtimingspec"], "CCD_R")),
+      tCCD_W  (tCK * parseUint(memspec["memtimingspec"], "CCD_W")),
+      tREFI   (tCK * parseUint(memspec["memtimingspec"], "REFI")),
+      tRFC    (tCK * parseUint(memspec["memtimingspec"], "RFC")),
+      tRP     (tCK * parseUint(memspec["memtimingspec"], "RP")),
+      tRRD    (tCK * parseUint(memspec["memtimingspec"], "RRD")),
+      tTAW    (tCK * parseUint(memspec["memtimingspec"], "TAW")),
+      tWTR    (tCK * parseUint(memspec["memtimingspec"], "WTR")),
+      tRTRS   (tCK * parseUint(memspec["memtimingspec"], "RTRS")),
+      iDD0    (parseUdouble(memspec["mempowerspec"], "idd0")),
+      iDD2N   (parseUdouble(memspec["mempowerspec"], "idd2n")),
+      iDD3N   (parseUdouble(memspec["mempowerspec"], "idd3n")),
+      iDD4R   (parseUdouble(memspec["mempowerspec"], "idd4r")),
+      iDD4W   (parseUdouble(memspec["mempowerspec"], "idd4w")),
+      iDD5    (parseUdouble(memspec["mempowerspec"], "idd5")),
+      iDD6    (parseUdouble(memspec["mempowerspec"], "idd6")),
+      vDD     (parseUdouble(memspec["mempowerspec"], "vdd")),
+      iDD02   (parseUdouble(memspec["mempowerspec"], "idd02")),
+      iDD2P0  (parseUdouble(memspec["mempowerspec"], "idd2p0")),
+      iDD2P02 (parseUdouble(memspec["mempowerspec"], "idd2p02")),
+      iDD2P1  (parseUdouble(memspec["mempowerspec"], "idd2p1")),
+      iDD2P12 (parseUdouble(memspec["mempowerspec"], "idd2p12")),
+      iDD2N2  (parseUdouble(memspec["mempowerspec"], "idd2n2")),
+      iDD3P0  (parseUdouble(memspec["mempowerspec"], "idd3p0")),
+      iDD3P02 (parseUdouble(memspec["mempowerspec"], "idd3p02")),
+      iDD3P1  (parseUdouble(memspec["mempowerspec"], "idd3p1")),
+      iDD3P12 (parseUdouble(memspec["mempowerspec"], "idd3p12")),
+      iDD3N2  (parseUdouble(memspec["mempowerspec"], "idd3n2")),
+      iDD4R2  (parseUdouble(memspec["mempowerspec"], "idd4r2")),
+      iDD4W2  (parseUdouble(memspec["mempowerspec"], "idd4w2")),
+      iDD52   (parseUdouble(memspec["mempowerspec"], "idd52")),
+      iDD62   (parseUdouble(memspec["mempowerspec"], "idd62")),
+      vDD2    (parseUdouble(memspec["mempowerspec"], "vdd2"))
 {
     uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
     uint64_t deviceSizeBytes = deviceSizeBits / 8;
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp
index 93ba82b5..c7fab8bf 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp
@@ -44,42 +44,42 @@ using json = nlohmann::json;
 
 MemSpecWideIO2::MemSpecWideIO2(json &memspec)
     : MemSpec(memspec, MemoryType::WideIO2,
-      parseUint(memspec["memarchitecturespec"]["nbrOfChannels"],"nbrOfChannels"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfChannels"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
       1,
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfBanks"],"nbrOfBanks")
-          * parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
-      parseUint(memspec["memarchitecturespec"]["nbrOfRanks"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
+          * parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
+      parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
       1),
-      tDQSCK  (tCK * parseUint(memspec["memtimingspec"]["DQSCK"], "DQSCK")),
-      tDQSS   (tCK * parseUint(memspec["memtimingspec"]["DQSS"], "DQSS")),
-      tCKE    (tCK * parseUint(memspec["memtimingspec"]["CKE"], "CKE")),
-      tRL     (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")),
-      tWL     (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")),
-      tRCpb   (tCK * parseUint(memspec["memtimingspec"]["RCPB"], "RCPB")),
-      tRCab   (tCK * parseUint(memspec["memtimingspec"]["RCAB"], "RCAB")),
-      tCKESR  (tCK * parseUint(memspec["memtimingspec"]["CKESR"], "CKESR")),
-      tXSR    (tCK * parseUint(memspec["memtimingspec"]["XSR"], "XSR")),
-      tXP     (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")),
-      tCCD    (tCK * parseUint(memspec["memtimingspec"]["CCD"], "CCD")),
-      tRTP    (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")),
-      tRCD    (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")),
-      tRPpb   (tCK * parseUint(memspec["memtimingspec"]["RPPB"], "RPPB")),
-      tRPab   (tCK * parseUint(memspec["memtimingspec"]["RPAB"], "RPAB")),
-      tRAS    (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")),
-      tWR     (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")),
-      tWTR    (tCK * parseUint(memspec["memtimingspec"]["WTR"], "WTR")),
-      tRRD    (tCK * parseUint(memspec["memtimingspec"]["RRD"], "RRD")),
-      tFAW    (tCK * parseUint(memspec["memtimingspec"]["FAW"], "FAW")),
-      tREFI   (tCK * static_cast<unsigned>(parseUint(memspec["memtimingspec"]["REFI"], "REFI")
-              * parseUdouble(memspec["memtimingspec"]["REFM"], "REFM"))),
-      tREFIpb (tCK * static_cast<unsigned>(parseUint(memspec["memtimingspec"]["REFIPB"], "REFIPB")
-              * parseUdouble(memspec["memtimingspec"]["REFM"], "REFM"))),
-      tRFCab  (tCK * parseUint(memspec["memtimingspec"]["RFCAB"], "RFCAB")),
-      tRFCpb  (tCK * parseUint(memspec["memtimingspec"]["RFCPB"], "RFCPB")),
-      tRTRS   (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS"))
+      tDQSCK  (tCK * parseUint(memspec["memtimingspec"], "DQSCK")),
+      tDQSS   (tCK * parseUint(memspec["memtimingspec"], "DQSS")),
+      tCKE    (tCK * parseUint(memspec["memtimingspec"], "CKE")),
+      tRL     (tCK * parseUint(memspec["memtimingspec"], "RL")),
+      tWL     (tCK * parseUint(memspec["memtimingspec"], "WL")),
+      tRCpb   (tCK * parseUint(memspec["memtimingspec"], "RCPB")),
+      tRCab   (tCK * parseUint(memspec["memtimingspec"], "RCAB")),
+      tCKESR  (tCK * parseUint(memspec["memtimingspec"], "CKESR")),
+      tXSR    (tCK * parseUint(memspec["memtimingspec"], "XSR")),
+      tXP     (tCK * parseUint(memspec["memtimingspec"], "XP")),
+      tCCD    (tCK * parseUint(memspec["memtimingspec"], "CCD")),
+      tRTP    (tCK * parseUint(memspec["memtimingspec"], "RTP")),
+      tRCD    (tCK * parseUint(memspec["memtimingspec"], "RCD")),
+      tRPpb   (tCK * parseUint(memspec["memtimingspec"], "RPPB")),
+      tRPab   (tCK * parseUint(memspec["memtimingspec"], "RPAB")),
+      tRAS    (tCK * parseUint(memspec["memtimingspec"], "RAS")),
+      tWR     (tCK * parseUint(memspec["memtimingspec"], "WR")),
+      tWTR    (tCK * parseUint(memspec["memtimingspec"], "WTR")),
+      tRRD    (tCK * parseUint(memspec["memtimingspec"], "RRD")),
+      tFAW    (tCK * parseUint(memspec["memtimingspec"], "FAW")),
+      tREFI   (tCK * static_cast<unsigned>(parseUint(memspec["memtimingspec"], "REFI")
+              * parseUdouble(memspec["memtimingspec"], "REFM"))),
+      tREFIpb (tCK * static_cast<unsigned>(parseUint(memspec["memtimingspec"], "REFIPB")
+              * parseUdouble(memspec["memtimingspec"], "REFM"))),
+      tRFCab  (tCK * parseUint(memspec["memtimingspec"], "RFCAB")),
+      tRFCpb  (tCK * parseUint(memspec["memtimingspec"], "RFCPB")),
+      tRTRS   (tCK * parseUint(memspec["memtimingspec"], "RTRS"))
 {
     uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
     uint64_t deviceSizeBytes = deviceSizeBits / 8;