diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3200A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3200A.json index 8bc5a428..75172a46 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3200A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3200A.json @@ -34,7 +34,8 @@ "WPST": 0, "WR": 48, "CCD_L_slr": 8, - "CCD_L_WR_slr": 16, + "CCD_L_WR_slr": 32, + "CCD_L_WR2_slr": 16, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 1600 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3600A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3600A.json index 639c16a9..e35d934f 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3600A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-3600A.json @@ -34,7 +34,8 @@ "WPST": 0, "WR": 54, "CCD_L_slr": 9, - "CCD_L_WR_slr": 18, + "CCD_L_WR_slr": 36, + "CCD_L_WR2_slr": 18, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 1800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4000A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4000A.json index 98d6a123..484ba99f 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4000A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4000A.json @@ -34,7 +34,8 @@ "WPST": 0, "WR": 60, "CCD_L_slr": 10, - "CCD_L_WR_slr": 20, + "CCD_L_WR_slr": 40, + "CCD_L_WR2_slr": 20, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 2000 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4400A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4400A.json index e27d625d..43b961e5 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4400A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4400A.json @@ -34,7 +34,8 @@ "WPST": 0, "WR": 66, "CCD_L_slr": 11, - "CCD_L_WR_slr": 22, + "CCD_L_WR_slr": 44, + "CCD_L_WR2_slr": 22, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 2200 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4800A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4800A.json index 5fef3321..eb4a3b8c 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4800A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-4800A.json @@ -34,7 +34,8 @@ "WPST": 0, "WR": 72, "CCD_L_slr": 12, - "CCD_L_WR_slr": 24, + "CCD_L_WR_slr": 48, + "CCD_L_WR2_slr": 24, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 2400 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5200A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5200A.json index 358643b8..030f4e43 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5200A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5200A.json @@ -34,7 +34,8 @@ "WPST": 0, "WR": 78, "CCD_L_slr": 13, - "CCD_L_WR_slr": 26, + "CCD_L_WR_slr": 52, + "CCD_L_WR2_slr": 26, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 2600 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5600A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5600A.json index 766c837c..8de5c0f9 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5600A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-5600A.json @@ -34,7 +34,8 @@ "WPST": 0, "WR": 84, "CCD_L_slr": 14, - "CCD_L_WR_slr": 28, + "CCD_L_WR_slr": 56, + "CCD_L_WR2_slr": 28, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 2800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6000A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6000A.json index 9e387dc4..0bf780ec 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6000A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6000A.json @@ -34,7 +34,8 @@ "WPST": 0, "WR": 90, "CCD_L_slr": 15, - "CCD_L_WR_slr": 30, + "CCD_L_WR_slr": 60, + "CCD_L_WR2_slr": 30, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 3000 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6400A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6400A.json index 18caa618..70d03828 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6400A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x4x1Gbx8_DDR5-6400A.json @@ -34,7 +34,8 @@ "WPST": 0, "WR": 96, "CCD_L_slr": 16, - "CCD_L_WR_slr": 32, + "CCD_L_WR_slr": 64, + "CCD_L_WR2_slr": 32, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 3200 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-3200A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-3200A.json index aa6e82b0..635cc6cf 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-3200A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-3200A.json @@ -35,6 +35,7 @@ "WR": 48, "CCD_L_slr": 8, "CCD_L_WR_slr": 32, + "CCD_L_WR2_slr": 16, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 1600 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-3600A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-3600A.json index 96359874..ac39be46 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-3600A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-3600A.json @@ -35,6 +35,7 @@ "WR": 54, "CCD_L_slr": 9, "CCD_L_WR_slr": 36, + "CCD_L_WR2_slr": 18, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 1800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4000A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4000A.json index bf632566..9887512d 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4000A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4000A.json @@ -35,6 +35,7 @@ "WR": 60, "CCD_L_slr": 10, "CCD_L_WR_slr": 40, + "CCD_L_WR2_slr": 20, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 2000 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4400A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4400A.json index a343598b..cd9bdced 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4400A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4400A.json @@ -35,6 +35,7 @@ "WR": 66, "CCD_L_slr": 11, "CCD_L_WR_slr": 44, + "CCD_L_WR2_slr": 22, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 2200 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4800A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4800A.json index 46998d40..6215400d 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4800A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-4800A.json @@ -35,6 +35,7 @@ "WR": 72, "CCD_L_slr": 12, "CCD_L_WR_slr": 48, + "CCD_L_WR2_slr": 24, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 2400 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-5200A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-5200A.json index 18e6c093..48d99a38 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-5200A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-5200A.json @@ -35,6 +35,7 @@ "WR": 78, "CCD_L_slr": 13, "CCD_L_WR_slr": 52, + "CCD_L_WR2_slr": 26, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 2600 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-5600A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-5600A.json index 4891bb1b..0a46d8ed 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-5600A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-5600A.json @@ -35,6 +35,7 @@ "WR": 84, "CCD_L_slr": 14, "CCD_L_WR_slr": 56, + "CCD_L_WR2_slr": 28, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 2800 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-6000A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-6000A.json index 3e26408e..ba5c81eb 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-6000A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-6000A.json @@ -35,6 +35,7 @@ "WR": 90, "CCD_L_slr": 15, "CCD_L_WR_slr": 60, + "CCD_L_WR2_slr": 30, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 3000 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-6400A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-6400A.json index ca9eac9b..ea3ec632 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-6400A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x2Gbx4_DDR5-6400A.json @@ -35,6 +35,7 @@ "WR": 96, "CCD_L_slr": 16, "CCD_L_WR_slr": 64, + "CCD_L_WR2_slr": 32, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 0, @@ -70,4 +71,4 @@ "clkMhz": 3200 } } -} \ No newline at end of file +} diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json index 315fb976..fbbe90fe 100644 --- a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json +++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x8x2Gbx4_DDR5-3200A.json @@ -35,6 +35,7 @@ "WR": 48, "CCD_L_slr": 8, "CCD_L_WR_slr": 32, + "CCD_L_WR2_slr": 16, "CCD_S_slr": 8, "CCD_S_WR_slr": 8, "CCD_dlr": 8, diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index 17b20a34..ca347381 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -162,7 +162,7 @@ void TlmRecorder::introduceTransactionSystem(tlm_generic_payload &trans) currentTransactionsInSystem[&trans].cmd = trans.get_command() == tlm::TLM_READ_COMMAND ? "R" : "W"; currentTransactionsInSystem[&trans].address = trans.get_address(); - currentTransactionsInSystem[&trans].burstlength = trans.get_streaming_width(); + currentTransactionsInSystem[&trans].burstLength = DramExtension::getBurstLength(trans); currentTransactionsInSystem[&trans].dramExtension = DramExtension::getExtension(trans); currentTransactionsInSystem[&trans].timeOfGeneration = GenerationExtension::getTimeOfGeneration(trans); @@ -406,7 +406,7 @@ void TlmRecorder::insertTransactionInDB(Transaction &recordingData) sqlite3_bind_int(insertTransactionStatement, 1, static_cast(recordingData.id)); sqlite3_bind_int(insertTransactionStatement, 2, static_cast(recordingData.id)); sqlite3_bind_int64(insertTransactionStatement, 3, static_cast(recordingData.address)); - sqlite3_bind_int(insertTransactionStatement, 4, static_cast(recordingData.burstlength)); + sqlite3_bind_int(insertTransactionStatement, 4, static_cast(recordingData.burstLength)); sqlite3_bind_int(insertTransactionStatement, 5, static_cast(recordingData.dramExtension.getThread().ID())); sqlite3_bind_int(insertTransactionStatement, 6, diff --git a/DRAMSys/library/src/common/TlmRecorder.h b/DRAMSys/library/src/common/TlmRecorder.h index d3974f1b..fd422987 100644 --- a/DRAMSys/library/src/common/TlmRecorder.h +++ b/DRAMSys/library/src/common/TlmRecorder.h @@ -92,7 +92,7 @@ private: uint64_t id; uint64_t address; - unsigned int burstlength; + unsigned int burstLength; std::string cmd; DramExtension dramExtension; sc_time timeOfGeneration; diff --git a/DRAMSys/library/src/common/dramExtensions.cpp b/DRAMSys/library/src/common/dramExtensions.cpp index 6104bcf4..44910e22 100644 --- a/DRAMSys/library/src/common/dramExtensions.cpp +++ b/DRAMSys/library/src/common/dramExtensions.cpp @@ -44,21 +44,21 @@ using namespace tlm; DramExtension::DramExtension() : thread(0), channel(0), rank(0), bankgroup(0), bank(0), - row(0), column(0), burstlength(0), + row(0), column(0), burstLength(0), threadPayloadID(0), channelPayloadID(0) {} DramExtension::DramExtension(Thread thread, Channel channel, Rank rank, BankGroup bankgroup, Bank bank, Row row, - Column column, unsigned int burstlength, + Column column, unsigned int burstLength, uint64_t threadPayloadID, uint64_t channelPayloadID) : thread(thread), channel(channel), rank(rank), bankgroup(bankgroup), bank(bank), - row(row), column(column), burstlength(burstlength), + row(row), column(column), burstLength(burstLength), threadPayloadID(threadPayloadID), channelPayloadID(channelPayloadID) {} void DramExtension::setExtension(tlm::tlm_generic_payload *payload, Thread thread, Channel channel, Rank rank, BankGroup bankgroup, Bank bank, Row row, - Column column, unsigned int burstlength, + Column column, unsigned int burstLength, uint64_t threadPayloadID, uint64_t channelPayloadID) { DramExtension *extension = nullptr; @@ -73,14 +73,14 @@ void DramExtension::setExtension(tlm::tlm_generic_payload *payload, extension->bank = bank; extension->row = row; extension->column = column; - extension->burstlength = burstlength; + extension->burstLength = burstLength; extension->threadPayloadID = threadPayloadID; extension->channelPayloadID = channelPayloadID; } else { extension = new DramExtension(thread, channel, rank, bankgroup, - bank, row, column, burstlength, + bank, row, column, burstLength, threadPayloadID, channelPayloadID); payload->set_auto_extension(extension); } @@ -89,11 +89,11 @@ void DramExtension::setExtension(tlm::tlm_generic_payload *payload, void DramExtension::setExtension(tlm::tlm_generic_payload &payload, Thread thread, Channel channel, Rank rank, BankGroup bankgroup, Bank bank, Row row, - Column column, unsigned int burstlength, + Column column, unsigned int burstLength, uint64_t threadPayloadID, uint64_t channelPayloadID) { setExtension(&payload, thread, channel, rank, bankgroup, - bank, row, column, burstlength, + bank, row, column, burstLength, threadPayloadID, channelPayloadID); } @@ -227,7 +227,7 @@ uint64_t DramExtension::getChannelPayloadID(const tlm_generic_payload &payload) tlm_extension_base *DramExtension::clone() const { return new DramExtension(thread, channel, rank, bankgroup, bank, row, column, - burstlength, threadPayloadID, channelPayloadID); + burstLength, threadPayloadID, channelPayloadID); } void DramExtension::copy_from(const tlm_extension_base &ext) @@ -240,7 +240,7 @@ void DramExtension::copy_from(const tlm_extension_base &ext) bank = cpyFrom.bank; row = cpyFrom.row; column = cpyFrom.column; - burstlength = cpyFrom.burstlength; + burstLength = cpyFrom.burstLength; } Thread DramExtension::getThread() const @@ -280,7 +280,7 @@ Column DramExtension::getColumn() const unsigned int DramExtension::getBurstLength() const { - return burstlength; + return burstLength; } uint64_t DramExtension::getThreadPayloadID() const diff --git a/DRAMSys/library/src/common/dramExtensions.h b/DRAMSys/library/src/common/dramExtensions.h index 896a95a8..462a61a8 100644 --- a/DRAMSys/library/src/common/dramExtensions.h +++ b/DRAMSys/library/src/common/dramExtensions.h @@ -165,7 +165,7 @@ public: DramExtension(); DramExtension(Thread thread, Channel channel, Rank rank, BankGroup bankgroup, Bank bank, Row row, - Column column, unsigned int burstlength, + Column column, unsigned int burstLength, uint64_t threadPayloadID, uint64_t channelPayloadID); virtual tlm::tlm_extension_base *clone() const; @@ -174,12 +174,12 @@ public: static void setExtension(tlm::tlm_generic_payload *payload, Thread thread, Channel channel, Rank rank, BankGroup bankgroup, Bank bank, Row row, - Column column, unsigned int burstlength, + Column column, unsigned int burstLength, uint64_t threadPayloadID, uint64_t channelPayloadID); static void setExtension(tlm::tlm_generic_payload &payload, Thread thread, Channel channel, Rank rank, BankGroup bankgroup, Bank bank, Row row, - Column column, unsigned int burstlength, + Column column, unsigned int burstLength, uint64_t threadPayloadID, uint64_t channelPayloadID); static DramExtension &getExtension(const tlm::tlm_generic_payload *payload); @@ -233,7 +233,7 @@ private: Bank bank; Row row; Column column; - unsigned int burstlength; + unsigned int burstLength; uint64_t threadPayloadID; uint64_t channelPayloadID; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index 4020a8ed..82c1987d 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -79,8 +79,8 @@ public: virtual bool hasRasAndCasBus() const; - virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const = 0; - virtual TimeInterval getIntervalOnDataStrobe(Command) const = 0; + virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const = 0; + virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const = 0; sc_time getCommandLength(Command) const; virtual uint64_t getSimMemSizeInBytes() const = 0; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp index 2da79c88..5c566b46 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.cpp @@ -120,7 +120,7 @@ sc_time MemSpecDDR3::getExecutionTime(Command command, const tlm_generic_payload } } -TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command) const +TimeInterval MemSpecDDR3::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return TimeInterval(tRL, tRL + burstDuration); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h index 6c9174de..370273b0 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR3.h @@ -89,8 +89,8 @@ public: virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command) const override; + virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; virtual uint64_t getSimMemSizeInBytes() const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp index cd6daac4..2b6e3bfb 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.cpp @@ -139,7 +139,7 @@ sc_time MemSpecDDR4::getExecutionTime(Command command, const tlm_generic_payload } } -TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command) const +TimeInterval MemSpecDDR4::getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return TimeInterval(tRL, tRL + burstDuration); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h index c63fb36f..e3a5ed9b 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR4.h @@ -97,8 +97,8 @@ public: virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command) const override; + virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; virtual uint64_t getSimMemSizeInBytes() const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp index 5d0353c8..fdd3f094 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.cpp @@ -59,56 +59,59 @@ MemSpecDDR5::MemSpecDDR5(json &memspec) numberOfLogicalRanks(logicalRanksPerPhysicalRank * numberOfPhysicalRanks), cmdMode(parseUint(memspec["memarchitecturespec"]["cmdMode"], "cmdMode")), refMode(parseUint(memspec["memarchitecturespec"]["refMode"], "refMode")), - tRCD (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")), - tPPD (tCK * parseUint(memspec["memtimingspec"]["PPD"], "PPD")), - tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")), - tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")), - tRC (tRAS + tRP), - tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")), - tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")), - tRPRE (tCK * parseUint(memspec["memtimingspec"]["RPRE"], "RPRE")), - tRPST (tCK * parseUint(memspec["memtimingspec"]["RPST"], "RPST")), - tRDDQS (tCK * parseUint(memspec["memtimingspec"]["RDDQS"], "RDDQS")), - tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")), - tWPRE (tCK * parseUint(memspec["memtimingspec"]["WPRE"], "WPRE")), - tWPST (tCK * parseUint(memspec["memtimingspec"]["WPST"], "WPST")), - tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")), - tCCD_L_slr (tCK * parseUint(memspec["memtimingspec"]["CCD_L_slr"], "CCD_L_slr")), - tCCD_L_WR_slr (tCK * parseUint(memspec["memtimingspec"]["CCD_L_WR_slr"], "CCD_L_WR_slr")), - tCCD_S_slr (tCK * parseUint(memspec["memtimingspec"]["CCD_S_slr"], "CCD_S_slr")), - tCCD_S_WR_slr (tCK * parseUint(memspec["memtimingspec"]["CCD_S_WR_slr"], "CCD_S_WR_slr")), - tCCD_dlr (tCK * parseUint(memspec["memtimingspec"]["CCD_dlr"], "CCD_dlr")), - tCCD_WR_dlr (tCK * parseUint(memspec["memtimingspec"]["CCD_WR_dlr"], "CCD_WR_dlr")), - tCCD_WR_dpr (tCK * parseUint(memspec["memtimingspec"]["CCD_WR_dpr"], "CCD_WR_dpr")), - tRRD_L_slr (tCK * parseUint(memspec["memtimingspec"]["RRD_L_slr"], "RRD_L_slr")), - tRRD_S_slr (tCK * parseUint(memspec["memtimingspec"]["RRD_S_slr"], "RRD_S_slr")), - tRRD_dlr (tCK * parseUint(memspec["memtimingspec"]["RRD_dlr"], "RRD_dlr")), - tFAW_slr (tCK * parseUint(memspec["memtimingspec"]["FAW_slr"], "FAW_slr")), - tFAW_dlr (tCK * parseUint(memspec["memtimingspec"]["FAW_dlr"], "FAW_dlr")), - tWTR_L (tCK * parseUint(memspec["memtimingspec"]["WTR_L"], "WTR_L")), - tWTR_S (tCK * parseUint(memspec["memtimingspec"]["WTR_S"], "WTR_S")), - tRFC_slr ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"]["RFC1_slr"], "RFC1_slr") - : tCK * parseUint(memspec["memtimingspec"]["RFC2_slr"], "RFC2_slr")), - tRFC_dlr ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"]["RFC1_dlr"], "RFC1_dlr") - : tCK * parseUint(memspec["memtimingspec"]["RFC2_dlr"], "RFC2_dlr")), - tRFC_dpr ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"]["RFC1_dpr"], "RFC1_dpr") - : tCK * parseUint(memspec["memtimingspec"]["RFC2_dpr"], "RFC2_dpr")), - tRFCsb_slr (tCK * parseUint(memspec["memtimingspec"]["RFCsb_slr"], "RFCsb_slr")), - tRFCsb_dlr (tCK * parseUint(memspec["memtimingspec"]["RFCsb_dlr"], "RFCsb_dlr")), - tREFI ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"]["REFI1"], "REFI1") - : tCK * parseUint(memspec["memtimingspec"]["REFI2"], "REFI2")), - tREFIsb (tCK * parseUint(memspec["memtimingspec"]["REFISB"], "REFISB")), - tREFSBRD_slr (tCK * parseUint(memspec["memtimingspec"]["REFSBRD_slr"], "REFSBRD_slr")), - tREFSBRD_dlr (tCK * parseUint(memspec["memtimingspec"]["REFSBRD_dlr"], "REFSBRD_dlr")), - tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS")), - tCPDED (tCK * parseUint(memspec["memtimingspec"]["CPDED"], "CPDED")), - tPD (tCK * parseUint(memspec["memtimingspec"]["PD"], "PD")), - tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")), - tACTPDEN (tCK * parseUint(memspec["memtimingspec"]["ACTPDEN"], "ACTPDEN")), - tPRPDEN (tCK * parseUint(memspec["memtimingspec"]["PRPDEN"], "PRPDEN")), - tREFPDEN (tCK * parseUint(memspec["memtimingspec"]["REFPDEN"], "REFPDEN")), - cmdOffset_S (cmdMode == 2 ? 1 * tCK : 0 * tCK), - cmdOffset_L (cmdMode == 2 ? 3 * tCK : 1 * tCK) + tRCD (tCK * parseUint(memspec["memtimingspec"]["RCD"], "RCD")), + tPPD (tCK * parseUint(memspec["memtimingspec"]["PPD"], "PPD")), + tRP (tCK * parseUint(memspec["memtimingspec"]["RP"], "RP")), + tRAS (tCK * parseUint(memspec["memtimingspec"]["RAS"], "RAS")), + tRC (tRAS + tRP), + tRL (tCK * parseUint(memspec["memtimingspec"]["RL"], "RL")), + tRTP (tCK * parseUint(memspec["memtimingspec"]["RTP"], "RTP")), + tRPRE (tCK * parseUint(memspec["memtimingspec"]["RPRE"], "RPRE")), + tRPST (tCK * parseUint(memspec["memtimingspec"]["RPST"], "RPST")), + tRDDQS (tCK * parseUint(memspec["memtimingspec"]["RDDQS"], "RDDQS")), + tWL (tCK * parseUint(memspec["memtimingspec"]["WL"], "WL")), + tWPRE (tCK * parseUint(memspec["memtimingspec"]["WPRE"], "WPRE")), + tWPST (tCK * parseUint(memspec["memtimingspec"]["WPST"], "WPST")), + tWR (tCK * parseUint(memspec["memtimingspec"]["WR"], "WR")), + tCCD_L_slr (tCK * parseUint(memspec["memtimingspec"]["CCD_L_slr"], "CCD_L_slr")), + tCCD_L_WR_slr (tCK * parseUint(memspec["memtimingspec"]["CCD_L_WR_slr"], "CCD_L_WR_slr")), + tCCD_L_WR2_slr (tCK * parseUint(memspec["memtimingspec"]["CCD_L_WR2_slr"], "CCD_L_WR2_slr")), + tCCD_S_slr (tCK * parseUint(memspec["memtimingspec"]["CCD_S_slr"], "CCD_S_slr")), + tCCD_S_WR_slr (tCK * parseUint(memspec["memtimingspec"]["CCD_S_WR_slr"], "CCD_S_WR_slr")), + tCCD_dlr (tCK * parseUint(memspec["memtimingspec"]["CCD_dlr"], "CCD_dlr")), + tCCD_WR_dlr (tCK * parseUint(memspec["memtimingspec"]["CCD_WR_dlr"], "CCD_WR_dlr")), + tCCD_WR_dpr (tCK * parseUint(memspec["memtimingspec"]["CCD_WR_dpr"], "CCD_WR_dpr")), + tRRD_L_slr (tCK * parseUint(memspec["memtimingspec"]["RRD_L_slr"], "RRD_L_slr")), + tRRD_S_slr (tCK * parseUint(memspec["memtimingspec"]["RRD_S_slr"], "RRD_S_slr")), + tRRD_dlr (tCK * parseUint(memspec["memtimingspec"]["RRD_dlr"], "RRD_dlr")), + tFAW_slr (tCK * parseUint(memspec["memtimingspec"]["FAW_slr"], "FAW_slr")), + tFAW_dlr (tCK * parseUint(memspec["memtimingspec"]["FAW_dlr"], "FAW_dlr")), + tWTR_L (tCK * parseUint(memspec["memtimingspec"]["WTR_L"], "WTR_L")), + tWTR_S (tCK * parseUint(memspec["memtimingspec"]["WTR_S"], "WTR_S")), + tRFC_slr ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"]["RFC1_slr"], "RFC1_slr") + : tCK * parseUint(memspec["memtimingspec"]["RFC2_slr"], "RFC2_slr")), + tRFC_dlr ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"]["RFC1_dlr"], "RFC1_dlr") + : tCK * parseUint(memspec["memtimingspec"]["RFC2_dlr"], "RFC2_dlr")), + tRFC_dpr ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"]["RFC1_dpr"], "RFC1_dpr") + : tCK * parseUint(memspec["memtimingspec"]["RFC2_dpr"], "RFC2_dpr")), + tRFCsb_slr (tCK * parseUint(memspec["memtimingspec"]["RFCsb_slr"], "RFCsb_slr")), + tRFCsb_dlr (tCK * parseUint(memspec["memtimingspec"]["RFCsb_dlr"], "RFCsb_dlr")), + tREFI ((refMode == 1) ? tCK * parseUint(memspec["memtimingspec"]["REFI1"], "REFI1") + : tCK * parseUint(memspec["memtimingspec"]["REFI2"], "REFI2")), + tREFIsb (tCK * parseUint(memspec["memtimingspec"]["REFISB"], "REFISB")), + tREFSBRD_slr (tCK * parseUint(memspec["memtimingspec"]["REFSBRD_slr"], "REFSBRD_slr")), + tREFSBRD_dlr (tCK * parseUint(memspec["memtimingspec"]["REFSBRD_dlr"], "REFSBRD_dlr")), + tRTRS (tCK * parseUint(memspec["memtimingspec"]["RTRS"], "RTRS")), + tCPDED (tCK * parseUint(memspec["memtimingspec"]["CPDED"], "CPDED")), + tPD (tCK * parseUint(memspec["memtimingspec"]["PD"], "PD")), + tXP (tCK * parseUint(memspec["memtimingspec"]["XP"], "XP")), + tACTPDEN (tCK * parseUint(memspec["memtimingspec"]["ACTPDEN"], "ACTPDEN")), + tPRPDEN (tCK * parseUint(memspec["memtimingspec"]["PRPDEN"], "PRPDEN")), + tREFPDEN (tCK * parseUint(memspec["memtimingspec"]["REFPDEN"], "REFPDEN")), + shortCmdOffset (cmdMode == 2 ? 1 * tCK : 0 * tCK), + longCmdOffset (cmdMode == 2 ? 3 * tCK : 1 * tCK), + shortBurstDuration(tCK * 8), + longBurstDuration(tCK * 16) { if (cmdMode == 1) { @@ -156,24 +159,39 @@ sc_time MemSpecDDR5::getRefreshIntervalSB() const } // Returns the execution time for commands that have a fixed execution time -sc_time MemSpecDDR5::getExecutionTime(Command command, const tlm_generic_payload &) const +sc_time MemSpecDDR5::getExecutionTime(Command command, const tlm_generic_payload &payload) const { if (command == Command::PRE || command == Command::PREA || command == Command::PRESB) - return tRP + cmdOffset_S; + return tRP + shortCmdOffset; else if (command == Command::ACT) - return tRCD + cmdOffset_L; + return tRCD + longCmdOffset; else if (command == Command::RD) - return tRL + burstDuration + cmdOffset_L; + { + if (DramExtension::getBurstLength(payload) == 32) + return tRL + longBurstDuration + longCmdOffset; + else + return tRL + shortBurstDuration + longCmdOffset; + } else if (command == Command::RDA) - return tRTP + tRP + cmdOffset_L; + return tRTP + tRP + longCmdOffset; else if (command == Command::WR) - return tWL + burstDuration + cmdOffset_L; + { + if (DramExtension::getBurstLength(payload) == 32) + return tWL + longBurstDuration + longCmdOffset; + else + return tWL + shortBurstDuration + longCmdOffset; + } else if (command == Command::WRA) - return tWL + burstDuration + tWR + tRP + cmdOffset_L; + { + if (DramExtension::getBurstLength(payload) == 32) + return tWL + longBurstDuration + tWR + tRP + longCmdOffset; + else + return tWL + shortBurstDuration + tWR + tRP + longCmdOffset; + } else if (command == Command::REFA) - return tRFC_slr + cmdOffset_S; + return tRFC_slr + shortCmdOffset; else if (command == Command::REFSB) - return tRFCsb_slr + cmdOffset_S; + return tRFCsb_slr + shortCmdOffset; else { SC_REPORT_FATAL("getExecutionTime", @@ -182,12 +200,22 @@ sc_time MemSpecDDR5::getExecutionTime(Command command, const tlm_generic_payload } } -TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command) const +TimeInterval MemSpecDDR5::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &payload) const { if (command == Command::RD || command == Command::RDA) - return TimeInterval(tRL + cmdOffset_L, tRL + burstDuration + cmdOffset_L); + { + if (DramExtension::getBurstLength(payload) == 32) + return TimeInterval(tRL + longCmdOffset, tRL + longBurstDuration + longCmdOffset); + else + return TimeInterval(tRL + longCmdOffset, tRL + shortBurstDuration+ longCmdOffset); + } else if (command == Command::WR || command == Command::WRA) - return TimeInterval(tWL + cmdOffset_L, tWL + burstDuration + cmdOffset_L); + { + if (DramExtension::getBurstLength(payload) == 32) + return TimeInterval(tWL + longCmdOffset, tWL + longBurstDuration + longCmdOffset); + else + return TimeInterval(tWL + longCmdOffset, tWL + shortBurstDuration + longCmdOffset); + } else { SC_REPORT_FATAL("MemSpec", "Method was called with invalid argument"); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h index 13883326..3de89eb9 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecDDR5.h @@ -69,6 +69,7 @@ public: const sc_time tWR; const sc_time tCCD_L_slr; const sc_time tCCD_L_WR_slr; + const sc_time tCCD_L_WR2_slr; const sc_time tCCD_S_slr; const sc_time tCCD_S_WR_slr; const sc_time tCCD_dlr; @@ -99,8 +100,11 @@ public: const sc_time tPRPDEN; const sc_time tREFPDEN; - const sc_time cmdOffset_S; - const sc_time cmdOffset_L; + const sc_time shortCmdOffset; + const sc_time longCmdOffset; + + const sc_time shortBurstDuration; + const sc_time longBurstDuration; // Currents and Voltages: // TODO: to be completed @@ -108,8 +112,8 @@ public: virtual sc_time getRefreshIntervalAB() const override; virtual sc_time getRefreshIntervalSB() const override; - virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command) const override; + virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; virtual uint64_t getSimMemSizeInBytes() const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp index 2c27dbc3..4ae7bb17 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.cpp @@ -128,7 +128,7 @@ sc_time MemSpecGDDR5::getExecutionTime(Command command, const tlm_generic_payloa } } -TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command) const +TimeInterval MemSpecGDDR5::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return TimeInterval(tCL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h index 3abeb869..cf584c98 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5.h @@ -88,8 +88,8 @@ public: virtual sc_time getRefreshIntervalAB() const override; virtual sc_time getRefreshIntervalPB() const override; - virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command) const override; + virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; virtual uint64_t getSimMemSizeInBytes() const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp index ea1dc46e..1c97fada 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.cpp @@ -128,7 +128,7 @@ sc_time MemSpecGDDR5X::getExecutionTime(Command command, const tlm_generic_paylo } } -TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command) const +TimeInterval MemSpecGDDR5X::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return TimeInterval(tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h index 10fcd5b5..f507232d 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR5X.h @@ -88,8 +88,8 @@ public: virtual sc_time getRefreshIntervalAB() const override; virtual sc_time getRefreshIntervalPB() const override; - virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command) const override; + virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; virtual uint64_t getSimMemSizeInBytes() const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp index d296f887..c0dfd854 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.cpp @@ -130,7 +130,7 @@ sc_time MemSpecGDDR6::getExecutionTime(Command command, const tlm_generic_payloa } } -TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command) const +TimeInterval MemSpecGDDR6::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return TimeInterval(tRL + tWCK2CKPIN + tWCK2CK + tWCK2DQO, diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h index c0f9f7d1..b6d86f8e 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecGDDR6.h @@ -90,8 +90,8 @@ public: virtual sc_time getRefreshIntervalAB() const override; virtual sc_time getRefreshIntervalPB() const override; - virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command) const override; + virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; virtual uint64_t getSimMemSizeInBytes() const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp index c299f9d9..25f77ef9 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.cpp @@ -130,7 +130,7 @@ sc_time MemSpecHBM2::getExecutionTime(Command command, const tlm_generic_payload } } -TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command) const +TimeInterval MemSpecHBM2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return TimeInterval(tRL + tDQSCK, tRL + tDQSCK + burstDuration); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h index a56f18fb..f5c0fbb0 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM2.h @@ -85,8 +85,8 @@ public: virtual bool hasRasAndCasBus() const override; - virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command) const override; + virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; virtual uint64_t getSimMemSizeInBytes() const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp index a046a7d7..9e181a0d 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.cpp @@ -132,7 +132,7 @@ sc_time MemSpecLPDDR4::getExecutionTime(Command command, const tlm_generic_paylo } } -TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command) const +TimeInterval MemSpecLPDDR4::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return TimeInterval(tRL + tDQSCK + 3 * tCK, diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h index 4c7d0d52..8005422e 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecLPDDR4.h @@ -83,8 +83,8 @@ public: virtual sc_time getRefreshIntervalAB() const override; virtual sc_time getRefreshIntervalPB() const override; - virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command) const override; + virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; virtual uint64_t getSimMemSizeInBytes() const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp index 91f9f1c8..dcbd1ae7 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.cpp @@ -126,7 +126,7 @@ sc_time MemSpecWideIO::getExecutionTime(Command command, const tlm_generic_paylo } } -TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command) const +TimeInterval MemSpecWideIO::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return TimeInterval(tRL + tAC, tRL + tAC + burstDuration); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h index eb1ad7d7..79b2818c 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO.h @@ -95,8 +95,8 @@ public: virtual sc_time getRefreshIntervalAB() const override; - virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command) const override; + virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; virtual uint64_t getSimMemSizeInBytes() const override; }; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp index 2b93a0cc..eb0efe10 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.cpp @@ -117,7 +117,7 @@ sc_time MemSpecWideIO2::getExecutionTime(Command command, const tlm_generic_payl } } -TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command) const +TimeInterval MemSpecWideIO2::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const { if (command == Command::RD || command == Command::RDA) return TimeInterval(tRL + tDQSCK, tRL + tDQSCK + burstDuration); diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h index 35503a61..31b01a7d 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpecWideIO2.h @@ -77,8 +77,8 @@ public: virtual sc_time getRefreshIntervalAB() const override; virtual sc_time getRefreshIntervalPB() const override; - virtual sc_time getExecutionTime(Command, const tlm::tlm_generic_payload &) const override; - virtual TimeInterval getIntervalOnDataStrobe(Command) const override; + virtual sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override; + virtual TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override; virtual uint64_t getSimMemSizeInBytes() const override; }; diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index af67bdae..29269952 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -313,7 +313,7 @@ void Controller::controllerMethod() manageRequests(thinkDelayFw); respQueue->insertPayload(payload, sc_time_stamp() + thinkDelayFw + phyDelayFw - + memSpec->getIntervalOnDataStrobe(command).end + + memSpec->getIntervalOnDataStrobe(command, *payload).end + phyDelayBw + thinkDelayBw); sc_time triggerTime = respQueue->getTriggerTime(); diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index bd548d50..243d43e5 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -75,7 +75,7 @@ void ControllerRecordable::sendToDram(Command command, tlm_generic_payload *payl { if (isCasCommand(command)) { - TimeInterval dataStrobe = Configuration::getInstance().memSpec->getIntervalOnDataStrobe(command); + TimeInterval dataStrobe = Configuration::getInstance().memSpec->getIntervalOnDataStrobe(command, *payload); tlmRecorder->updateDataStrobe(sc_time_stamp() + delay + dataStrobe.start, sc_time_stamp() + delay + dataStrobe.end, *payload); } diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp index 1de608a8..67ee3b73 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp @@ -59,29 +59,50 @@ CheckerDDR5::CheckerDDR5() last4ActivatesLogical = std::vector>(memSpec->numberOfLogicalRanks); last4ActivatesPhysical = std::vector>(memSpec->numberOfPhysicalRanks); + lastBurstLengthByCommandAndDIMMRank = std::vector> + (4, std::vector(memSpec->numberOfDIMMRanks)); + lastBurstLengthByCommandAndPhysicalRank = std::vector> + (4, std::vector(memSpec->numberOfPhysicalRanks)); + lastBurstLengthByCommandAndLogicalRank = std::vector> + (4, std::vector(memSpec->numberOfLogicalRanks)); + lastBurstLengthByCommandAndBankGroup = std::vector> + (4, std::vector(memSpec->numberOfBankGroups)); + lastBurstLengthByCommandAndBank = std::vector> + (4, std::vector(memSpec->numberOfBanks)); + lastBurstLengthByCommand = std::vector(4); + lastBurstLengthByCommandAndBankInGroup = std::vector> + (4, std::vector(memSpec->numberOfRanks * memSpec->banksPerGroup)); + cmdOffset = memSpec->cmdMode * memSpec->tCK; - tRD_BURST = memSpec->burstLength / memSpec->dataRate * memSpec->tCK; - tWR_BURST = memSpec->burstLength / memSpec->dataRate * memSpec->tCK; + tRD_BURST = 8 * memSpec->tCK; + tWR_BURST = 8 * memSpec->tCK; tWTRA = memSpec->tWR - memSpec->tRTP; - tWRRDA = memSpec->tWL + tWR_BURST + tWTRA; + tWRRDA = memSpec->tWL + tWR_BURST + tWTRA; // tWTRA = tWR - tRTP tWRPRE = memSpec->tWL + tWR_BURST + memSpec->tWR; tRDAACT = memSpec->tRTP + memSpec->tRP; tWRAACT = tWRPRE + memSpec->tRP; - tCCD_L_RTW_slr = memSpec->tRL - memSpec->tWL + tRD_BURST + 2 * memSpec->tCK - memSpec->tRDDQS + memSpec->tRPST + memSpec->tWPRE; - tCCD_S_RTW_slr = memSpec->tRL - memSpec->tWL + tRD_BURST + 2 * memSpec->tCK - memSpec->tRDDQS + memSpec->tRPST + memSpec->tWPRE; - tCCD_RTW_dlr = memSpec->tRL - memSpec->tWL + tRD_BURST + 2 * memSpec->tCK - memSpec->tRDDQS + memSpec->tRPST + memSpec->tWPRE; + tCCD_L_RTW_slr = memSpec->tRL - memSpec->tWL + tRD_BURST + 2 * memSpec->tCK + - memSpec->tRDDQS + memSpec->tRPST + memSpec->tWPRE; + tCCD_S_RTW_slr = memSpec->tRL - memSpec->tWL + tRD_BURST + 2 * memSpec->tCK + - memSpec->tRDDQS + memSpec->tRPST + memSpec->tWPRE; + tCCD_RTW_dlr = memSpec->tRL - memSpec->tWL + tRD_BURST + 2 * memSpec->tCK + - memSpec->tRDDQS + memSpec->tRPST + memSpec->tWPRE; tRDRD_dpr = tRD_BURST + memSpec->tRTRS; tRDRD_ddr = tRD_BURST + memSpec->tRTRS; - tRDWR_dpr = memSpec->tRL - memSpec->tWL + tRD_BURST + memSpec->tRTRS - memSpec->tRDDQS + memSpec->tRPST + memSpec->tWPRE; - tRDWR_ddr = memSpec->tRL - memSpec->tWL + tRD_BURST + memSpec->tRTRS - memSpec->tRDDQS + memSpec->tRPST + memSpec->tWPRE; + tRDWR_dpr = memSpec->tRL - memSpec->tWL + tRD_BURST + memSpec->tRTRS + - memSpec->tRDDQS + memSpec->tRPST + memSpec->tWPRE; + tRDWR_ddr = memSpec->tRL - memSpec->tWL + tRD_BURST + memSpec->tRTRS + - memSpec->tRDDQS + memSpec->tRPST + memSpec->tWPRE; tCCD_L_WTR_slr = memSpec->tWL + tWR_BURST + memSpec->tWTR_L; tCCD_S_WTR_slr = memSpec->tWL + tWR_BURST + memSpec->tWTR_S; tCCD_WTR_dlr = memSpec->tWL + tWR_BURST + memSpec->tWTR_S; tWRWR_dpr = std::max(memSpec->tCCD_WR_dpr, tWR_BURST + memSpec->tRTRS); tWRWR_ddr = tWR_BURST + memSpec->tRTRS; - tWRRD_dpr = memSpec->tWL - memSpec->tRL + tWR_BURST + memSpec->tRTRS + memSpec->tRDDQS + memSpec->tWPST + memSpec->tRPRE; - tWRRD_ddr = memSpec->tWL - memSpec->tRL + tWR_BURST + memSpec->tRTRS + memSpec->tRDDQS + memSpec->tWPST + memSpec->tRPRE; + tWRRD_dpr = memSpec->tWL - memSpec->tRL + tWR_BURST + memSpec->tRTRS + + memSpec->tRDDQS + memSpec->tWPST + memSpec->tRPRE; + tWRRD_ddr = memSpec->tWL - memSpec->tRL + tWR_BURST + memSpec->tRTRS + + memSpec->tRDDQS + memSpec->tWPST + memSpec->tRPRE; tRDPDEN = memSpec->tRL + tRD_BURST + cmdOffset; tWRPDEN = memSpec->tWL + tWR_BURST + memSpec->tWR + cmdOffset; tWRAPDEN = memSpec->tWL + tWR_BURST + memSpec->tWR + cmdOffset; @@ -89,7 +110,8 @@ CheckerDDR5::CheckerDDR5() // TODO: tRTP BL 32 (similar to LPDDR4) } -sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned burstLength) const +sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank, + unsigned burstLength) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -108,93 +130,198 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_slr); + { + if (lastBurstLengthByCommandAndBankGroup[Command::RD][bankgroup.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + 16 * memSpec->tCK); // 16 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_slr); // 16 tCK + } lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RD][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S_slr); + { + if (lastBurstLengthByCommandAndLogicalRank[Command::RD][logicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + 16 * memSpec->tCK); // 16 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S_slr); // 16 tCK + } lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::RD][physicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_dlr); + { + if (lastBurstLengthByCommandAndPhysicalRank[Command::RD][physicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + 16 * memSpec->tCK); // 16 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_dlr); // 16 tCK + } lastCommandStart = lastScheduledByCommand[Command::RD]; if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::RD][physicalrank.ID()]) { if (lastCommandStart == lastScheduledByCommandAndDIMMRank[Command::RD][dimmrank.ID()]) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_dpr); + { + if (lastBurstLengthByCommandAndDIMMRank[Command::RD][dimmrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_dpr + tRD_BURST); // 16 tCK + tRTRS + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_dpr); // 16 tCK + tRTRS + } else - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_ddr); + { + if (lastBurstLengthByCommandAndPhysicalRank[Command::RD][physicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_ddr + tRD_BURST); // 16 tCK + tRTRS + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_ddr); // 16 tCK + tRTRS + } } lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_slr); + { + if (lastBurstLengthByCommandAndBankGroup[Command::RDA][bankgroup.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + 16 * memSpec->tCK); // 16 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_slr); // 16 tCK + } lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RDA][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S_slr); + { + if (lastBurstLengthByCommandAndBankGroup[Command::RDA][bankgroup.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + 16 * memSpec->tCK); // 16 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S_slr); // 16 tCK + } lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::RDA][physicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_dlr); + { + if (lastBurstLengthByCommandAndPhysicalRank[Command::RDA][physicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + 16 * memSpec->tCK); // 16 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_dlr); // 16 tCK + } lastCommandStart = lastScheduledByCommand[Command::RDA]; if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::RDA][physicalrank.ID()]) { if (lastCommandStart == lastScheduledByCommandAndDIMMRank[Command::RDA][dimmrank.ID()]) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_dpr); + { + if (lastBurstLengthByCommandAndDIMMRank[Command::RDA][dimmrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_dpr + tRD_BURST); // 16 tCK + tRTRS + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_dpr); // 16 tCK + tRTRS + } else - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_ddr); + { + if (lastBurstLengthByCommandAndPhysicalRank[Command::RDA][physicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_ddr + tRD_BURST); // 16 tCK + tRTRS + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDRD_ddr); // 16 tCK + tRTRS + } } if (command == Command::RDA) { lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDA); + { + if (lastBurstLengthByCommandAndBank[Command::WR][bank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDA + tWR_BURST); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRDA); // + 8 tCK + } } lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr); + { + if (lastBurstLengthByCommandAndBankGroup[Command::WR][bankgroup.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr + tWR_BURST); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr); // + 8 tCK + } lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WR][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_WTR_slr); + { + if (lastBurstLengthByCommandAndLogicalRank[Command::WR][logicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_WTR_slr + tWR_BURST); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_WTR_slr); // + 8 tCK + } lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::WR][physicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_WTR_dlr); + { + if (lastBurstLengthByCommandAndPhysicalRank[Command::WR][physicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_WTR_dlr + tWR_BURST); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_WTR_dlr); // + 8 tCK + } lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::WR][physicalrank.ID()]) { if (lastCommandStart == lastScheduledByCommandAndDIMMRank[Command::WR][dimmrank.ID()]) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_dpr); + { + if (lastBurstLengthByCommandAndDIMMRank[Command::WR][dimmrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_dpr + tWR_BURST); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_dpr); // + 8 tCK + } else - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_ddr); + { + if (lastBurstLengthByCommand[Command::WR] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_ddr + tWR_BURST); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_ddr); // + 8 tCK + } } lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr); + { + if (lastBurstLengthByCommandAndBankGroup[Command::WRA][bankgroup.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr + tWR_BURST); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_WTR_slr); // + 8 tCK + } lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WRA][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_WTR_slr); + { + if (lastBurstLengthByCommandAndLogicalRank[Command::WRA][logicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_WTR_slr + tWR_BURST); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_WTR_slr); // + 8 tCK + } lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::WRA][physicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_WTR_dlr); + { + if (lastBurstLengthByCommandAndPhysicalRank[Command::WRA][physicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_WTR_dlr + tWR_BURST); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_WTR_dlr); // + 8 tCK + } lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::WRA][physicalrank.ID()]) { if (lastCommandStart == lastScheduledByCommandAndDIMMRank[Command::WRA][dimmrank.ID()]) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_dpr); + { + if (lastBurstLengthByCommandAndDIMMRank[Command::WRA][dimmrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_dpr + tWR_BURST); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_dpr); // + 8 tCK + } else - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_ddr); + { + if (lastBurstLengthByCommand[Command::WRA] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_ddr + tWR_BURST); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRRD_ddr); // + 8 tCK + } } } else if (command == Command::WR || command == Command::WRA) @@ -205,86 +332,206 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankgroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_RTW_slr); + { + if (lastBurstLengthByCommandAndBankGroup[Command::RD][bankgroup.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_RTW_slr + tRD_BURST); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_RTW_slr); // + 8 tCK + } lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RD][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_RTW_slr); + { + if (lastBurstLengthByCommandAndLogicalRank[Command::RD][logicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_RTW_slr + tRD_BURST); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_RTW_slr); // + 8 tCK + } lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::RD][physicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_RTW_dlr); + { + if (lastBurstLengthByCommandAndPhysicalRank[Command::RD][physicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_RTW_dlr + tRD_BURST); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_RTW_dlr); // + 8 tCK + } lastCommandStart = lastScheduledByCommand[Command::RD]; if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::RD][physicalrank.ID()]) { if (lastCommandStart == lastScheduledByCommandAndDIMMRank[Command::RD][dimmrank.ID()]) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_dpr); + { + if (lastBurstLengthByCommandAndDIMMRank[Command::RD][dimmrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_dpr + tRD_BURST); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_dpr); // + 8 tCK + } else - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_ddr); + { + if (lastBurstLengthByCommand[Command::RD] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_ddr + tRD_BURST); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_ddr); // + 8 tCK + } } lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankgroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_RTW_slr); + { + if (lastBurstLengthByCommandAndBankGroup[Command::RDA][bankgroup.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_RTW_slr + tRD_BURST); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_L_RTW_slr); // + 8 tCK + } lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RDA][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_RTW_slr); + { + if (lastBurstLengthByCommandAndLogicalRank[Command::RDA][logicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_RTW_slr + tRD_BURST); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_S_RTW_slr); // + 8 tCK + } lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::RDA][physicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_RTW_dlr); + { + if (lastBurstLengthByCommandAndPhysicalRank[Command::RDA][physicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_RTW_dlr + tRD_BURST); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tCCD_RTW_dlr); // + 8 tCK + } lastCommandStart = lastScheduledByCommand[Command::RDA]; if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::RDA][physicalrank.ID()]) { if (lastCommandStart == lastScheduledByCommandAndDIMMRank[Command::RDA][dimmrank.ID()]) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_dpr); + { + if (lastBurstLengthByCommandAndDIMMRank[Command::RDA][dimmrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_dpr + tRD_BURST); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_dpr); // + 8 tCK + } else - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_ddr); + { + if (lastBurstLengthByCommand[Command::RDA] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_ddr + tRD_BURST); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDWR_ddr); // + 8 tCK + } } lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankgroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR_slr); + { + if (lastBurstLengthByCommandAndBankGroup[Command::WR][bankgroup.ID()] == 32) + { + if (burstLength == 16 && memSpec->bitWidth == 4) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWR_BURST + memSpec->tCCD_L_WR_slr); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWR_BURST + memSpec->tCCD_L_WR2_slr); + } + else + { + if (burstLength == 16 && memSpec->bitWidth == 4) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR_slr); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR2_slr); + } + } lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WR][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S_WR_slr); + { + if (lastBurstLengthByCommandAndLogicalRank[Command::WR][logicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + 16 * memSpec->tCK); // 16 clocks + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S_WR_slr); // 16 clocks + } lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::WR][physicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_WR_dlr); + { + if (lastBurstLengthByCommandAndPhysicalRank[Command::WR][physicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + 16 * memSpec->tCK); // 16 clocks + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_WR_dlr); // 16 clocks + } lastCommandStart = lastScheduledByCommand[Command::WR]; if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::WR][physicalrank.ID()]) { if (lastCommandStart == lastScheduledByCommandAndDIMMRank[Command::WR][dimmrank.ID()]) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_dpr); + { + if (lastBurstLengthByCommandAndDIMMRank[Command::WR][dimmrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_dpr + tWR_BURST); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_dpr); // + 8 tCK + } else - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_ddr); + { + if (lastBurstLengthByCommand[Command::WR] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_ddr + tWR_BURST); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_ddr); // + 8 tCK + } } lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankgroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR_slr); + { + if (lastBurstLengthByCommandAndBankGroup[Command::WRA][bankgroup.ID()] == 32) + { + if (burstLength == 16 && memSpec->bitWidth == 4) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWR_BURST + memSpec->tCCD_L_WR_slr); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWR_BURST + memSpec->tCCD_L_WR2_slr); + } + else + { + if (burstLength == 16 && memSpec->bitWidth == 4) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR_slr); + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_L_WR2_slr); + } + } lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WRA][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S_WR_slr); + { + if (lastBurstLengthByCommandAndLogicalRank[Command::WRA][logicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + 16 * memSpec->tCK); // 16 clocks + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_S_WR_slr); // 16 clocks + } lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::WRA][physicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_WR_dlr); + { + if (lastBurstLengthByCommandAndPhysicalRank[Command::WRA][physicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + 16 * memSpec->tCK); // 16 clocks + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tCCD_WR_dlr); // 16 clocks + } lastCommandStart = lastScheduledByCommand[Command::WRA]; if (lastCommandStart != lastScheduledByCommandAndPhysicalRank[Command::WRA][physicalrank.ID()]) { if (lastCommandStart == lastScheduledByCommandAndDIMMRank[Command::WRA][dimmrank.ID()]) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_dpr); + { + if (lastBurstLengthByCommandAndDIMMRank[Command::WRA][dimmrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_dpr + tWR_BURST); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_dpr); // + 8 tCK + } else - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_ddr); + { + if (lastBurstLengthByCommand[Command::WRA] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_ddr + tWR_BURST); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRWR_ddr); // + 8 tCK + } } } else if (command == Command::ACT) @@ -311,7 +558,12 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAACT); + { + if (lastBurstLengthByCommandAndBank[Command::WRA][bank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAACT + tWR_BURST); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAACT); // + 8 tCK + } lastCommandStart = lastScheduledByCommandAndBank[Command::PRE][bank.ID()]; if (lastCommandStart != sc_max_time()) @@ -347,25 +599,30 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (last4ActivatesLogical[logicalrank.ID()].size() >= 4) earliestTimeToStart = std::max(earliestTimeToStart, last4ActivatesLogical[logicalrank.ID()].front() - + memSpec->tFAW_slr - memSpec->cmdOffset_L); + + memSpec->tFAW_slr - memSpec->longCmdOffset); if (last4ActivatesPhysical[physicalrank.ID()].size() >= 4) earliestTimeToStart = std::max(earliestTimeToStart, last4ActivatesPhysical[physicalrank.ID()].front() - + memSpec->tFAW_dlr - memSpec->cmdOffset_L); + + memSpec->tFAW_dlr - memSpec->longCmdOffset); } else if (command == Command::PRE) { lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + cmdOffset); lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + cmdOffset); lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tCK); + { + if (lastBurstLengthByCommandAndBank[Command::WR][bank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + tWR_BURST + cmdOffset); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + cmdOffset); // + 8 tCK + } lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::PRE][physicalrank.ID()]; if (lastCommandStart != sc_max_time()) @@ -383,23 +640,33 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr { lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::ACT][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + cmdOffset); lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RD][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + cmdOffset); lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::RDA][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + cmdOffset); lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WR][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tCK); + { + if (lastBurstLengthByCommandAndLogicalRank[Command::WR][logicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + tWR_BURST + cmdOffset); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + cmdOffset); // + 8 tCK + } lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WRA][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tCK); + { + if (lastBurstLengthByCommandAndLogicalRank[Command::WRA][logicalrank.ID()]) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + tWR_BURST + cmdOffset); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + cmdOffset); // + 8 tCK + } lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::PRE][physicalrank.ID()]; if (lastCommandStart != sc_max_time()) @@ -415,23 +682,33 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr { lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::ACT][bankInGroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + cmdOffset); lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::RD][bankInGroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + cmdOffset); lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::RDA][bankInGroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRTP + cmdOffset); lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::WR][bankInGroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tCK); + { + if (lastBurstLengthByCommandAndBankInGroup[Command::WR][bankInGroup.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + tWR_BURST + cmdOffset); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + cmdOffset); // + 8 tCK + } lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::WRA][bankInGroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tCK); + { + if (lastBurstLengthByCommandAndBankInGroup[Command::WRA][bankInGroup.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + tWR_BURST + cmdOffset); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + cmdOffset); // + 8 tCK + } lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::PRE][physicalrank.ID()]; if (lastCommandStart != sc_max_time()) @@ -447,15 +724,20 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr { lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::ACT][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + cmdOffset); lastCommandStart = lastScheduledByCommandAndPhysicalRank[Command::RDA][physicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDAACT + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDAACT + cmdOffset); lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::WRA][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP + memSpec->tCK); + { + if (lastBurstLengthByCommandAndLogicalRank[Command::WRA][logicalrank.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + tWR_BURST + memSpec->tRP + cmdOffset); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRPRE + memSpec->tRP + cmdOffset); // + 8 tCK + } lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::PRE][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) @@ -484,19 +766,24 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr { lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::ACT][bankInGroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRC + cmdOffset); lastCommandStart = lastScheduledByCommandAndLogicalRank[Command::ACT][logicalrank.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD_L_slr + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD_L_slr + cmdOffset); lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::RDA][bankInGroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDAACT + memSpec->tCK); + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tRDAACT + cmdOffset); lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::WRA][bankInGroup.ID()]; if (lastCommandStart != sc_max_time()) - earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAACT + memSpec->tCK); + { + if (lastBurstLengthByCommandAndBankInGroup[Command::WRA][bankInGroup.ID()] == 32) + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAACT + tWR_BURST + cmdOffset); // + 8 tCK + else + earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tWRAACT + cmdOffset); // + 8 tCK + } lastCommandStart = lastScheduledByCommandAndBankInGroup[Command::PRE][bankInGroup.ID()]; if (lastCommandStart != sc_max_time()) @@ -532,11 +819,11 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr if (last4ActivatesLogical[logicalrank.ID()].size() >= 4) earliestTimeToStart = std::max(earliestTimeToStart, last4ActivatesLogical[logicalrank.ID()].front() - + memSpec->tFAW_slr - memSpec->cmdOffset_S); + + memSpec->tFAW_slr - memSpec->shortCmdOffset); if (last4ActivatesPhysical[physicalrank.ID()].size() >= 4) earliestTimeToStart = std::max(earliestTimeToStart, last4ActivatesPhysical[physicalrank.ID()].front() - + memSpec->tFAW_dlr - memSpec->cmdOffset_S); + + memSpec->tFAW_dlr - memSpec->shortCmdOffset); } else SC_REPORT_FATAL("CheckerDDR5", "Unknown command!"); @@ -547,7 +834,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr return earliestTimeToStart; } -void CheckerDDR5::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) +void CheckerDDR5::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned burstLength) { PRINTDEBUGMESSAGE("CheckerDDR5", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); @@ -555,6 +842,7 @@ void CheckerDDR5::insert(Command command, Rank rank, BankGroup bankgroup, Bank b Rank logicalrank = rank; Rank physicalrank = Rank(logicalrank.ID() / memSpec->logicalRanksPerPhysicalRank); Rank dimmrank = Rank(physicalrank.ID() / memSpec->physicalRanksPerDIMMRank); + Bank bankingroup = Bank(rank.ID() * memSpec->banksPerGroup + bank.ID() % memSpec->banksPerGroup); lastScheduledByCommandAndDIMMRank[command][dimmrank.ID()] = sc_time_stamp(); lastScheduledByCommandAndPhysicalRank[command][physicalrank.ID()] = sc_time_stamp(); @@ -565,8 +853,18 @@ void CheckerDDR5::insert(Command command, Rank rank, BankGroup bankgroup, Bank b lastCommandOnBus = sc_time_stamp() + memSpec->getCommandLength(command) - memSpec->tCK; - lastScheduledByCommandAndBankInGroup[command][rank.ID() * memSpec->banksPerGroup - + bank.ID() % memSpec->banksPerGroup] = sc_time_stamp(); + lastScheduledByCommandAndBankInGroup[command][bankingroup.ID()] = sc_time_stamp(); + + if (isCasCommand(command)) + { + lastBurstLengthByCommandAndDIMMRank[command][dimmrank.ID()] = burstLength; + lastBurstLengthByCommandAndPhysicalRank[command][physicalrank.ID()] = burstLength; + lastBurstLengthByCommandAndLogicalRank[command][logicalrank.ID()] = burstLength; + lastBurstLengthByCommandAndBankGroup[command][bankgroup.ID()] = burstLength; + lastBurstLengthByCommandAndBank[command][bank.ID()] = burstLength; + lastBurstLengthByCommand[command] = burstLength; + lastBurstLengthByCommandAndBankInGroup[command][bankingroup.ID()] = burstLength; + } if (command == Command::ACT || command == Command::REFSB) { diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR5.h b/DRAMSys/library/src/controller/checker/CheckerDDR5.h index 7bd2f4ad..ace723e4 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR5.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR5.h @@ -65,6 +65,15 @@ private: std::vector> last4ActivatesPhysical; std::vector> last4ActivatesLogical; + std::vector> lastBurstLengthByCommandAndDIMMRank; + std::vector> lastBurstLengthByCommandAndPhysicalRank; + std::vector> lastBurstLengthByCommandAndLogicalRank; + std::vector> lastBurstLengthByCommandAndBankGroup; + std::vector> lastBurstLengthByCommandAndBank; + std::vector lastBurstLengthByCommand; + + std::vector> lastBurstLengthByCommandAndBankInGroup; + // TODO: store BL of last RD and WR globally or for each hierarchy? sc_time cmdOffset;