From f9ef97f361381da11830782add2a71012e45c973 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=C3=89der=20F=2E=20Zulian?= <zulian@eit.uni-kl.de>
Date: Tue, 10 Jul 2018 17:19:51 +0200
Subject: [PATCH] changes in rgr default config

---
 DRAMSys/library/resources/configs/memspecs/rgrspec.xml | 4 ++--
 DRAMSys/library/resources/simulations/rgrsim.xml       | 1 +
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/DRAMSys/library/resources/configs/memspecs/rgrspec.xml b/DRAMSys/library/resources/configs/memspecs/rgrspec.xml
index f1ddefd8..52d20f56 100644
--- a/DRAMSys/library/resources/configs/memspecs/rgrspec.xml
+++ b/DRAMSys/library/resources/configs/memspecs/rgrspec.xml
@@ -1,4 +1,4 @@
-<!DOCTYPE memspec SYSTEM "memspec.dtd">
+
 <memspec>
     <parameter id="memoryId" type="string" value="rgrspec" />
     <parameter id="memoryType" type="string" value="DDR4" />
@@ -15,7 +15,7 @@
         <parameter id="nbrOfRows" type="uint" value="16384" />
         <parameter id="nbrOfRows" type="uint" value="8192" />
         -->
-        <parameter id="nbrOfRows" type="uint" value="8192" />
+        <parameter id="nbrOfRows" type="uint" value="131072" />
         <parameter id="dataRate" type="uint" value="2" />
         <parameter id="burstLength" type="uint" value="8" />
     </memarchitecturespec>
diff --git a/DRAMSys/library/resources/simulations/rgrsim.xml b/DRAMSys/library/resources/simulations/rgrsim.xml
index 3dee8806..342bf8ec 100644
--- a/DRAMSys/library/resources/simulations/rgrsim.xml
+++ b/DRAMSys/library/resources/simulations/rgrsim.xml
@@ -14,6 +14,7 @@
     <!-- <tracesetup id="no_refresh_fr_fcfs_nbw_b16_ddr4_8b_1x"> -->
     <tracesetup id="rgrsetup">
         <!--
+        <device clkMhz="1000">rgr_all_rows.stl</device>
         <device clkMhz="1000">rgr_pullin_test.stl</device>
         <device clkMhz="1000">rgr_postpone_test.stl</device>
         <device clkMhz="1000">rgr_bw_postpone_test.stl</device>