diff --git a/DRAMSys/library/resources/configs/memspecs/HBM3.json b/DRAMSys/library/resources/configs/memspecs/HBM3.json
index 17cf58e7..16c18b75 100644
--- a/DRAMSys/library/resources/configs/memspecs/HBM3.json
+++ b/DRAMSys/library/resources/configs/memspecs/HBM3.json
@@ -10,7 +10,10 @@
             "nbrOfRows": 32768,
             "width": 32,
             "nbrOfDevices": 1,
-            "nbrOfChannels": 1
+            "nbrOfChannels": 1,
+            "RAAIMT" : 16,
+            "RAAMMT" : 96,
+            "RAACDR" : 16
         },
         "memoryId": "",
         "memoryType": "HBM3",
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM3.cpp b/DRAMSys/library/src/configuration/memspec/MemSpecHBM3.cpp
index cfe3f422..d5aeaada 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM3.cpp
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM3.cpp
@@ -56,6 +56,9 @@ MemSpecHBM3::MemSpecHBM3(const DRAMSysConfiguration::MemSpec &memSpec)
       memSpec.memArchitectureSpec.entries.at("nbrOfBankGroups")
           * memSpec.memArchitectureSpec.entries.at("nbrOfPseudoChannels"),
       memSpec.memArchitectureSpec.entries.at("nbrOfDevices")),
+      RAAIMT(memSpec.memArchitectureSpec.entries.at("RAAIMT")),
+      RAAMMT(memSpec.memArchitectureSpec.entries.at("RAAMMT")),
+      RAACDR(memSpec.memArchitectureSpec.entries.at("RAACDR")),
       tDQSCK  (tCK * memSpec.memTimingSpec.entries.at("DQSCK")),
       tRC     (tCK * memSpec.memTimingSpec.entries.at("RC")),
       tRAS    (tCK * memSpec.memTimingSpec.entries.at("RAS")),
@@ -151,9 +154,9 @@ sc_time MemSpecHBM3::getExecutionTime(Command command, const tlm_generic_payload
         return tWL + burstDuration;
     else if (command == Command::WRA)
         return tWL + burstDuration + tWR + tRP;
-    else if (command == Command::REFAB)
+    else if (command == Command::REFAB || command == Command::RFMAB)
         return tRFC;
-    else if (command == Command::REFPB)
+    else if (command == Command::REFPB || command == Command::RFMPB)
         return tRFCPB;
     else
     {
@@ -175,3 +178,18 @@ TimeInterval MemSpecHBM3::getIntervalOnDataStrobe(Command command, const tlm_gen
         return {};
     }
 }
+
+unsigned MemSpecHBM3::getRAACDR() const
+{
+    return RAACDR;
+}
+
+unsigned MemSpecHBM3::getRAAIMT() const
+{
+    return RAAIMT;
+}
+
+unsigned MemSpecHBM3::getRAAMMT() const
+{
+    return RAAMMT;
+}
diff --git a/DRAMSys/library/src/configuration/memspec/MemSpecHBM3.h b/DRAMSys/library/src/configuration/memspec/MemSpecHBM3.h
index 8695461d..f9a32241 100644
--- a/DRAMSys/library/src/configuration/memspec/MemSpecHBM3.h
+++ b/DRAMSys/library/src/configuration/memspec/MemSpecHBM3.h
@@ -45,6 +45,10 @@ class MemSpecHBM3 final : public MemSpec
 public:
     explicit MemSpecHBM3(const DRAMSysConfiguration::MemSpec &memSpec);
 
+    const unsigned RAAIMT;
+    const unsigned RAAMMT;
+    const unsigned RAACDR;
+
     // Memspec Variables:
     const sc_core::sc_time tDQSCK;
 //    sc_time tDQSQ; // TODO: check actual value of this parameter
@@ -85,6 +89,10 @@ public:
     sc_core::sc_time getRefreshIntervalAB() const override;
     sc_core::sc_time getRefreshIntervalPB() const override;
 
+    unsigned getRAACDR() const override;
+    unsigned getRAAIMT() const override;
+    unsigned getRAAMMT() const override;
+
     bool hasRasAndCasBus() const override;
 
     sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;