diff --git a/DRAMSys/simulator/resources/scripts/generateTrace.py b/DRAMSys/simulator/resources/scripts/generateTrace.py
new file mode 100644
index 00000000..ba22f861
--- /dev/null
+++ b/DRAMSys/simulator/resources/scripts/generateTrace.py
@@ -0,0 +1,23 @@
+#!/usr/bin/python
+# This script generates an example trace for DDR3
+#
+#<addressmapping>
+#    <channel from="128"  to="128"  /> <!-- only one channel -->
+#    <bank    from="27"   to="29"   />
+#    <row     from="13"   to="26"   /> 26 downto 13 --> 2^14 = 16384
+#    <column  from="3"    to="12"   /> Burstlength = 8 --> 8 down bits always zero --> 12 downto 3 --> 7 --> 2^7 = 128
+#    <bytes   from="0"    to="2"    /> 2^3 = 8
+#</addressmapping>
+
+numberOfRows = 16384
+numberOfColumns = 128
+byteOffset = 64
+bankOffset = numberOfRows * numberOfColumns
+
+# Write to Bank 0
+for x in range(0, bankOffset):
+    print "{0:d}:\tread\t0x{1:X}".format(x,(x*byteOffset))
+
+# Write to Bank 1
+for x in range(bankOffset, 2*bankOffset):
+    print "{0:d}:\tread\t0x{1:X}".format(x,(x*byteOffset))