DRAMSys_gem5 - numumber of transactors from config

DRAMSys - new config UseMalloc (default is mmap())

DRAMSys/gem5/gem5_se/run.sh

@@ -85,7 +85,8 @@ for s in $simfiles; do
 		`sed -i s/id=\".*\"/id=\"${sfn}_${bin}\"/g $sf`
 		simulation="${sfpath}/${sfn}_${bin}.${ext}"
 		cp $sf $simulation
-		LD_PRELOAD=/usr/lib/libtcmalloc.so ./${elf} ${simulation} ../../DRAMSys/gem5/gem5_se/${bin}/config.ini >> out_${sfn}_${bin}.txt &
+		# LD_PRELOAD=/usr/lib/libtcmalloc.so ./${elf} ${simulation} ../../DRAMSys/gem5/gem5_se/${bin}/config.ini >> out_${sfn}_${bin}.txt &
+		./${elf} ${simulation} ../../DRAMSys/gem5/gem5_se/${bin}/config.ini >> out_${sfn}_${bin}.txt &
 	done
 done
 

DRAMSys/gem5/main.cpp

@@ -39,6 +39,7 @@
 #include <systemc>
 #include <tlm>
 #include <string>
+#include <cstdlib>
 
 #include "DRAMSys.h"
 #include "TraceSetup.h"
@@ -133,16 +134,21 @@ int sc_main(int argc, char **argv)
     string SimulationXML;
     string gem5ConfigFile;
     string resources;
+    unsigned int numTransactors;
+    Gem5SystemC::Gem5SlaveTransactor *t;
+    std::vector<Gem5SystemC::Gem5SlaveTransactor *> transactors;
 
-    if (argc > 1) {
+    if (argc == 4) {
         // Get path of resources:
         resources = pathOfFile(argv[0])
                     + string("/../../DRAMSys/library/resources/");
 
         SimulationXML = argv[1];
         gem5ConfigFile = argv[2];
+        numTransactors = atoi(argv[3]);
+
     } else {
-        SC_REPORT_FATAL("sc_main", "Please provide configuration files");
+        SC_REPORT_FATAL("sc_main", "Please provide configuration files and number of ports");
     }
 
     // Instantiate DRAMSys:
@@ -150,25 +156,28 @@ int sc_main(int argc, char **argv)
 
     // Instantiate gem5:
     Gem5SimControlDRAMsys sim_control(gem5ConfigFile);
-#define CHOICE1
-//#define CHOICE2
-//#define CHOICE3
 
-#ifdef CHOICE1 //If only one gem5 port is used
+    // XXX: this code assumes:
-    Gem5SystemC::Gem5SlaveTransactor transactor("transactor", "transactor");
+    // - for a single port the port name is "transactor"
-    transactor.socket.bind(dramSys.tSocket);
+    // - for multiple ports names are transactor1, transactor2, ..., transactorN
-    transactor.sim_control.bind(sim_control);
+    // Names generated here must match port names used by the gem5 config file, e.g., config.ini
-#endif
+    if (numTransactors == 1) {
-
+        t = new Gem5SystemC::Gem5SlaveTransactor("transactor", "transactor");
-#ifdef CHOICE2
+        t->socket.bind(dramSys.tSocket);
-    // If there are two ports
+        t->sim_control.bind(sim_control);
-    Gem5SystemC::Gem5SlaveTransactor transactor1("transactor1", "transactor1");
+        transactors.push_back(t);
-    Gem5SystemC::Gem5SlaveTransactor transactor2("transactor2", "transactor2");
+    } else {
-    transactor1.socket.bind(dramSys.tSocket);
+        for (unsigned i = 0; i < numTransactors; i++) {
-    transactor2.socket.bind(dramSys.tSocket);
+            // If there are two or more ports
-    transactor1.sim_control.bind(sim_control);
+            unsigned index = i + 1;
-    transactor2.sim_control.bind(sim_control);
+            std::string name = "transactor" + std::to_string(index);
-#endif
+            std::string portName = "transactor" + std::to_string(index);
+            t = new Gem5SystemC::Gem5SlaveTransactor(name.c_str(), portName.c_str());
+            t->socket.bind(dramSys.tSocket);
+            t->sim_control.bind(sim_control);
+            transactors.push_back(t);
+        }
+    }
 
 #ifdef CHOICE3
     // If for example two gem5 ports are used (NVM and DRAM) with
@@ -198,6 +207,10 @@ int sc_main(int argc, char **argv)
         sc_core::sc_stop();
     }
 
+    for (auto t : transactors) {
+       delete t;
+    }
+
     SC_REPORT_INFO("sc_main", "End of Simulation");
 
     return EXIT_SUCCESS;

DRAMSys/library/resources/configs/simulator/ddr3-single-device.xml

@@ -20,4 +20,5 @@
 	- ErrorModel (store data with errormodel)
     -->
     <StoreMode value="NoStorage" />
+    <UseMalloc value="0" />
 </simconfig>

DRAMSys/library/resources/configs/simulator/ddr3.xml

@@ -25,4 +25,5 @@
     E.g. the DRAM is located at 0x80000000 for gem5
     <AddressOffset value = "2147483648" />
     -->
+    <UseMalloc value="0" />
 </simconfig>

DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.xml

@@ -10,7 +10,6 @@
     <NumberOfMemChannels value="1"/>
     <NumberOfDevicesOnDIMM value = "8" />
     <CheckTLM2Protocol value = "0" />
-    <AddressOffset value = "0" />
     <ECCControllerMode value = "Disabled" />
     <ErrorChipSeed value="42" />
     <ErrorCSVFile value="" />
@@ -25,4 +24,5 @@
     E.g. the DRAM is located at 0x80000000 for gem5
     -->
     <AddressOffset value = "2147483648" />
+    <UseMalloc value="1" />
 </simconfig>

DRAMSys/library/resources/configs/simulator/ddr3_ecc.xml

@@ -20,4 +20,5 @@
 	- ErrorModel (store data with errormodel)
     -->
     <StoreMode value="ErrorModel" />
+    <UseMalloc value="0" />
 </simconfig>

DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.xml

@@ -25,4 +25,5 @@
     E.g. the DRAM is located at 0x80000000 for gem5
     <AddressOffset value = "2147483648" />
     -->
+    <UseMalloc value="0" />
 </simconfig>

DRAMSys/library/resources/configs/simulator/orgr.xml

@@ -48,4 +48,5 @@
     <ControllerCoreRGRB14 value="0"/>
     <ControllerCoreRGRB15 value="0"/>
 
+    <UseMalloc value="0" />
 </simconfig>

DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.xml

@@ -48,4 +48,5 @@
     <ControllerCoreRGRB14 value="0"/>
     <ControllerCoreRGRB15 value="0"/>
 
+    <UseMalloc value="0" />
 </simconfig>

DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.xml

@@ -48,4 +48,5 @@
     <ControllerCoreRGRB14 value="0"/>
     <ControllerCoreRGRB15 value="0"/>
 
+    <UseMalloc value="0" />
 </simconfig>

DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.xml

@@ -48,4 +48,5 @@
     <ControllerCoreRGRB14 value="0"/>
     <ControllerCoreRGRB15 value="0"/>
 
+    <UseMalloc value="0" />
 </simconfig>

DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.xml

@@ -48,4 +48,5 @@
     <ControllerCoreRGRB14 value="0"/>
     <ControllerCoreRGRB15 value="0"/>
 
+    <UseMalloc value="0" />
 </simconfig>

DRAMSys/library/resources/configs/simulator/orgr_ddr4.xml

@@ -15,4 +15,5 @@
     <ErrorChipSeed value="42" />
     <ErrorCSVFile value="" />
     <StoreMode value="NoStorage" />
+    <UseMalloc value="0" />
 </simconfig>

DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-se.xml

@@ -15,4 +15,5 @@
     <ErrorChipSeed value="42" />
     <ErrorCSVFile value="" />
     <StoreMode value="Store" />
+    <UseMalloc value="0" />
 </simconfig>

DRAMSys/library/resources/configs/simulator/rgrsimcfg.xml

@@ -15,4 +15,5 @@
     <ErrorChipSeed value="42" />
     <ErrorCSVFile value="" />
     <StoreMode value="NoStorage" />
+    <UseMalloc value="0" />
 </simconfig>

DRAMSys/library/resources/configs/simulator/sms.xml

@@ -10,5 +10,6 @@
     <NumberOfMemChannels value="4"/>
     <NumberOfDevicesOnDIMM value = "1" />
     <CheckTLM2Protocol value = "0" />
+    <UseMalloc value="0" />
 </simconfig>
 

DRAMSys/library/resources/configs/simulator/wideio.xml

@@ -19,5 +19,6 @@
 	- ErrorModel (store data with errormodel)
     -->
     <StoreMode value="NoStorage" />
+    <UseMalloc value="0" />
 </simconfig>
 

DRAMSys/library/resources/configs/simulator/wideio_ecc.xml

@@ -19,5 +19,6 @@
 	- ErrorModel (store data with errormodel)
     -->
     <StoreMode value="ErrorModel" />
+    <UseMalloc value="0" />
 </simconfig>
 

DRAMSys/library/resources/configs/simulator/wideio_thermal.xml

@@ -19,5 +19,6 @@
 	- ErrorModel (store data with errormodel)
     -->
     <StoreMode value="NoStorage" />
+    <UseMalloc value="0" />
 </simconfig>
 

DRAMSys/library/src/controller/core/configuration/Configuration.cpp

@@ -279,6 +279,8 @@ void Configuration::setParameter(std::string name, std::string value)
 #else
         AddressOffset = 0;
 #endif
+    } else if (name == "UseMalloc") {
+        UseMalloc = string2bool(value);
     } else if (name == "CheckTLM2Protocol")
         CheckTLM2Protocol = string2bool(value);
     else if (name == "ECCControllerMode")

DRAMSys/library/src/controller/core/configuration/Configuration.h

@@ -134,6 +134,7 @@ struct  Configuration {
     ECCControllerMode ECCMode = ECCControllerMode::Disabled;
     ECCBaseClass *pECC = nullptr;
     bool gem5 = false;
+    bool UseMalloc = false;
     unsigned long long int AddressOffset = 0;
 
     // MemSpec (from DRAM-Power XML)

DRAMSys/library/src/simulation/Dram.h

@@ -60,8 +60,6 @@
 #include "../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
 #include "../error/errormodel.h"
 
-//#define USE_MALLOC
-
 using namespace std;
 using namespace tlm;
 using namespace Data;
@@ -98,15 +96,15 @@ struct Dram : sc_module {
         dramController = NULL;
 
         std::uint64_t memorySize = Configuration::getInstance().getSimMemSizeInBytes();
-#ifdef USE_MALLOC
+        if (Configuration::getInstance().UseMalloc) {
-        memory = (unsigned char *)malloc(memorySize);
+            memory = (unsigned char *)malloc(memorySize);
-        if (!memory) {
+            if (!memory) {
-            SC_REPORT_FATAL(this->name(), "Memory allocation failed");
+                SC_REPORT_FATAL(this->name(), "Memory allocation failed");
+            }
+        } else {
+            // allocate and model storage of one DRAM channel using memory map
+            memory = (unsigned char *)mmap(NULL, memorySize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0);
         }
-#else
-        // allocate and model storage of one DRAM channel using memory map
-        memory = (unsigned char *)mmap(NULL, memorySize, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON | MAP_NORESERVE, -1, 0);
-#endif
 
         tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw);
         tSocket.register_transport_dbg(this, &Dram::transport_dbg);
@@ -309,9 +307,9 @@ struct Dram : sc_module {
             delete e;
         }
 
-#ifdef USE_MALLOC
+        if (Configuration::getInstance().UseMalloc) {
-        free(memory);
+            free(memory);
-#endif
+        }
     }
 
     virtual tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload,

README.md

@@ -457,6 +457,7 @@ Below, the sub-configurations are listed and explained.
       <NumberOfMemChannels value="1"/>
       <NumberOfDevicesOnDIMM value = "8" />
       <ECCControllerMode value = "Disabled" />
+      <UseMalloc value = "0" />
   </simconfig>
   ```
 
@@ -498,6 +499,9 @@ Below, the sub-configurations are listed and explained.
   - *ECCControllerMode* (string)
     - "Disabled": No ECC Controller is used
     - "Hamming": Enables an ECC Controller with classic SECDED implementation using Hamming Code
+  - *UseMalloc* (boolean)
+    - "0": model storage using mmap() (DEFAULT)
+    - "1": allocate memory for modeling storage using malloc()
 
 - **Temperature Simulator Configuration**
 
@@ -1543,12 +1547,12 @@ in a conf directory of this building directory.
 Then the simulation can be started with:
 
 ```bash
-./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.xml config.ini
+./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.xml config.ini 1
 ```
 
 Let the simulation run for some seconds and then stop it with **CTRL-C**.
 Observe the output of the simulation in the trace analyzer. The trace database
-file is stored in the gem5 directory in the building directory.
+can be found inside the gem5 directory in the building directory.
 
 ### Gem5 SE mode and DRAMSys
 
@@ -1634,7 +1638,6 @@ The simconfig should be changed in order to support storage and address offsets:
     <NumberOfMemChannels value="1"/>
     <NumberOfDevicesOnDIMM value = "8" />
     <CheckTLM2Protocol value = "0" />
-    <AddressOffset value = "0" />
     <ECCControllerMode value = "Disabled" />
     <ErrorChipSeed value="42" />
     <ErrorCSVFile value="" />
@@ -1650,13 +1653,14 @@ The simconfig should be changed in order to support storage and address offsets:
     -->
     <StoreMode value="Store" />
     <AddressOffset value = "2147483648" />
+    <UseMalloc value = "1" />
 </simconfig>
 ```
 
 Then start DRAMSys_gem5 with the following command:
 
 ```bash
-./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.xml config.ini
+./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.xml config.ini 1
 ```
 
 For further sophisticated address mappings or scenarios checkout the file DRAMSys/gem5/main.cpp
@@ -1674,7 +1678,7 @@ tar -xaf DRAMSys/gem5/boot_linux/linux-aarch32-ael.img.tar.gz -C DRAMSys/gem5/bo
 Execute the example:
 
 ```bash
-./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-boot-linux.xml ../../DRAMSys/gem5/configs/boot_linux.ini 
+./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-boot-linux.xml ../../DRAMSys/gem5/configs/boot_linux.ini 1
 ```
 
 Open a new terminal and connect to gem5:
@@ -1697,7 +1701,7 @@ python files are stored [here](DRAMSys/gem5/examples).
 This is an example for running an elastic trace:
 
 ```bash
-./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.xml ../../DRAMSys/gem5/configs/singleElasticTraceReplay.ini
+./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.xml ../../DRAMSys/gem5/configs/singleElasticTraceReplay.ini 1
 ```
 
 An overview of the architcture being simulated is presented below:
@@ -1709,21 +1713,13 @@ Note that the address offset is usually zero for elastic traces.
 Another example with L2 cache:
 
 ```bash
-./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.xml ../../DRAMSys/gem5/configs/singleElasticTraceReplayWithL2.ini
+./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.xml ../../DRAMSys/gem5/configs/singleElasticTraceReplayWithL2.ini 1
 ```
 
-If two elastic traces should be used the main.cpp must be modified:
+If two elastic traces should be used run the simulation with the following example:
-
-```c++
-//#define CHOICE1
-#define CHOICE2
-//#define CHOICE3
-```
-
-Run the simulation with the following example:
 
 ```
-./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.xml ../../DRAMSys/gem5/configs/dualElasticTraceReplay.ini
+./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.xml ../../DRAMSys/gem5/configs/dualElasticTraceReplay.ini 2
 ```
 
 An overview of the architcture being simulated is presented below:
@@ -1738,8 +1734,6 @@ If you need help please contact Matthias Jung.
 Users can profit of running multiple simulations automatically with
 [gem5ilva](DRAMSys/library/resources/scripts/DRAMSylva/gem5ilva.sh).
 
-Enjoy!
-
 ## References
 
 [1] TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, A Virtual Platform for Memory Controller Design Space Exploration