Relocated the python scripts. They now live in the analyzer directory and are deployed to the output folder when building the analyzer.

Major change to simulation logic in dramSys: Commands in a transaction are now scheduled one at a time, instead of
scheduling a whole transaction at once. Since single commands (e.g. Pre or Act) are not that long, refreshes are allowed to be delayed
to allow a command to finsh. Consequently, the whole loop in the ControllerCore about trying to scheduleding a transaction and aborting it when
it collides with a refresh could be ommitted. Lastly, Fifo_Strict has been added, which is a Fifo Scheduler that forces the read and write transactions, even
between different banks to be executed in order. Fifo and FR_FCFS have been modified to fit into the new scheduling logic.

dram/src/simulation/Dram.h

@@ -26,11 +26,12 @@
 
 using namespace std;
 using namespace tlm;
-using namespace core;
+;
 using namespace Data;
 
 
-#define POWER //not better to define in simulation xml? also flag for storage simulation
+//#define POWER
+//not better to define in simulation xml? also flag for storage simulation
 //configuration->PowerAnalysys
 //configuration->ModelStorage
 //configuration->ModelErrotInjection