Relocated the python scripts. They now live in the analyzer directory and are deployed to the output folder when building the analyzer.

Major change to simulation logic in dramSys: Commands in a transaction are now scheduled one at a time, instead of
scheduling a whole transaction at once. Since single commands (e.g. Pre or Act) are not that long, refreshes are allowed to be delayed
to allow a command to finsh. Consequently, the whole loop in the ControllerCore about trying to scheduleding a transaction and aborting it when
it collides with a refresh could be ommitted. Lastly, Fifo_Strict has been added, which is a Fifo Scheduler that forces the read and write transactions, even
between different banks to be executed in order. Fifo and FR_FCFS have been modified to fit into the new scheduling logic.

dram/src/controller/core/configuration/Configuration.cpp

@@ -11,8 +11,6 @@
 
 using namespace std;
 
-namespace core{
-
 string Configuration::memspecUri = "";
 string Configuration::memconfigUri = "";
 
@@ -66,10 +64,6 @@ void Configuration::setParameter(std::string name, std::string value)
         BankwiseLogic = string2bool(value);
     else if(name == "OpenPagePolicy")
         OpenPagePolicy = string2bool(value);
-    else if(name == "AdaptiveOpenPagePolicy")
-        AdaptiveOpenPagePolicy = string2bool(value);
-    else if(name == "RefreshAwareScheduling")
-        RefreshAwareScheduling = string2bool(value);
     else if(name == "MaxNrOfTransactions")
         MaxNrOfTransactions = string2int(value);
     else if(name == "Scheduler")
@@ -113,5 +107,4 @@ void Configuration::setParameters(std::map<std::string, std::string> parameterMa
     }
 }
 
-} /* namespace core */