Relocated the python scripts. They now live in the analyzer directory and are deployed to the output folder when building the analyzer.

Major change to simulation logic in dramSys: Commands in a transaction are now scheduled one at a time, instead of
scheduling a whole transaction at once. Since single commands (e.g. Pre or Act) are not that long, refreshes are allowed to be delayed
to allow a command to finsh. Consequently, the whole loop in the ControllerCore about trying to scheduleding a transaction and aborting it when
it collides with a refresh could be ommitted. Lastly, Fifo_Strict has been added, which is a Fifo Scheduler that forces the read and write transactions, even
between different banks to be executed in order. Fifo and FR_FCFS have been modified to fit into the new scheduling logic.

dram/src/controller/ControllerState.cpp

@@ -0,0 +1,117 @@
+/*
+ * controller_state.cpp
+ *
+ *  Created on: Mar 5, 2014
+ *      Author: jonny
+ */
+
+#include "ControllerState.h"
+#include <algorithm>
+#include "core/TimingCalculation.h"
+
+
+const ScheduledCommand ControllerState::getLastCommand(Command command, Bank bank) //TODO const reference? and make const
+{
+    return lastScheduledByCommandAndBank[command][bank];
+}
+
+const ScheduledCommand ControllerState::getLastCommand(Command command)
+{
+    ScheduledCommand max;
+
+    for (unsigned int i = 0; i < config->memSpec.NumberOfBanks; ++i)
+    {
+        ScheduledCommand current = getLastCommand(command, Bank(i));
+        if (current.getStart() > max.getStart())
+            max = current;
+    }
+
+    return max;
+}
+
+const ScheduledCommand ControllerState::getLastScheduledCommand()
+{
+    ScheduledCommand lastCommand;
+
+    for(Command cmd : getAllCommands())
+    {
+        for(Bank bank : Configuration::getInstance().memSpec.getBanks())
+        {
+            ScheduledCommand& current = lastScheduledByCommandAndBank[cmd][bank];
+            if (current.getStart() > lastCommand.getStart())
+                lastCommand = current;
+        }
+    }
+
+    return lastCommand;
+}
+
+const ScheduledCommand ControllerState::getLastScheduledCommand(Bank bank)
+{
+    ScheduledCommand lastCommand;
+
+    for(Command cmd : getAllCommands())
+    {
+        ScheduledCommand& current = lastScheduledByCommandAndBank[cmd][bank];
+        if (current.getStart() > lastCommand.getStart())
+            lastCommand = current;
+    }
+
+    return lastCommand;
+}
+
+void ControllerState::change(const ScheduledCommand& scheduledCommand)
+{
+    bus.blockSlot(scheduledCommand.getStart());
+
+    lastScheduledByCommandAndBank[scheduledCommand.getCommand()][scheduledCommand.getBank()] = scheduledCommand;
+
+    switch (scheduledCommand.getCommand())
+    {
+    case Command::Read:
+        lastDataStrobeCommands.emplace_back(scheduledCommand);
+        break;
+    case Command::ReadA:
+        rowBufferStates.closeRowBuffer(scheduledCommand.getBank());
+        lastDataStrobeCommands.emplace_back(scheduledCommand);
+        break;
+    case Command::Write:
+        lastDataStrobeCommands.emplace_back(scheduledCommand);
+        break;
+    case Command::WriteA:
+        rowBufferStates.closeRowBuffer(scheduledCommand.getBank());
+        lastDataStrobeCommands.emplace_back(scheduledCommand);
+        break;
+    case Command::AutoRefresh:
+        break;
+    case Command::Activate:
+        rowBufferStates.openRowInRowBuffer(scheduledCommand.getBank(), scheduledCommand.getRow());
+        lastActivates.emplace(scheduledCommand.getStart(), scheduledCommand);
+        break;
+    case Command::Precharge:
+        rowBufferStates.closeRowBuffer(scheduledCommand.getBank());
+        break;
+    case Command::PrechargeAll:
+        rowBufferStates.closeAllRowBuffers();
+        break;
+    case Command::SREF:
+        rowBufferStates.closeRowBuffer(scheduledCommand.getBank());
+        break;
+    default:
+        break;
+    }
+}
+
+void ControllerState::cleanUp(sc_time time)
+{
+    bus.cleanUpSlots(time);
+    vector<ScheduledCommand> tmp;
+    for(ScheduledCommand& command: lastDataStrobeCommands)
+    {
+        if(command.getEnd() >= time || getDistance(command.getEnd(), time) <= config->memSpec.tDataStrobeHistory())
+            tmp.push_back(command);
+    }
+    lastDataStrobeCommands = tmp;
+    if(time >= config->memSpec.tActHistory())
+        lastActivates.erase(lastActivates.begin(), lastActivates.lower_bound(time - config->memSpec.tActHistory()));
+}