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Relocated the python scripts. They now live in the analyzer directory and are deployed to the output folder when building the analyzer.

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Major change to simulation logic in dramSys: Commands in a transaction are now scheduled one at a time, instead of
scheduling a whole transaction at once. Since single commands (e.g. Pre or Act) are not that long, refreshes are allowed to be delayed
to allow a command to finsh. Consequently, the whole loop in the ControllerCore about trying to scheduleding a transaction and aborting it when
it collides with a refresh could be ommitted. Lastly, Fifo_Strict has been added, which is a Fifo Scheduler that forces the read and write transactions, even
between different banks to be executed in order. Fifo and FR_FCFS have been modified to fit into the new scheduling logic.
This commit is contained in:
gernhard2
2015-02-16 08:21:27 +01:00
parent badcc37118
commit f11adf51dc
101 changed files with 1814 additions and 2378 deletions
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4
dram/src/common/xmlAddressdecoder.cpp
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@@ -52,8 +52,8 @@ DecodedAddress xmlAddressDecoder::decodeAddress(sc_dt::uint64 addr)
//result.rank = (addr & masks["rank"]) >> shifts["rank"];
//result.bankgroup = (addr & masks["bankgroup"]) >> shifts["bankgroup"];
result.bank = (addr & masks["bank"]) >> shifts["bank"];
result.bankgroup = result.bank % core::Configuration::getInstance().memSpec.NumberOfBankGroups;
result.rank = result.bank % core::Configuration::getInstance().memSpec.NumberOfRanks;
result.bankgroup = result.bank % Configuration::getInstance().memSpec.NumberOfBankGroups;
result.rank = result.bank % Configuration::getInstance().memSpec.NumberOfRanks;
result.row = (addr & masks["row"]) >> shifts["row"];
result.column = (addr & masks["column"]) >> shifts["column"];
result.bytes = (addr & masks["bytes"]) >> shifts["bytes"];