From ef1fe83bb40123b62b5382fc06580ed63128f225 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Mon, 14 Sep 2015 09:52:49 +0200 Subject: [PATCH] Added DDR3 to the config --- .../configuration/ConfigurationLoader.cpp | 78 +++++++++++++++++++ .../core/configuration/ConfigurationLoader.h | 1 + 2 files changed, 79 insertions(+) diff --git a/DRAMSys/simulator/src/controller/core/configuration/ConfigurationLoader.cpp b/DRAMSys/simulator/src/controller/core/configuration/ConfigurationLoader.cpp index a69063fb..bf4166d4 100644 --- a/DRAMSys/simulator/src/controller/core/configuration/ConfigurationLoader.cpp +++ b/DRAMSys/simulator/src/controller/core/configuration/ConfigurationLoader.cpp @@ -97,6 +97,10 @@ void ConfigurationLoader::loadMemSpec(Configuration& config, XMLElement* memspec { loadDDR4(config, memspec); } + else if (config.memSpec.MemoryType == "DDR3") + { + loadDDR3(config, memspec); + } else if (config.memSpec.MemoryType == "WIDEIO_SDR") { loadWideIO(config, memspec); @@ -129,6 +133,80 @@ void ConfigurationLoader::loadMemConfig(Configuration& config, XMLElement* memco loadConfig(config, memconfig); } +void ConfigurationLoader::loadDDR3(Configuration& config, XMLElement* memspec) +{ + //MemArchitecture + XMLElement* architecture = memspec->FirstChildElement("memarchitecturespec"); + + config.memSpec.NumberOfBanks = queryUIntParameter(architecture, "nbrOfBanks"); + config.memSpec.NumberOfBankGroups = 1; + config.memSpec.NumberOfRanks = queryUIntParameter(architecture, "nbrOfRanks"); + config.memSpec.BurstLength = queryUIntParameter(architecture, "burstLength"); + config.memSpec.nActivate = 4; + config.memSpec.DataRate = queryUIntParameter(architecture, "dataRate"); + config.memSpec.NumberOfRows = queryUIntParameter(architecture, "nbrOfRows"); + config.memSpec.NumberOfColumns = queryUIntParameter(architecture, "nbrOfColumns"); + config.memSpec.BusWidth = queryUIntParameter(architecture, "width"); + config.memSpec.DLL = true; + config.memSpec.termination = true; + + //MemTimings + XMLElement* timings = memspec->FirstChildElement("memtimingspec"); + double clkMhz = queryDoubleParameter(timings, "clkMhz"); + config.memSpec.clk = FrequencyToClk(clkMhz); + sc_time clk = config.memSpec.clk; + config.memSpec.tRP = clk * queryUIntParameter(timings, "RP"); + config.memSpec.tRAS = clk * queryUIntParameter(timings, "RAS"); + config.memSpec.tRC = clk * queryUIntParameter(timings, "RC"); + config.memSpec.tRTP = clk * queryUIntParameter(timings, "RTP"); + config.memSpec.tRRD_S = clk * queryUIntParameter(timings, "RRD"); + config.memSpec.tRRD_L = clk * queryUIntParameter(timings, "RRD"); + config.memSpec.tCCD_S = clk * queryUIntParameter(timings, "CCD"); + config.memSpec.tCCD_L = clk * queryUIntParameter(timings, "CCD"); + config.memSpec.tRCD = clk * queryUIntParameter(timings, "RCD"); + config.memSpec.tNAW = clk * queryUIntParameter(timings, "FAW"); + config.memSpec.tRL = clk * queryUIntParameter(timings, "RL"); + config.memSpec.tWL = clk * queryUIntParameter(timings, "WL"); + config.memSpec.tWR = clk * queryUIntParameter(timings, "WR"); + config.memSpec.tWTR_S = clk * queryUIntParameter(timings, "WTR"); + config.memSpec.tWTR_L = clk * queryUIntParameter(timings, "WTR"); + config.memSpec.tCKESR = clk * queryUIntParameter(timings, "CKESR"); + config.memSpec.tCKE = clk * queryUIntParameter(timings, "CKE"); + config.memSpec.tXP = clk * queryUIntParameter(timings, "XP"); + config.memSpec.tXPDLL = clk * queryUIntParameter(timings, "XPDLL"); + config.memSpec.tXSR = clk * queryUIntParameter(timings, "XS"); + config.memSpec.tXSRDLL = clk * queryUIntParameter(timings, "XSDLL"); + config.memSpec.tAL = clk * queryUIntParameter(timings, "AL"); + config.memSpec.tRFC = clk * queryUIntParameter(timings, "RFC"); + config.memSpec.tREFI = clk * queryUIntParameter(timings, "REFI"); + config.memSpec.tDQSCK = clk * queryUIntParameter(timings, "DQSCK"); + + config.memSpec.refreshTimings.clear(); + for (unsigned int i = 0; i < config.memSpec.NumberOfBanks; ++i) + { + config.memSpec.refreshTimings[Bank(i)] = RefreshTiming(config.memSpec.tRFC, config.memSpec.tREFI); + } + + // Currents and Volatages: TODO Check if this is correct. + XMLElement* powers = memspec->FirstChildElement("mempowerspec"); + config.memSpec.iDD0 = queryDoubleParameter(powers, "idd0"); + config.memSpec.iDD02 = queryDoubleParameter(powers, "idd0"); + config.memSpec.iDD2P0 = queryDoubleParameter(powers, "idd2p0"); + config.memSpec.iDD2P1 = queryDoubleParameter(powers, "idd2p1"); + config.memSpec.iDD2N = queryDoubleParameter(powers, "idd2n"); + config.memSpec.iDD3P0 = queryDoubleParameter(powers, "idd3p0"); + config.memSpec.iDD3P1 = queryDoubleParameter(powers, "idd3p1"); + config.memSpec.iDD3N = queryDoubleParameter(powers, "idd3n"); + config.memSpec.iDD4R = queryDoubleParameter(powers, "idd4r"); + config.memSpec.iDD4W = queryDoubleParameter(powers, "idd4w"); + config.memSpec.iDD5 = queryDoubleParameter(powers, "idd5"); + config.memSpec.iDD6 = queryDoubleParameter(powers, "idd6"); + config.memSpec.iDD62 = queryDoubleParameter(powers, "idd6"); + config.memSpec.vDD = queryDoubleParameter(powers, "vdd"); + config.memSpec.vDD2 = queryDoubleParameter(powers, "vdd"); +} + + void ConfigurationLoader::loadDDR4(Configuration& config, XMLElement* memspec) { //MemArchitecture diff --git a/DRAMSys/simulator/src/controller/core/configuration/ConfigurationLoader.h b/DRAMSys/simulator/src/controller/core/configuration/ConfigurationLoader.h index 0f0fb2e0..12b30667 100644 --- a/DRAMSys/simulator/src/controller/core/configuration/ConfigurationLoader.h +++ b/DRAMSys/simulator/src/controller/core/configuration/ConfigurationLoader.h @@ -58,6 +58,7 @@ private: static void loadConfig(Configuration& config, tinyxml2::XMLElement* configNode); //specific loader + static void loadDDR3(Configuration& config, tinyxml2::XMLElement* memspec); static void loadDDR4(Configuration& config, tinyxml2::XMLElement* memspec); static void loadWideIO(Configuration& config, tinyxml2::XMLElement* memspec); };