diff --git a/README.md b/README.md index 4eabcd46..59e654e9 100644 --- a/README.md +++ b/README.md @@ -3,21 +3,9 @@ de.uni-kl.ems.dram.vp.system Generic DRAM controller -#Setup with Eclipse +#Setup with QTCreator -1. Start Eclipse ($eclipse) -2. -> Import - -> Git - -> Projects from Git - -> Existing Local Repository - -> Add Path to $dram.vp.system - -> Import Existing Projects - -> Finish - -3. Configure Eclipse: - -> Run Configurations - -> Environment - -> Variable: LD_LIBRARY_PATH = /opt/systemc/lib-linux64/:/opt/gcc/lib64 +needs update! diff --git a/dram/dramSys/dramSys.pro b/dram/dramSys/dramSys.pro index 6e5bbe27..e8e8ffa7 100644 --- a/dram/dramSys/dramSys.pro +++ b/dram/dramSys/dramSys.pro @@ -70,7 +70,6 @@ SOURCES += \ HEADERS += \ ../src/common/third_party/tinyxml2.h \ - ../src/common/xmlConfig.h \ ../src/common/xmlAddressdecoder.h \ ../src/common/Utils.h \ ../src/common/TlmRecorder.h \ diff --git a/dram/resources/configs/memconfigs/fifo.xml b/dram/resources/configs/memconfigs/fifo.xml index 603049f2..2e23e330 100644 --- a/dram/resources/configs/memconfigs/fifo.xml +++ b/dram/resources/configs/memconfigs/fifo.xml @@ -1,6 +1,6 @@ - + diff --git a/dram/resources/scripts/metrics.py b/dram/resources/scripts/metrics.py index 7f780cca..8f448db1 100644 --- a/dram/resources/scripts/metrics.py +++ b/dram/resources/scripts/metrics.py @@ -38,17 +38,17 @@ def getClock(connection): result = cursor.fetchone() return result[0] -@metric -def latency_histogram(connection): - cursor = connection.cursor() - cursor.execute("SELECT ((p2.PhaseEnd - p1.PhaseEnd)/1000) FROM Transactions t, Phases p1, Phases p2 WHERE t.id = p1.Transact and t.id = p2.Transact and p1.PhaseName = \"REQ\" and p2.PhaseName = \"RESP\" ") - result = cursor.fetchall() - #result.sort() - #print(max(result)[0]) - import matplotlib.pyplot as plt - plt.hist(result, bins=max(result)[0], histtype='barstacked') - plt.savefig('hist.png') - return "Saved as hist.png" +#@metric +#def latency_histogram(connection): +# cursor = connection.cursor() +# cursor.execute("SELECT ((p2.PhaseEnd - p1.PhaseEnd)/1000) FROM Transactions t, Phases p1, Phases p2 WHERE t.id = p1.Transact and t.id = p2.Transact and p1.PhaseName = \"REQ\" and p2.PhaseName = \"RESP\" ") +# result = cursor.fetchall() +# #result.sort() +# #print(max(result)[0]) +# import matplotlib.pyplot as plt +# plt.hist(result, bins=max(result)[0], histtype='barstacked') +# plt.savefig('hist.png') +# return "Saved as hist.png" @metric def average_response_latency_in_ns(connection): @@ -59,6 +59,17 @@ def average_response_latency_in_ns(connection): result = cursor.fetchone() return round(result[0],1) +@metric +def memory_utilisation(connection): + cursor = connection.cursor() + cursor.execute(""" SELECT sum(DataStrobeEnd - DataStrobeBegin) FROM transactions """) + active = cursor.fetchone() + cursor = connection.cursor() + cursor.execute(""" SELECT max(DataStrobeEnd) FROM Transactions """) + total = cursor.fetchone() + return str(active[0]/total[0]*100)+"%" + + def refreshMissDecision(connection,calculatedMetrics): cursor = connection.cursor() cursor.execute("""SELECT phases.ID,PhaseBegin,PhaseEnd,TBank FROM Phases INNER JOIN transactions on transactions.id = phases.transact WHERE PhaseName='AUTO_REFRESH' """) diff --git a/dram/src/common/protocol.h b/dram/src/common/protocol.h index 8cebad64..a9c1ae57 100755 --- a/dram/src/common/protocol.h +++ b/dram/src/common/protocol.h @@ -41,6 +41,16 @@ DECLARE_EXTENDED_PHASE(END_PDNA); DECLARE_EXTENDED_PHASE(BEGIN_SREF); DECLARE_EXTENDED_PHASE(END_SREF); +// Phases for Power Down Bankwise +DECLARE_EXTENDED_PHASE(BEGIN_PDNPB); +DECLARE_EXTENDED_PHASE(END_PDNPB); + +DECLARE_EXTENDED_PHASE(BEGIN_PDNAB); +DECLARE_EXTENDED_PHASE(END_PDNAB); + +DECLARE_EXTENDED_PHASE(BEGIN_SREFB); +DECLARE_EXTENDED_PHASE(END_SREFB); + //Triggers DECLARE_EXTENDED_PHASE(REF_TRIGGER); diff --git a/dram/src/common/xmlConfig.h b/dram/src/common/xmlConfig.h deleted file mode 100755 index 110dd2aa..00000000 --- a/dram/src/common/xmlConfig.h +++ /dev/null @@ -1,97 +0,0 @@ -#ifndef CONFIH_H -#define CONFIH_H - -#include -#include - -using namespace std; - -class xmlConfig -{ - public: - - sc_time clk; - sc_time tRRD; - sc_time tRC; - sc_time tRCD; - sc_time tBL; - sc_time tRL; - sc_time tWL; - sc_time tWTR; - sc_time tRP; - sc_time tRAS; - sc_time tWR; - sc_time tREF; - sc_time tRFC; - sc_time tXP; - sc_time tCKE; - sc_time tXSR; - sc_time tCKESR; - sc_time tREFA; - sc_time tREFB; - sc_time tPDNTO; - - double IDD0; - double IDD2N; - double IDD3N; - double IDD4R; - double IDD4W; - double IDD5; - double IDD6; - double IDD5B1; - double IDD2P; - double IDD3P; - double VDD; - - sc_time ccPreprocessingTime; - - public: - xmlConfig() - { - //clk = sc_time(6.0, SC_NS); // 166MHz - clk = sc_time(6, SC_NS); // 166MHz - - // Timings: - // WC timings for 200MHz - // before thermal: - tRRD = 2 * clk; // 2 * clk; // 4 * clk;//1 * clk; //2 * clk; - tRCD = 3 * clk; // 2 * clk; // 10 * clk;//3 * clk; //4 * clk; - tRL = 3 * clk; // 3 * clk; // 10 * clk;//3 * clk; //3 * clk; - tBL = 1 * clk; // 1 * clk; // 1 * clk;//1 * clk; //1 * clk; - tWL = 1 * clk; // 1 * clk; // 9 * clk;//1 * clk; //1 * clk; - tWTR = 3 * clk; // 3 * clk; // 4 * clk;//3 * clk; //3 * clk; - tRP = 3 * clk; // 3 * clk; // 10 * clk;//3 * clk; //4 * clk; // sadri changed from 2 to 3 = 18ns/6ns - tRAS = 6 * clk; // 5 * clk; // 18 * clk;//8 * clk; //9 * clk; - tWR = 2 * clk; // 2 * clk; // 10 * clk;//2 * clk; //3 * clk; - tRFC = 18 * clk; // 22 * clk; // 15 * clk; // 110* clk;//18 * clk; // sadri changed from 15 to 22 = 130ns/6ns - tXP = 2 * clk; - tCKE = 3 * clk; - tXSR = tRFC + 2 * clk; - tCKESR = 3 * clk; - tPDNTO = 0 * clk; - tRC = tRP + tRAS; - tREF = sc_time(64, SC_MS); - tREFA = tRP + tRFC; - tREFB = tRP + tRC; // refresh for one bank - - // Power realted currents and voltages: - // 166MHz thermal non minimal timings (200MHz) - // 166MHz with minimal timing - IDD0 = 37.85 / 1000.0; // 47.3 / 1000.0; //64 / 1000.0; - IDD2N = 4.36 / 1000.0; // 4.36 / 1000.0; //4.4 / 1000.0; - IDD3N = 5.60 / 1000.0; // 6.07 / 1000.0; //5.9 / 1000.0; - IDD4R = 94.64 / 1000.0; // 94.65 / 1000.0; //94 / 1000.0; - IDD4W = 88.65 / 1000.0; // 88.66 / 1000.0; //88 / 1000.0; - IDD5 = 136.20 / 1000.0; // 162.56 / 1000.0; //163 / 1000.0; - IDD5B1 = 37.32 / 1000.0; // - IDD2P = 2.4 / 1000.0; // - IDD3P = 3.6 / 1000.0; // - IDD6 = 3.4 / 1000.0; // - - VDD = 1.2; - - ccPreprocessingTime = 1 * clk; - } -}; - -#endif diff --git a/dram/src/simulation/Dram.h b/dram/src/simulation/Dram.h index 0770e22a..7049ea86 100644 --- a/dram/src/simulation/Dram.h +++ b/dram/src/simulation/Dram.h @@ -40,9 +40,8 @@ struct Dram: sc_module { tSocket.register_nb_transport_fw(this, &Dram::nb_transport_fw); -// MemorySpecification memSpec(MemSpecParser::getMemSpecFromXML(Configuration::getInstance().memspecUri)); -// MemorySpecification::getMemSpecFromXML(Configuration::getInstance().memspecUri)); -// DRAMPower = new libDRAMPower( memSpec, 1,1,1,0,0 ); + //MemorySpecification memSpec(MemSpecParser::getMemSpecFromXML(Configuration::getInstance().memspecUri)); + //DRAMPower = new libDRAMPower( memSpec, 0 ); } ~Dram()