From eb720d5aa61482c96d16876a0878e5a1d6f1838f Mon Sep 17 00:00:00 2001
From: Lukas Steiner <lsteiner@rhrk.uni-kl.de>
Date: Tue, 25 Aug 2020 10:18:10 +0200
Subject: [PATCH] Add DDR5 example.

---
 .../am_ddr5_2x8x8x8Gbx4_dimm_p1KB_rbc.json    | 55 ++++++++++++++++
 .../JEDEC_2x8x8x8Gb_DDR5-3200A_4bit.json      | 66 +++++++++++++++++++
 .../resources/simulations/ddr5-example.json   |  6 +-
 3 files changed, 124 insertions(+), 3 deletions(-)
 create mode 100644 DRAMSys/library/resources/configs/amconfigs/am_ddr5_2x8x8x8Gbx4_dimm_p1KB_rbc.json
 create mode 100644 DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x8x8Gb_DDR5-3200A_4bit.json

diff --git a/DRAMSys/library/resources/configs/amconfigs/am_ddr5_2x8x8x8Gbx4_dimm_p1KB_rbc.json b/DRAMSys/library/resources/configs/amconfigs/am_ddr5_2x8x8x8Gbx4_dimm_p1KB_rbc.json
new file mode 100644
index 00000000..48f1301d
--- /dev/null
+++ b/DRAMSys/library/resources/configs/amconfigs/am_ddr5_2x8x8x8Gbx4_dimm_p1KB_rbc.json
@@ -0,0 +1,55 @@
+{
+    "CONGEN": {
+        "BYTE_BIT": [
+            0,
+            1
+        ],
+        "COLUMN_BIT": [
+            2,
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9,
+            10,
+            11,
+            12
+        ],
+        "BANKGROUP_BIT": [
+            13,
+            14,
+            15
+        ],
+        "BANK_BIT": [
+            16
+        ],
+        "ROW_BIT": [
+            17,
+            18,
+            19,
+            20,
+            21,
+            22,
+            23,
+            24,
+            25,
+            26,
+            27,
+            28,
+            29,
+            30,
+            31,
+            32
+        ],
+        "RANK_BIT": [
+            33,
+            34,
+            35
+        ],
+        "CHANNEL_BIT": [
+            36
+        ]
+    }
+}
\ No newline at end of file
diff --git a/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x8x8Gb_DDR5-3200A_4bit.json b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x8x8Gb_DDR5-3200A_4bit.json
new file mode 100644
index 00000000..95e2e703
--- /dev/null
+++ b/DRAMSys/library/resources/configs/memspecs/JEDEC_2x8x8x8Gb_DDR5-3200A_4bit.json
@@ -0,0 +1,66 @@
+{
+    "memspec": {
+        "memarchitecturespec": {
+            "burstLength": 16,
+            "dataRate": 2,
+            "nbrOfBankGroups": 8,
+            "nbrOfBanks": 16,
+            "nbrOfColumns": 2048,
+            "nbrOfRanks": 8,
+            "nbrOfDIMMRanks": 2,
+            "nbrOfPhysicalRanks": 2,
+            "nbrOfLogicalRanks": 2,
+            "nbrOfRows": 65536,
+            "width": 4,
+            "nbrOfDevicesOnDIMM": 8,
+            "nbrOfChannels": 2
+        },
+        "memoryId": "JEDEC_2x8x8x8Gbx4_DDR5-3200A_4bit",
+        "memoryType": "DDR5",
+        "memtimingspec": {
+            "RCD": 22,
+            "PPD": 2,
+            "RP": 22,
+            "RAS": 52,
+            "RL": 22,
+            "RTP": 12,
+            "RPRE": 1,
+            "RPST": 0,
+            "RDDQS": 0,
+            "WL": 20,
+            "WPRE": 2,
+            "WPST": 0,
+            "WR": 48,
+            "CCD_L_slr": 8, 
+            "CCD_L_WR_slr": 32,
+            "CCD_S_slr": 8,
+            "CCD_S_WR_slr": 8,
+            "CCD_dlr": 8,    
+            "CCD_WR_dlr": 8, 
+            "CCD_WR_dpr": 8,  
+            "RRD_L_slr": 8,
+            "RRD_S_slr": 8, 
+            "RRD_dlr": 4,    
+            "FAW_slr": 32,    
+            "FAW_dlr": 16,    
+            "WTR_L": 16,      
+            "WTR_S": 4,      
+            "RFC_slr": 312,    
+            "RFC_dlr": 104,    
+            "RFC_dpr": 104,    
+            "RFCsb_slr": 184,  
+            "RFCsb_dlr": 62,  
+            "REFI": 6240,   
+            "REFSBRD_slr": 48, 
+            "REFSBRD_dlr": 24,
+            "RTRS": 2,        
+            "CPDED": 8,      
+            "PD": 12,         
+            "XP": 12,         
+            "ACTPDEN": 2,    
+            "PRPDEN": 2,     
+            "REFPDEN": 2,
+            "clkMhz": 1600
+        }
+    }
+}
diff --git a/DRAMSys/library/resources/simulations/ddr5-example.json b/DRAMSys/library/resources/simulations/ddr5-example.json
index b0052ec5..8c36a540 100644
--- a/DRAMSys/library/resources/simulations/ddr5-example.json
+++ b/DRAMSys/library/resources/simulations/ddr5-example.json
@@ -1,14 +1,14 @@
 {
     "simulation": {
-        "addressmapping": "am_ddr5_2x4x8Gbx8_dimm_p1KB_rbc.json",
+        "addressmapping": "am_ddr5_2x8x8x8Gbx4_dimm_p1KB_rbc.json",
         "mcconfig": "fr_fcfs.json",
-        "memspec": "JEDEC_2x8Gb_DDR5-3200A_8bit.json",
+        "memspec": "JEDEC_2x8x8x8Gb_DDR5-3200A_4bit.json",
         "simconfig": "ddr5.json",
         "simulationid": "ddr5-example",
         "thermalconfig": "config.json",
         "tracesetup": [
             {
-                "clkMhz": 200,
+                "clkMhz": 2000,
                 "name": "ddr3_example.stl"
             }
         ]