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Éder F. Zulian
2018-08-30 13:40:56 +02:00
parent 332c0d925c
commit e8bdd28bc6
1 changed files with 13 additions and 11 deletions
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README.md
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@@ -1475,7 +1475,7 @@ GEM5=/path/to/gem5/
Optionally, export environment variables in your **~/.bashrc** file or Optionally, export environment variables in your **~/.bashrc** file or
equivalent and open a new terminal: equivalent and open a new terminal:
``` ```bash
# In this example gem5 is located at $HOME/gem5 (that is your home folder). # In this example gem5 is located at $HOME/gem5 (that is your home folder).
# Modify the variable to use the correct location. # Modify the variable to use the correct location.
export GEM5=$HOME/gem5 export GEM5=$HOME/gem5
@@ -1524,16 +1524,18 @@ cd gem5/utils/tlm/
../../build/ARM/gem5.opt conf/tlm_slave.py ../../build/ARM/gem5.opt conf/tlm_slave.py
``` ```
The message Ignore the message below.
``` ```
"fatal: Can't find port handler type 'tlm_slave'" "fatal: Can't find port handler type 'tlm_slave'"
``` ```
is totally okay. The configuration file config.ini will be stored in the m5out/
directory. Copy this configuration file to the building directory of DRAMSys: The configuration file config.ini will be stored in the **m5out** directory.
Copy this configuration file to the building directory of DRAMSys:
``` ```
dram.vp.system/build-DRAMSys-Desktop_Qt_5_7_0_clang_64bit-Debug/gem5 dram.vp.system/build-DRAMSys-Desktop_Qt_5_7_0_clang_64bit-Debug/gem5
``` ```
Also the traffic generatior configuration file (conf/tgen.cfg) must be stored Also the traffic generatior configuration file (conf/tgen.cfg) must be stored
in a conf directory of this building directory. in a conf directory of this building directory.
@@ -1575,20 +1577,20 @@ Command template for generating **.ini** configuration files follows:
```bash ```bash
build/ARM/gem5.opt configs/example/se.py \ build/ARM/gem5.opt configs/example/se.py \
-c <application> --mem-size=512MB --mem-channels=1 \ -c <application> --mem-size=512MB --mem-channels=1 \
--caches --l2cache --mem-type=SimpleMemory \ --caches --l2cache --mem-type=SimpleMemory \
--cpu-type=TimingSimpleCPU --num-cpu=1 \ --cpu-type=TimingSimpleCPU --num-cpu=1 \
--tlm-memory=transactor --tlm-memory=transactor
``` ```
An overview of the architcture being simulated is presented below: An overview of the architcture being simulated is presented below:
![arch](DRAMSys/docs/images/gem5_se_mode_arch.svg) ![arch](DRAMSys/docs/images/gem5_se_mode_arch.png)
Note: this is a gem5 generated file, therefore DRAMSys is omitted. DRAMSys is **Note**: this is a gem5 generated file, therefore DRAMSys is omitted. DRAMSys is
direct connected as external tlm slave. direct connected as external tlm slave.
Note: workaround in se.py required: **Note**: workaround in se.py required:
```python ```python
... ...