From e6051ac9673ecbdb5792fd7d48b432d5792f0729 Mon Sep 17 00:00:00 2001 From: Matthias Jung Date: Sat, 1 Aug 2015 11:17:30 +0200 Subject: [PATCH] Bit flipping for independent cells is now implemented --- DRAMSys/dramSys/src/error/errormodel.cpp | 112 ++++++++++++++++++++++- DRAMSys/dramSys/src/error/errormodel.h | 18 +++- 2 files changed, 126 insertions(+), 4 deletions(-) diff --git a/DRAMSys/dramSys/src/error/errormodel.cpp b/DRAMSys/dramSys/src/error/errormodel.cpp index aa33ec94..31f7f7f8 100644 --- a/DRAMSys/dramSys/src/error/errormodel.cpp +++ b/DRAMSys/dramSys/src/error/errormodel.cpp @@ -45,6 +45,7 @@ errorModel::errorModel(const char * name) numberOfColumns = Configuration::getInstance().memSpec.NumberOfColumns; bytesPerColumn = xmlAddressDecoder::getInstance().amount["bytes"]; numberOfRows = Configuration::getInstance().memSpec.NumberOfRows; + numberOfBitErrorEvents = 0; // Initialize the lastRow Access array: lastRowAccess = new sc_time[numberOfRows]; @@ -86,6 +87,9 @@ void errorModel::store(tlm::tlm_generic_payload &trans) // Get the key for the dataMap from the transaction's address: DecodedAddress key = xmlAddressDecoder::getInstance().decodeAddress(trans.get_address()); + // Set context: + setContext(key); + // Check if the provided data length is correct: assert((bytesPerColumn * burstLenght) == trans.get_data_length()); @@ -140,6 +144,9 @@ void errorModel::load(tlm::tlm_generic_payload &trans) // Get the key for the dataMap from the transaction's address: DecodedAddress key = xmlAddressDecoder::getInstance().decodeAddress(trans.get_address()); + // Set context: + setContext(key); + // Check if the provided data length is correct: assert((bytesPerColumn * burstLenght) == trans.get_data_length()); @@ -172,7 +179,97 @@ void errorModel::refresh(unsigned int row) void errorModel::activate(unsigned int row) { - // TODO + // The Activate command is responsible that an retention error is manifested. + + // Get the time interval between now and the last acivate/refresh + sc_time interval = sc_time_stamp() - lastRowAccess[row]; + + // Obtain the number of bit flips for the current temperature and the time interval: + unsigned int n = getNumberOfFlips(temperature, interval); + + // Mark the the first n Bits in the list of weak cells as flipped: + for (unsigned int i=0; i0 transitions are supported) + // DRAMs based on anti cells are not supported yet by this model + if(getBit(key,byte,bitInByte) == 1) + { + // Prepare bit mask: invert mask and AND it later + unsigned char mask = pow(2, bitInByte); + mask = ~mask; + + // Temporal storage for modification: + unsigned char tempByte; + + if(weakCells[i].dependent == false) + { + // Load the affected byte to tempByte + memcpy(&tempByte, dataMap[key]+byte, 1); + + // Flip the bit: + tempByte = (tempByte & mask); + + // Copy the modified byte back to the dataMap: + memcpy(dataMap[key]+byte, &tempByte, 1); + } + else // if(weakCells[i].dependent == true) + { + // TODO: dependet + } + } + } + } + + lastRowAccess[row] = sc_time_stamp(); +} + +unsigned int errorModel::getBit(DecodedAddress key, unsigned int byte, unsigned int bitInByte) +{ + // TODO: corner cases + + // If the data was not writte by the produce yet it is zero: + if(dataMap.count(key) == 0) + { + return 0; + } + else // Return the value of the bit + { + unsigned char tempByte; + + // Copy affected byte to a temporal variable: + memcpy(&tempByte, dataMap[key]+byte, 1); + unsigned char mask = pow(2, bitInByte); + return (byte & mask) >> bitInByte; + } } void errorModel::setTemperature(double t) @@ -435,4 +532,15 @@ unsigned int errorModel::getNumberOfFlips(double temp, sc_time time) } } - +void errorModel::setContext(DecodedAddress addr) +{ + // This function is called the first store ore load to get the context in + // which channel, rank or bank the error model is used. + if(myChannel == -1 && myBank == -1 && myBankgroup == -1 && myRank == -1 ) + { + myChannel = addr.channel; + myBank = addr.bank; + myBankgroup = addr.bankgroup; + myRank = addr.rank; + } +} diff --git a/DRAMSys/dramSys/src/error/errormodel.h b/DRAMSys/dramSys/src/error/errormodel.h index 512c90f1..7bba9022 100644 --- a/DRAMSys/dramSys/src/error/errormodel.h +++ b/DRAMSys/dramSys/src/error/errormodel.h @@ -52,7 +52,6 @@ class errorModel void refresh(unsigned int row); void activate(unsigned int row); void setTemperature(double t); - unsigned int getNumberOfFlips(double temp, sc_time time); private: // Configuration Parameters: @@ -68,9 +67,14 @@ class errorModel // Online Parameters: double temperature; - // Input data related things: + // Private Methods: void parseInputData(); void prepareWeakCells(); + unsigned int getNumberOfFlips(double temp, sc_time time); + void setContext(DecodedAddress addr); + unsigned int getBit(DecodedAddress key, unsigned int byte, unsigned int bitInByte); + + // Input related data structures: struct errors { @@ -109,10 +113,20 @@ class errorModel return addrFirst < addrSecond; } }; + + // The data structure stores complete column accesses + // A DRAM burst will be splitted up in several column accesses + // e.g. BL=4 means that 4 elements will be added to the dataMap! std::map dataMap; // An array to save when the last ACT/REF to a row happened: sc_time * lastRowAccess; + + // Context Variables (will be written by the first dram access) + int myChannel; + int myRank; + int myBankgroup; + int myBank; }; #endif // ERRORMODEL_H