derek/DRAMSys
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changed stuff, refresh aware

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robert
2014-04-09 13:54:37 +02:00
parent 339dfbbdbb
commit e51deb97ec
17 changed files with 106 additions and 56 deletions
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20
dram/src/simulation/main.cpp
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@@ -30,16 +30,24 @@ int sc_main(int argc, char **argv)
sc_set_time_resolution(1, SC_PS);
Configuration::memspecUri = "/home/jonny/git/dram/dram/resources/configs/memspecs/MatzesWideIO.xml";
Configuration::memconfigUri = "/home/jonny/git/dram/dram/resources/configs/memconfigs/memconfig.xml";
string resources = pathOfFile(argv[0]) + string("/../resources/");
string memconfig = "memconfig.xml";
string memspec = "MatzesWideIO.xml";
string stl1 = "chstone-sha_32.stl";
unsigned int burstlength1 = 4;
string stl2 = "empty.stl";
unsigned int burstlength2 = 2;
string traceName = "tpr.tdb";
SimulationManager simulationManager("sim", stl1,burstlength1, stl2,burstlength2, traceName, resources,false);
string stl2 = "mediabench-h263decode_32.stl";
unsigned int burstlength2 = 4;
string traceName = "unaware_long.tdb";
Configuration::memspecUri = "/home/robert/git/dram/dram/resources/configs/memspecs/MatzesWideIO.xml";
Configuration::memconfigUri = "/home/robert/git/dram/dram/resources/configs/memconfigs/memconfig.xml";
// Configuration::memconfigUri = resources + string("configs/memconfigs/") + memconfig;
// Configuration::memconfigUri = resources + string("configs/memspecs/") + memspec;
SimulationManager simulationManager("sim",memconfig,memspec,stl1,burstlength1, stl2,burstlength2, traceName, resources,false);
simulationManager.startSimulation();
startTraceAnalyzer(traceName);
return 0;