From e38d0aae1f08fa4bb4ed05621de15803251c7ebe Mon Sep 17 00:00:00 2001 From: Lukas Steiner Date: Wed, 5 May 2021 17:10:08 +0200 Subject: [PATCH] Introduce burst length parameter. --- DRAMSys/library/src/common/dramExtensions.cpp | 12 +++++++++++- DRAMSys/library/src/common/dramExtensions.h | 4 +++- DRAMSys/library/src/controller/BankMachine.cpp | 12 ++++++++---- DRAMSys/library/src/controller/Controller.cpp | 3 ++- .../library/src/controller/checker/CheckerDDR3.cpp | 4 ++-- DRAMSys/library/src/controller/checker/CheckerDDR3.h | 5 +++-- .../library/src/controller/checker/CheckerDDR4.cpp | 4 ++-- DRAMSys/library/src/controller/checker/CheckerDDR4.h | 5 +++-- .../library/src/controller/checker/CheckerDDR5.cpp | 4 ++-- DRAMSys/library/src/controller/checker/CheckerDDR5.h | 7 +++++-- .../library/src/controller/checker/CheckerGDDR5.cpp | 4 ++-- .../library/src/controller/checker/CheckerGDDR5.h | 5 +++-- .../library/src/controller/checker/CheckerGDDR5X.cpp | 4 ++-- .../library/src/controller/checker/CheckerGDDR5X.h | 5 +++-- .../library/src/controller/checker/CheckerGDDR6.cpp | 4 ++-- .../library/src/controller/checker/CheckerGDDR6.h | 5 +++-- .../library/src/controller/checker/CheckerHBM2.cpp | 4 ++-- DRAMSys/library/src/controller/checker/CheckerHBM2.h | 5 +++-- DRAMSys/library/src/controller/checker/CheckerIF.h | 5 +++-- .../library/src/controller/checker/CheckerLPDDR4.cpp | 4 ++-- .../library/src/controller/checker/CheckerLPDDR4.h | 5 +++-- .../library/src/controller/checker/CheckerWideIO.cpp | 4 ++-- .../library/src/controller/checker/CheckerWideIO.h | 5 +++-- .../src/controller/checker/CheckerWideIO2.cpp | 4 ++-- .../library/src/controller/checker/CheckerWideIO2.h | 5 +++-- DRAMSys/library/src/simulation/Arbiter.cpp | 4 +++- DRAMSys/library/src/simulation/Arbiter.h | 2 ++ 27 files changed, 84 insertions(+), 50 deletions(-) diff --git a/DRAMSys/library/src/common/dramExtensions.cpp b/DRAMSys/library/src/common/dramExtensions.cpp index 09a49be9..6104bcf4 100644 --- a/DRAMSys/library/src/common/dramExtensions.cpp +++ b/DRAMSys/library/src/common/dramExtensions.cpp @@ -194,6 +194,16 @@ Column DramExtension::getColumn(const tlm_generic_payload &payload) return DramExtension::getColumn(&payload); } +unsigned DramExtension::getBurstLength(const tlm_generic_payload *payload) +{ + return DramExtension::getExtension(payload).getBurstLength(); +} + +unsigned DramExtension::getBurstLength(const tlm_generic_payload &payload) +{ + return DramExtension::getBurstLength(&payload); +} + uint64_t DramExtension::getThreadPayloadID(const tlm_generic_payload *payload) { return DramExtension::getExtension(payload).getThreadPayloadID(); @@ -268,7 +278,7 @@ Column DramExtension::getColumn() const return column; } -unsigned int DramExtension::getBurstlength() const +unsigned int DramExtension::getBurstLength() const { return burstlength; } diff --git a/DRAMSys/library/src/common/dramExtensions.h b/DRAMSys/library/src/common/dramExtensions.h index 989bb079..896a95a8 100644 --- a/DRAMSys/library/src/common/dramExtensions.h +++ b/DRAMSys/library/src/common/dramExtensions.h @@ -205,6 +205,8 @@ public: static Row getRow(const tlm::tlm_generic_payload &payload); static Column getColumn(const tlm::tlm_generic_payload *payload); static Column getColumn(const tlm::tlm_generic_payload &payload); + static unsigned getBurstLength(const tlm::tlm_generic_payload *payload); + static unsigned getBurstLength(const tlm::tlm_generic_payload &payload); static uint64_t getThreadPayloadID(const tlm::tlm_generic_payload *payload); static uint64_t getThreadPayloadID(const tlm::tlm_generic_payload &payload); static uint64_t getChannelPayloadID(const tlm::tlm_generic_payload *payload); @@ -218,7 +220,7 @@ public: Row getRow() const; Column getColumn() const; - unsigned int getBurstlength() const; + unsigned int getBurstLength() const; uint64_t getThreadPayloadID() const; uint64_t getChannelPayloadID() const; void incrementRow(); diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp index 0fab68d9..4fdecbb1 100644 --- a/DRAMSys/library/src/controller/BankMachine.cpp +++ b/DRAMSys/library/src/controller/BankMachine.cpp @@ -148,7 +148,8 @@ sc_time BankMachineOpen::start() else // row miss nextCommand = Command::PRE; } - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, + bankgroup, bank, DramExtension::getBurstLength(currentPayload)); } } return timeToSchedule; @@ -178,7 +179,8 @@ sc_time BankMachineClosed::start() else SC_REPORT_FATAL("BankMachine", "Wrong TLM command"); } - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, + bankgroup, bank, DramExtension::getBurstLength(currentPayload)); } } return timeToSchedule; @@ -225,7 +227,8 @@ sc_time BankMachineOpenAdaptive::start() else // row miss nextCommand = Command::PRE; } - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, + bankgroup, bank, DramExtension::getBurstLength(currentPayload)); } } return timeToSchedule; @@ -272,7 +275,8 @@ sc_time BankMachineClosedAdaptive::start() else // row miss, should never happen SC_REPORT_FATAL("BankMachine", "Should never be reached for this policy"); } - timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, bankgroup, bank); + timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, rank, + bankgroup, bank, DramExtension::getBurstLength(currentPayload)); } } return timeToSchedule; diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 21355bb1..af67bdae 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -287,6 +287,7 @@ void Controller::controllerMethod() Rank rank = DramExtension::getRank(payload); BankGroup bankgroup = DramExtension::getBankGroup(payload); Bank bank = DramExtension::getBank(payload); + unsigned burstLength = DramExtension::getBurstLength(payload); if (isRankCommand(command)) { @@ -304,7 +305,7 @@ void Controller::controllerMethod() refreshManagers[rank.ID()]->updateState(command); powerDownManagers[rank.ID()]->updateState(command); - checker->insert(command, rank, bankgroup, bank); + checker->insert(command, rank, bankgroup, bank, burstLength); if (isCasCommand(command)) { diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp index 1e48ea04..0d52b904 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.cpp @@ -60,7 +60,7 @@ CheckerDDR3::CheckerDDR3() tWRAPDEN = memSpec->tWL + tBURST + memSpec->tWR + memSpec->tCK; } -sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const +sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank, unsigned) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -412,7 +412,7 @@ sc_time CheckerDDR3::timeToSatisfyConstraints(Command command, Rank rank, BankGr return earliestTimeToStart; } -void CheckerDDR3::insert(Command command, Rank rank, BankGroup, Bank bank) +void CheckerDDR3::insert(Command command, Rank rank, BankGroup, Bank bank, unsigned) { PRINTDEBUGMESSAGE("CheckerDDR3", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR3.h b/DRAMSys/library/src/controller/checker/CheckerDDR3.h index efce001a..1eed6b48 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR3.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR3.h @@ -45,8 +45,9 @@ class CheckerDDR3 final : public CheckerIF { public: CheckerDDR3(); - virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; - virtual void insert(Command, Rank, BankGroup, Bank) override; + virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), + BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; + virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; private: const MemSpecDDR3 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp index 1dad1943..25544d7b 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.cpp @@ -63,7 +63,7 @@ CheckerDDR4::CheckerDDR4() tWRAPDEN = memSpec->tWL + tBURST + memSpec->tCK + memSpec->tWR; } -sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const +sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -443,7 +443,7 @@ sc_time CheckerDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGr return earliestTimeToStart; } -void CheckerDDR4::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) +void CheckerDDR4::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) { PRINTDEBUGMESSAGE("CheckerDDR4", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR4.h b/DRAMSys/library/src/controller/checker/CheckerDDR4.h index 694eecd4..d2befee3 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR4.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR4.h @@ -45,8 +45,9 @@ class CheckerDDR4 final : public CheckerIF { public: CheckerDDR4(); - virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; - virtual void insert(Command, Rank, BankGroup, Bank) override; + virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), + BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; + virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; private: const MemSpecDDR4 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp index a5458a3d..1de608a8 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerDDR5.cpp @@ -89,7 +89,7 @@ CheckerDDR5::CheckerDDR5() // TODO: tRTP BL 32 (similar to LPDDR4) } -sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const +sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned burstLength) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -547,7 +547,7 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGr return earliestTimeToStart; } -void CheckerDDR5::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) +void CheckerDDR5::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) { PRINTDEBUGMESSAGE("CheckerDDR5", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerDDR5.h b/DRAMSys/library/src/controller/checker/CheckerDDR5.h index caf04154..7bd2f4ad 100644 --- a/DRAMSys/library/src/controller/checker/CheckerDDR5.h +++ b/DRAMSys/library/src/controller/checker/CheckerDDR5.h @@ -45,8 +45,9 @@ class CheckerDDR5 final : public CheckerIF { public: CheckerDDR5(); - virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; - virtual void insert(Command, Rank, BankGroup, Bank) override; + virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), + BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; + virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; private: const MemSpecDDR5 *memSpec; @@ -64,6 +65,8 @@ private: std::vector> last4ActivatesPhysical; std::vector> last4ActivatesLogical; + // TODO: store BL of last RD and WR globally or for each hierarchy? + sc_time cmdOffset; sc_time tRD_BURST; diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp index fe5fc00d..a32251f1 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5.cpp @@ -64,7 +64,7 @@ CheckerGDDR5::CheckerGDDR5() tWRPRE = memSpec->tWL + tBURST + memSpec->tWR; } -sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const +sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -525,7 +525,7 @@ sc_time CheckerGDDR5::timeToSatisfyConstraints(Command command, Rank rank, BankG return earliestTimeToStart; } -void CheckerGDDR5::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) +void CheckerGDDR5::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) { PRINTDEBUGMESSAGE("CheckerGDDR5", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5.h b/DRAMSys/library/src/controller/checker/CheckerGDDR5.h index 326dae75..30ab9287 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5.h +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5.h @@ -45,8 +45,9 @@ class CheckerGDDR5 final : public CheckerIF { public: CheckerGDDR5(); - virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; - virtual void insert(Command, Rank, BankGroup, Bank) override; + virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), + BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; + virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; private: const MemSpecGDDR5 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp index bb5679a9..487184a0 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.cpp @@ -64,7 +64,7 @@ CheckerGDDR5X::CheckerGDDR5X() tWRPRE = memSpec->tWL + tBURST + memSpec->tWR; } -sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const +sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -525,7 +525,7 @@ sc_time CheckerGDDR5X::timeToSatisfyConstraints(Command command, Rank rank, Bank return earliestTimeToStart; } -void CheckerGDDR5X::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) +void CheckerGDDR5X::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) { PRINTDEBUGMESSAGE("CheckerGDDR5X", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h index 39138be3..652de82b 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR5X.h @@ -45,8 +45,9 @@ class CheckerGDDR5X final : public CheckerIF { public: CheckerGDDR5X(); - virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; - virtual void insert(Command, Rank, BankGroup, Bank) override; + virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), + BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; + virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; private: const MemSpecGDDR5X *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp index f0f6fa54..f50504e6 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR6.cpp @@ -63,7 +63,7 @@ CheckerGDDR6::CheckerGDDR6() tWRPRE = memSpec->tWL + tBURST + memSpec->tWR; } -sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const +sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -546,7 +546,7 @@ sc_time CheckerGDDR6::timeToSatisfyConstraints(Command command, Rank rank, BankG return earliestTimeToStart; } -void CheckerGDDR6::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) +void CheckerGDDR6::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) { PRINTDEBUGMESSAGE("CheckerGDDR6", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerGDDR6.h b/DRAMSys/library/src/controller/checker/CheckerGDDR6.h index 202bd8d3..edd78a7c 100644 --- a/DRAMSys/library/src/controller/checker/CheckerGDDR6.h +++ b/DRAMSys/library/src/controller/checker/CheckerGDDR6.h @@ -45,8 +45,9 @@ class CheckerGDDR6 final : public CheckerIF { public: CheckerGDDR6(); - virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; - virtual void insert(Command, Rank, BankGroup, Bank) override; + virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), + BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; + virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; private: const MemSpecGDDR6 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp index 4ed20f3f..7472d0ad 100644 --- a/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.cpp @@ -64,7 +64,7 @@ CheckerHBM2::CheckerHBM2() tWRRDL = memSpec->tWL + tBURST + memSpec->tWTRL; } -sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank) const +sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -500,7 +500,7 @@ sc_time CheckerHBM2::timeToSatisfyConstraints(Command command, Rank rank, BankGr return earliestTimeToStart; } -void CheckerHBM2::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank) +void CheckerHBM2::insert(Command command, Rank rank, BankGroup bankgroup, Bank bank, unsigned) { PRINTDEBUGMESSAGE("CheckerHBM2", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerHBM2.h b/DRAMSys/library/src/controller/checker/CheckerHBM2.h index 3578ee9b..a68a5f86 100644 --- a/DRAMSys/library/src/controller/checker/CheckerHBM2.h +++ b/DRAMSys/library/src/controller/checker/CheckerHBM2.h @@ -45,8 +45,9 @@ class CheckerHBM2 final : public CheckerIF { public: CheckerHBM2(); - virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; - virtual void insert(Command, Rank, BankGroup, Bank) override; + virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), + BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; + virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; private: const MemSpecHBM2 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerIF.h b/DRAMSys/library/src/controller/checker/CheckerIF.h index b5c4d9bb..a930d797 100644 --- a/DRAMSys/library/src/controller/checker/CheckerIF.h +++ b/DRAMSys/library/src/controller/checker/CheckerIF.h @@ -46,8 +46,9 @@ class CheckerIF public: virtual ~CheckerIF() {} - virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const = 0; - virtual void insert(Command, Rank, BankGroup, Bank) = 0; + virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), + BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const = 0; + virtual void insert(Command, Rank, BankGroup, Bank, unsigned) = 0; }; #endif // CHECKERIF_H diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp index 366f9b1f..2dfc9456 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.cpp @@ -66,7 +66,7 @@ CheckerLPDDR4::CheckerLPDDR4() tREFPDEN = memSpec->tCK + memSpec->tCMDCKE; } -sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const +sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank, unsigned) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -496,7 +496,7 @@ sc_time CheckerLPDDR4::timeToSatisfyConstraints(Command command, Rank rank, Bank return earliestTimeToStart; } -void CheckerLPDDR4::insert(Command command, Rank rank, BankGroup, Bank bank) +void CheckerLPDDR4::insert(Command command, Rank rank, BankGroup, Bank bank, unsigned) { PRINTDEBUGMESSAGE("CheckerLPDDR4", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h index 5a73154a..3fe5e506 100644 --- a/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h +++ b/DRAMSys/library/src/controller/checker/CheckerLPDDR4.h @@ -45,8 +45,9 @@ class CheckerLPDDR4 final : public CheckerIF { public: CheckerLPDDR4(); - virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; - virtual void insert(Command, Rank, BankGroup, Bank) override; + virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), + BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; + virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; private: const MemSpecLPDDR4 *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp index 6f588494..16985f5d 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.cpp @@ -60,7 +60,7 @@ CheckerWideIO::CheckerWideIO() tWRAPDEN = memSpec->tWL + tBURST + memSpec->tWR; // + memSpec->tCK; ?? } -sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const +sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank, unsigned) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -385,7 +385,7 @@ sc_time CheckerWideIO::timeToSatisfyConstraints(Command command, Rank rank, Bank return earliestTimeToStart; } -void CheckerWideIO::insert(Command command, Rank rank, BankGroup, Bank bank) +void CheckerWideIO::insert(Command command, Rank rank, BankGroup, Bank bank, unsigned) { PRINTDEBUGMESSAGE("CheckerWideIO", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO.h b/DRAMSys/library/src/controller/checker/CheckerWideIO.h index e5cdb430..c8b145a6 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO.h +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO.h @@ -45,8 +45,9 @@ class CheckerWideIO final : public CheckerIF { public: CheckerWideIO(); - virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; - virtual void insert(Command, Rank, BankGroup, Bank) override; + virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), + BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; + virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; private: const MemSpecWideIO *memSpec; diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp index 14818bed..10e75682 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO2.cpp @@ -61,7 +61,7 @@ CheckerWideIO2::CheckerWideIO2() tWRRD_R = memSpec->tWL + memSpec->tCK + tBURST + memSpec->tRTRS - memSpec->tRL; } -sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank) const +sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, BankGroup, Bank bank, unsigned) const { sc_time lastCommandStart; sc_time earliestTimeToStart = sc_time_stamp(); @@ -463,7 +463,7 @@ sc_time CheckerWideIO2::timeToSatisfyConstraints(Command command, Rank rank, Ban return earliestTimeToStart; } -void CheckerWideIO2::insert(Command command, Rank rank, BankGroup, Bank bank) +void CheckerWideIO2::insert(Command command, Rank rank, BankGroup, Bank bank, unsigned) { PRINTDEBUGMESSAGE("CheckerWideIO2", "Changing state on bank " + std::to_string(bank.ID()) + " command is " + commandToString(command)); diff --git a/DRAMSys/library/src/controller/checker/CheckerWideIO2.h b/DRAMSys/library/src/controller/checker/CheckerWideIO2.h index 08d328b9..a1e32636 100644 --- a/DRAMSys/library/src/controller/checker/CheckerWideIO2.h +++ b/DRAMSys/library/src/controller/checker/CheckerWideIO2.h @@ -45,8 +45,9 @@ class CheckerWideIO2 final : public CheckerIF { public: CheckerWideIO2(); - virtual sc_time timeToSatisfyConstraints(Command, Rank, BankGroup, Bank) const override; - virtual void insert(Command, Rank, BankGroup, Bank) override; + virtual sc_time timeToSatisfyConstraints(Command, Rank = Rank(0), + BankGroup = BankGroup(0), Bank = Bank(0), unsigned burstLength = 0) const override; + virtual void insert(Command, Rank, BankGroup, Bank, unsigned) override; private: const MemSpecWideIO2 *memSpec; diff --git a/DRAMSys/library/src/simulation/Arbiter.cpp b/DRAMSys/library/src/simulation/Arbiter.cpp index 500f098b..bd8f0baa 100644 --- a/DRAMSys/library/src/simulation/Arbiter.cpp +++ b/DRAMSys/library/src/simulation/Arbiter.cpp @@ -54,6 +54,8 @@ Arbiter::Arbiter(sc_module_name name, std::string pathToAddressMapping) : addressDecoder = new AddressDecoder(pathToAddressMapping); addressDecoder->print(); + + burstLengthShift = std::log2(Configuration::getInstance().memSpec->dataBusWidth / 8); } ArbiterSimple::ArbiterSimple(sc_module_name name, std::string pathToAddressMapping) : @@ -140,7 +142,7 @@ tlm_sync_enum Arbiter::nb_transport_fw(int id, tlm_generic_payload &payload, Channel(decodedAddress.channel), Rank(decodedAddress.rank), BankGroup(decodedAddress.bankgroup), Bank(decodedAddress.bank), Row(decodedAddress.row), Column(decodedAddress.column), - payload.get_streaming_width(), 0, 0); + payload.get_data_length() >> burstLengthShift, 0, 0); payload.acquire(); } diff --git a/DRAMSys/library/src/simulation/Arbiter.h b/DRAMSys/library/src/simulation/Arbiter.h index d124c466..ebd2d3bf 100644 --- a/DRAMSys/library/src/simulation/Arbiter.h +++ b/DRAMSys/library/src/simulation/Arbiter.h @@ -87,6 +87,8 @@ protected: sc_time tCK; sc_time arbitrationDelayFw; sc_time arbitrationDelayBw; + + unsigned burstLengthShift; }; class ArbiterSimple final : public Arbiter