diff --git a/DRAMSys/simulator/src/controller/scheduler/Fr_Fcfs_read_priority.cpp b/DRAMSys/simulator/src/controller/scheduler/Fr_Fcfs_read_priority.cpp
index 57f17426..92c07c63 100644
--- a/DRAMSys/simulator/src/controller/scheduler/Fr_Fcfs_read_priority.cpp
+++ b/DRAMSys/simulator/src/controller/scheduler/Fr_Fcfs_read_priority.cpp
@@ -52,21 +52,10 @@ std::pair<Command, gp*> FR_FCFS_RP::getNextRequest(Bank bank)
     // 3. Read Miss (Hazard Check) TODO
     // 4. Write Miss TODO
 
-    if(DebugManager::getInstance().writeToConsole == true)
-    {
-        for(unsigned long i=0; i < buffer[bank].size(); i++)
-        {
-            gp* trans = buffer[bank].at(i);
-            cout << ((trans->get_command() == tlm::TLM_READ_COMMAND)?"R":"W");
-        }
-        cout << endl;
-        cout.flush();
-    }
-
     // 1. Seach for read hit:
-    for(unsigned long i=0; i < buffer[bank].size(); i++)
+    for(auto it = buffer[bank].begin(); it!=buffer[bank].end(); it++)
     {
-        gp* read = buffer[bank].at(i);
+        gp* read = *it;
 
         if(read->get_command() == tlm::TLM_READ_COMMAND)
         {
@@ -74,20 +63,19 @@ std::pair<Command, gp*> FR_FCFS_RP::getNextRequest(Bank bank)
             if(DramExtension::getRow(read)
                 == controllerCore.getRowBufferStates().getRowInRowBuffer(bank))
             {
-                if(hazardDetection(bank, i) == false)
+                if(hazardDetection(bank, it) == false)
                 {
-                    buffer[bank].erase(buffer[bank].begin() + i);
-                    return pair<Command, gp*>(getReadWriteCommand(*read),
-                                              read);
+                    buffer[bank].erase(it);
+                    return pair<Command, gp*>(getReadWriteCommand(*read),read);
                 }
             }
         }
     }
 
-    // 2. Search for write hit:
-    for(unsigned long i=0; i < buffer[bank].size(); i++)
+    // 2. Seach for write hit:
+    for(auto it = buffer[bank].begin(); it!=buffer[bank].end(); it++)
     {
-        gp* write = buffer[bank].at(i);
+        gp* write = *it;
 
         if(write->get_command() == tlm::TLM_WRITE_COMMAND)
         {
@@ -95,9 +83,8 @@ std::pair<Command, gp*> FR_FCFS_RP::getNextRequest(Bank bank)
             if(DramExtension::getRow(write)
                 == controllerCore.getRowBufferStates().getRowInRowBuffer(bank))
             {
-                    buffer[bank].erase(buffer[bank].begin() + i);
-                    return pair<Command, gp*>(getReadWriteCommand(*write),
-                                              write);
+                buffer[bank].erase(it);
+                return pair<Command, gp*>(getReadWriteCommand(*write),write);
             }
         }
     }
@@ -111,13 +98,14 @@ std::pair<Command, gp*> FR_FCFS_RP::getNextRequest(Bank bank)
 
 // There is a hazard if a read is found which will be scheduled before a write
 // to the same column and the same row of the same bank:
-bool FR_FCFS_RP::hazardDetection(Bank bank, unsigned long id)
+bool FR_FCFS_RP::hazardDetection(Bank bank, std::deque<gp*>::iterator ext)
 {
-    gp* read = buffer[bank].at(id);
+    gp* read = *ext;
 
-    for(unsigned long i=0; i < id; i++)
+    //for(unsigned long i=0; i < id; i++)
+    for(auto it = buffer[bank].begin(); it!=ext; it++)
     {
-        gp* write = buffer[bank].at(i);
+        gp* write = *it;
         if(write->get_command() == tlm::TLM_WRITE_COMMAND)
         {
             if((DramExtension::getExtension(read).getColumn()
diff --git a/DRAMSys/simulator/src/controller/scheduler/Fr_Fcfs_read_priority.h b/DRAMSys/simulator/src/controller/scheduler/Fr_Fcfs_read_priority.h
index 1593a517..1b00d732 100644
--- a/DRAMSys/simulator/src/controller/scheduler/Fr_Fcfs_read_priority.h
+++ b/DRAMSys/simulator/src/controller/scheduler/Fr_Fcfs_read_priority.h
@@ -48,7 +48,7 @@ public:
 
 private:
 
-    bool hazardDetection(Bank bank, unsigned long id);
+    bool hazardDetection(Bank bank, std::deque<gp*>::iterator ext);
     void printDebugMessage(std::string message);
 };