diff --git a/DRAMSys/gem5/README.md b/DRAMSys/gem5/README.md index 2ab5d744..9d27e7dd 100644 --- a/DRAMSys/gem5/README.md +++ b/DRAMSys/gem5/README.md @@ -13,311 +13,27 @@ scons --with-cxx-config --without-python --without-tcmalloc build/ARM/libgem5_op In order to use gem5 with DRAMSys export the `GEM5` environment variable (gem5 root directory) and add the path of the library to `LD_LIBRARY_PATH`, then rerun CMake and rebuild the DRAMSys project. -Before you can run gem5 with DRAMSys it is mandatory to run gem5 first without DRAMSys and generate a configuration file *config.ini*, which will be the value of the second parameter passed to DRAMSys_gem5. +### DRAMSys with gem5 ARM SE mode -### DRAMSys with gem5 Traffic Generator - -In the following we will run a simple example with a gem5 traffic generator: - -``` -Base System Architecture: -+-------------+ +------+ ^ -| System Port | | TGEN | | -+-------+-----+ +--+---+ | - | | | gem5 World - | +----+ | - | | | -+-------v------v-------+ | -| Membus | v -+---------------+------+ External Port (see sc_slave_port.*) - | ^ - +----v----+ | TLM World - | DRAMSys | | (see sc_target.*) - +---------+ v - -``` - -As mentioned before we first need to create a *config.ini* that represents the gem5 configuration. We do so by starting gem5 with the desired python configuration script. +All essential files for a functional example are provided. Execute a hello world application: ```bash -cd gem5/util/tlm/ -../../build/ARM/gem5.opt conf/tlm_slave.py -``` - -**Ignore the message below.** -``` -"fatal: Can't find port handler type 'tlm_slave'" -``` - -The configuration file *config.ini* will be stored in the *m5out* directory. Copy this configuration file to the building directory of DRAMSys where the -executable *DRAMSys_gem5* is located (*DRAMSys/build/gem5*). - -Also the traffic generatior configuration file (*conf/tgen.cfg*) must be stored in a conf directory of this building directory (*DRAMSys/build/gem5/conf*). - -Then the simulation can be started with: - -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json config.ini 1 -``` - -Let the simulation run for some seconds and then stop it with **CTRL-C**. Observe the output of the simulation in the Trace Analyzer. The trace database can be found in *DRAMSys/build/gem5*. - -### gem5 SE mode and DRAMSys - -All essential files for some functional examples are provided. - -Execute a hello world application: - -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/configs/hello.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/hello-ARM/config.ini 1 ``` A **Hello world!** message should be printed to the standard output. -Execute applications: +### DRAMSys with gem5 x86 SE mode + +Make sure you have built *gem5/build/X86/libgem5_opt.so*. Add the path of the library to `LD_LIBRARY_PATH` and remove the path of the ARM library. + +Change the architecture in the [CMake file](DRAMSys/gem5/CMakeLists.txt) to *X86*, rerun CMake and rebuild the project. Test with a hello world application for X86: ```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/Oscar/config.ini 1 +./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/hello-x86/config.ini 1 ``` -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/Bubblesort/config.ini 1 -``` - -Wait some minutes for the application to finish. The hello application binary was copied from gem5 repository. Other applications were obtained with [gem5.TnT]. - -Command template for generating *.ini* configuration files follows: - -```bash -build/ARM/gem5.opt configs/example/se.py \ - -c --mem-size=512MB --mem-channels=1 \ - --caches --l2cache --mem-type=SimpleMemory \ - --cpu-type=TimingSimpleCPU --num-cpu=1 \ - --tlm-memory=transactor -``` - -An overview of the architcture being simulated is presented below: - -![arch](images/gem5_se_mode_arch.png) - -**Note**: This is a gem5 generated file, therefore DRAMSys is omitted. DRAMSys is directly connected as an external TLM slave. - -**Note**: Workaround in se.py required: - -```python -... -if options.tlm_memory: - system.physmem = SimpleMemory() -MemConfig.config_mem(options, system) -... -``` - -A convenience script to execute several applications automatically [run.sh](DRAMSys/gem5/gem5_se/run.sh) is provided. Take a look and learn from it. - -### [PARSEC] FS Mode - -Full system simulation files for ARM are available in [DRAMSys/gem5/gem5_fs/parsec_arm_minor_2c_8GB](DRAMSys/gem5/gem5_fs/parsec_arm_minor_2c_8GB). Choose the benchmark in [parsec_arm_minor_2c_8GB.rcS](DRAMSys/gem5/gem5_fs/parsec_arm_minor_2c_8GB/parsec_arm_minor_2c_8GB.rcS) and edit the paths in [config.ini](DRAMSys/gem5/gem5_fs/parsec_arm_minor_2c_8GB/config.ini). - -All files required to build DRAMSys_gem5 and execute the simulation (gem5 library, benchmarks, disk image, etc.) can be obtained with [gem5.TnT]. - -Start a simulation, e.g.: - -```bash -DRAMSys/build/gem5$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/rgrsim-gem5-fs.json ../../DRAMSys/gem5/gem5_fs/parsec_arm_minor_2c_8GB/config.ini 1 -``` - -Optionally, open another terminal or tab and connect to gem5. - -```bash -$ telnet localhost 3456 -``` - -Note: The port may vary, gem5 prints it during initialization. Example: - -``` -system.terminal: Listening for connections on port 3456 -``` - -### [PARSEC] SE Mode - - -Binaries and gem5 SE configuration files for ARM available in [DRAMSys/gem5/gem5_se/parsec-arm](DRAMSys/gem5/gem5_se/parsec-arm). Use [gem5.TnT] to download parsec: Go to your *gem5.TnT* folder. Then go to *arch/arm* folder. Execute the script *build-parsec-serial.sh*. - -```bash -gem5.TnT/arch/arm$ ./build-parsec-serial.sh -``` - -Extract inputs files. Example: - -```bash -cd $HOME/gem5_tnt/benchmarks/parsec-3.0/pkgs/kernels/canneal/inputs -tar -xf input_simdev.tar -tar -xf input_test.tar -tar -xf input_simmedium.tar -tar -xf input_simsmall.tar -tar -xf input_native.tar -tar -xf input_simlarge.tar - -cd $HOME/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/fluidanimate/inputs -tar -xf input_simdev.tar -tar -xf input_test.tar -tar -xf input_native.tar -tar -xf input_simlarge.tar -tar -xf input_simmedium.tar -tar -xf input_simsmall.tar - -cd $HOME/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/blackscholes/inputs -tar -xf input_simdev.tar -tar -xf input_test.tar -tar -xf input_native.tar -tar -xf input_simlarge.tar -tar -xf input_simmedium.tar -tar -xf input_simsmall.tar -``` - -Open [DRAMSys/gem5/gem5_se/parsec-arm/config.ini](DRAMSys/gem5/gem5_se/parsec-arm/config.ini) - -Edit **cmd=**. - -Edit **executable=**. - -Examples (**Replace USER. Use the correct path in your computer.**): - -``` --- canneal -- - -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/canneal/canneal 1 5 100 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/kernels/canneal/inputs/10.nets 1 -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/canneal/canneal 1 100 300 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/kernels/canneal/inputs/100.nets 2 -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/canneal/canneal 1 10000 2000 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/kernels/canneal/inputs/100000.nets 32 -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/canneal/canneal 1 15000 2000 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/kernels/canneal/inputs/200000.nets 64 -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/canneal/canneal 1 15000 2000 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/kernels/canneal/inputs/400000.nets 128 - -executable=../../DRAMSys/gem5/gem5_se/parsec-arm/canneal/canneal - --- streamcluster -- - -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster 2 5 1 10 10 5 none output.txt 1 -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster 3 10 3 16 16 10 none output.txt 1 -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster 10 20 32 4096 4096 1000 none output.txt 1 -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster 10 20 64 8192 8192 1000 none output.txt 1 -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster 10 20 128 16384 16384 1000 none output.txt 1 -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster 10 20 128 1000000 200000 5000 none output.txt 1 - -executable=../../DRAMSys/gem5/gem5_se/parsec-arm/streamcluster/streamcluster - --- swaptions -- - -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/swaptions/swaptions -ns 1 -sm 5 -nt 1 -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/swaptions/swaptions -ns 3 -sm 50 -nt 1 -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/swaptions/swaptions -ns 16 -sm 5000 -nt 1 -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/swaptions/swaptions -ns 32 -sm 10000 -nt 1 -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/swaptions/swaptions -ns 64 -sm 20000 -nt 1 - -executable=../../DRAMSys/gem5/gem5_se/parsec-arm/swaptions/swaptions - --- fluidanimate -- - -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/fluidanimate/fluidanimate 1 1 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/fluidanimate/inputs/in_5K.fluid out.fluid -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/fluidanimate/fluidanimate 1 3 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/fluidanimate/inputs/in_15K.fluid out.fluid -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/fluidanimate/fluidanimate 1 5 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/fluidanimate/inputs/in_35K.fluid out.fluid -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/fluidanimate/fluidanimate 1 5 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/fluidanimate/inputs/in_100K.fluid out.fluid -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/fluidanimate/fluidanimate 1 5 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/fluidanimate/inputs/in_300K.fluid out.fluid - -executable=../../DRAMSys/gem5/gem5_se/parsec-arm/fluidanimate/fluidanimate - --- blackscholes -- - -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/blackscholes/blackscholes 1 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/blackscholes/inputs/in_4.txt prices.txt -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/blackscholes/blackscholes 1 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/blackscholes/inputs/in_16.txt prices.txt -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/blackscholes/blackscholes 1 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/blackscholes/inputs/in_4K.txt prices.txt -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/blackscholes/blackscholes 1 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/blackscholes/inputs/in_16K.txt prices.txt -cmd=../../DRAMSys/gem5/gem5_se/parsec-arm/blackscholes/blackscholes 1 /home/USER/gem5_tnt/benchmarks/parsec-3.0/pkgs/apps/blackscholes/inputs/in_64K.txt prices.txt - -executable=../../DRAMSys/gem5/gem5_se/parsec-arm/blackscholes/blackscholes - -``` - -Start a simulation. Example: - -```bash -DRAMSys/build/gem5$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/rgrsim-gem5-se.json ../../DRAMSys/gem5/gem5_se/parsec-arm/config.ini 1 -``` - -### Boot Linux with gem5 and DRAMSys - -The procedure is very similar to the traffic generator example above. - -First we have to generate the config.ini file by starting gem5 with the following configuration: - -```bash -build/ARM/gem5.opt configs/example/fs.py \ - --tlm-memory=transactor --cpu-type=TimingSimpleCPU --num-cpu=1 \ - --mem-type=SimpleMemory --mem-size=512MB --mem-channels=1 --caches \ - --l2cache --machine-type=VExpress_EMM \ - --dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \ - --kernel=vmlinux.aarch32.ll_20131205.0-gem5 \ - --disk-image=linux-aarch32-ael.img -``` - -The *config.ini* should be copied again to the DRAMSys_gem5 build folder. - -The *simconfig* should be changed in order to support storage and address offsets: - -``` json -{ - "simconfig": { - "CheckTLM2Protocol": false, - "DatabaseRecording": true, - "Debug": false, - "ECCControllerMode": "Disabled", - "EnableWindowing": false, - "ErrorCSVFile": "", - "ErrorChipSeed": 42, - "PowerAnalysis": false, - "SimulationName": "ddr3", - "SimulationProgressBar": false, - "ThermalSimulation": false, - "WindowSize": 1000, - - "StoreMode": "Store", - "AddressOffset": 2147483648, - "UseMalloc": true - } -} -``` - -Then start *DRAMSys_gem5* with the following command: - -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-example.json config.ini 1 -``` - -For further sophisticated address mappings or scenarios checkout the file *DRAMSys/gem5/main.cpp*. - -#### Boot Linux with gem5 and DRAMSys Example - -**All essential files for a functional example are provided.** - -Unzip the disk image: - -```bash -tar -xaf DRAMSys/gem5/boot_linux/linux-aarch32-ael.img.tar.gz -C DRAMSys/gem5/boot_linux/ -``` - -Execute the example: - -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-boot-linux.json ../../DRAMSys/gem5/configs/boot_linux.ini 1 -``` - -Open a new terminal and connect to gem5: - -```bash -telnet localhost 3456 -``` - -Wait some minutes for the Linux boot process to complete then login. Username is **root**, no password required. - +A **Hello world!** message should be printed to the standard output. ### DRAMSys with gem5 Elastic Traces @@ -352,156 +68,11 @@ An overview of the architcture being simulated is presented below: For more sophisticated setups, even with L2 caches the proper *.ini* file should be created. -### DRAMSys + gem5 x86 - -Make sure you have built *gem5/build/X86/libgem5_opt.so*. Add the path of the library to `LD_LIBRARY_PATH` and remove the path of the ARM library. - -Change the architecture in the [CMake file](DRAMSys/gem5/CMakeLists.txt) to *X86*, rerun CMake and rebuild the project. Test with a hello world application for X86: - -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/hello-x86/config.ini 1 -``` - -A **Hello world!** message should be printed to the standard output. - -### [MiBench] - -Applications for x86 and configuration files available in [DRAMSys/gem5/gem5_se/MiBench](DRAMSys/gem5/gem5_se/MiBench). - -Examples: - -**Automotive Applications** - -**Basicmath** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/basicmath/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/basicmath/large/config.ini 1 -``` - -**Bitcount** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/bitcount/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/bitcount/large/config.ini 1 -``` - -**Qsort** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/qsort/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/qsort/large/config.ini 1 -``` - -**Susan** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/small/corners/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/large/corners/config.ini 1 - -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/small/edges/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/large/edges/config.ini 1 - -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/small/smoothing/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/automotive/susan/large/smoothing/config.ini 1 -``` - -**Network Applications** - -**Dijkstra** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/network/dijkstra/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/network/dijkstra/large/config.ini 1 -``` - -**Patricia** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/network/patricia/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/network/patricia/large/config.ini 1 -``` - -**Security Applications** - -**Blowfish Encode** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/encode/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/encode/large/config.ini 1 -``` - -**Blowfish Decode** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/decode/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/blowfish/decode/large/config.ini 1 -``` - -**SHA** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/sha/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/security/sha/large/config.ini 1 -``` - -**Telecom Applications** - -**CRC32** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/crc32/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/crc32/large/config.ini 1 -``` - -**FFT** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft/large/config.ini 1 -``` - -**FFT-INV** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft-inv/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/fft-inv/large/config.ini 1 -``` - -**GSM Encode** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/encode/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/encode/large/config.ini 1 -``` - -**GSM Decode** -```bash -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/decode/small/config.ini 1 -./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json ../../DRAMSys/gem5/gem5_se/MiBench/telecomm/gsm/decode/large/config.ini 1 -``` - -Check the folder [DRAMSys/gem5/gem5_se/MiBench](DRAMSys/gem5/gem5_se/MiBench) for all applications and configuration files. - -### More AArch64 Apps - -Full system simulation files for ARM available in [DRAMSys/gem5/gem5_fs/arm64](DRAMSys/gem5/gem5_fs/arm64). You can edit [arm64.rcS](DRAMSys/gem5/gem5_fs/arm64/arm64.rcS) to start an application and call *m5 exit* when it finishes. - -Edit the paths in [config.ini](DRAMSys/gem5/gem5_fs/arm64/config.ini). All files required to build DRAMSys_gem5 and execute the simulation (gem5 library, benchmarks, disk image, etc.) can be obtained with [gem5.TnT]. - -Start a simulation. Example: - -```bash -DRAMSys/build/gem5$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/rgrsim-gem5-fs.json ../../DRAMSys/gem5/gem5_fs/arm64/config.ini 1 -``` - -Optionally, open another terminal or tab and connect to gem5. - -```bash -$ telnet localhost 3456 -``` - -Note: The port may vary, gem5 prints it during initialization. Example: - -``` -system.terminal: Listening for connections on port 3456 -``` - ## References [1] System Simulation with gem5 and SystemC: The Keystone for Full Interoperability C. Menard, M. Jung, J. Castrillon, N. Wehn. IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2017, Samos Island, Greece. -[2] Exploring System Performance using Elastic Traces: Fast, Accurate and Portable -R. Jagtap, S. Diestelhorst, A. Hansson, M. Jung, N. Wehn, IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), 2016, Samos Island, Greece. - [gem5.TnT]: https://github.com/tukl-msd/gem5.TnT [MiBench]: http://vhosts.eecs.umich.edu/mibench/ [PARSEC]: http://parsec.cs.princeton.edu/ \ No newline at end of file diff --git a/DRAMSys/gem5/boot_linux/boot_emm.arm b/DRAMSys/gem5/boot_linux/boot_emm.arm deleted file mode 100644 index b46a5d9d..00000000 Binary files a/DRAMSys/gem5/boot_linux/boot_emm.arm and /dev/null differ diff --git a/DRAMSys/gem5/boot_linux/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb b/DRAMSys/gem5/boot_linux/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb deleted file mode 100644 index 6f59f4f9..00000000 Binary files a/DRAMSys/gem5/boot_linux/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb and /dev/null differ diff --git a/DRAMSys/gem5/configs/boot_linux.ini b/DRAMSys/gem5/configs/boot_linux.ini deleted file mode 100644 index 471e37de..00000000 --- a/DRAMSys/gem5/configs/boot_linux.ini +++ /dev/null @@ -1,1661 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=true -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=LinuxArmSystem -children=bootmem bridge cf0 clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler external_memory intrctrl iobus iocache l2 membus realview terminal tol2bus vncserver voltage_domain -atags_addr=134217728 -auto_reset_addr_64=false -boot_loader=../../DRAMSys/gem5/boot_linux/boot_emm.arm -boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=512MB root=/dev/sda1 -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -dtb_filename=../../DRAMSys/gem5/boot_linux/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb -early_kernel_symbols=false -enable_context_switch_stats_dump=false -eventq_index=0 -exit_on_work_items=false -flags_addr=469827632 -gic_cpu_addr=738205696 -have_large_asid_64=false -have_lpae=true -have_security=false -have_virtualization=false -highest_el_is_64=false -init_param=0 -kernel=../../DRAMSys/gem5/boot_linux/vmlinux.aarch32.ll_20131205.0-gem5 -kernel_addr_check=false -kernel_extras= -load_addr_mask=0 -load_offset=2147483648 -m5ops_base=0 -machine_type=VExpress_EMM -mem_mode=timing -mem_ranges=2147483648:2684354559:0:0:0:0 -memories=system.bootmem system.realview.vram -mmap_using_noreserve=false -multi_proc=true -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -panic_on_oops=false -panic_on_panic=false -phys_addr_range_64=40 -power_model= -readfile= -reset_addr_64=0 -semihosting=Null -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[1] - -[system.bootmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=false -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -range=0:67108863:0:0:0:0 -port=system.membus.master[1] - -[system.bridge] -type=Bridge -clk_domain=system.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -ranges=788529152:805306367:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0 -req_size=16 -resp_size=16 -master=system.iobus.slave[0] -slave=system.membus.master[0] - -[system.cf0] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.cf0.image - -[system.cf0.image] -type=CowDiskImage -children=child -child=system.cf0.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.cf0.image.child] -type=RawDiskImage -eventq_index=0 -image_file=../../DRAMSys/gem5/boot_linux/linux-aarch32-ael.img -read_only=true - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_gating_on_idle=false -power_model= -profile=0 -progress_interval=0 -pwr_gating_latency=300 -simpoint_start_insts= -socket_id=0 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.tracer -wait_for_remote_gdb=false -workload= -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu.dcache.replacement_policy -response_latency=2 -sequential_access=false -size=65536 -system=system -tag_latency=2 -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -warmup_percentage=0 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.tol2bus.slave[1] - -[system.cpu.dcache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu.dcache.tags] -type=BaseSetAssoc -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu.dcache.replacement_policy -sequential_access=false -size=65536 -tag_latency=2 -warmup_percentage=0 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system -port=system.tol2bus.slave[3] - -[system.cpu.icache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu.icache.replacement_policy -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu.icache.tags -tgts_per_mshr=20 -warmup_percentage=0 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.tol2bus.slave[0] - -[system.cpu.icache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu.icache.tags] -type=BaseSetAssoc -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu.icache.replacement_policy -sequential_access=false -size=32768 -tag_latency=2 -warmup_percentage=0 - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -impdef_nop=false -midr=1091551472 -pmu=Null -system=system -vecRegRenameMode=Full - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system -port=system.tol2bus.slave[2] - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.cpu_voltage_domain - -[system.cpu_voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.0 - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.external_memory] -type=ExternalSlave -addr_ranges=2147483648:2684354559:0:0:0:0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -port_data=transactor -port_type=tlm_slave -power_model= -port=system.membus.master[6] - -[system.intrctrl] -type=IntrControl -eventq_index=0 -sys=system - -[system.iobus] -type=NoncoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=1 -frontend_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -response_latency=2 -use_default_range=false -width=16 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side -slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma - -[system.iocache] -type=Cache -children=replacement_policy tags -addr_ranges=2147483648:2684354559:0:0:0:0 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=50 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.iocache.replacement_policy -response_latency=50 -sequential_access=false -size=1024 -system=system -tag_latency=50 -tags=system.iocache.tags -tgts_per_mshr=12 -warmup_percentage=0 -write_buffers=8 -writeback_clean=false -cpu_side=system.iobus.master[23] -mem_side=system.membus.slave[2] - -[system.iocache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.iocache.tags] -type=BaseSetAssoc -assoc=8 -block_size=64 -clk_domain=system.clk_domain -data_latency=50 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.iocache.replacement_policy -sequential_access=false -size=1024 -tag_latency=50 -warmup_percentage=0 - -[system.l2] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=20 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.l2.replacement_policy -response_latency=20 -sequential_access=false -size=2097152 -system=system -tag_latency=20 -tags=system.l2.tags -tgts_per_mshr=12 -warmup_percentage=0 -write_buffers=8 -writeback_clean=false -cpu_side=system.tol2bus.master[0] -mem_side=system.membus.slave[3] - -[system.l2.replacement_policy] -type=LRURP -eventq_index=0 - -[system.l2.tags] -type=BaseSetAssoc -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=20 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.l2.replacement_policy -sequential_access=false -size=2097152 -tag_latency=20 -warmup_percentage=0 - -[system.membus] -type=CoherentXBar -children=badaddr_responder snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -point_of_unification=true -power_model= -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.bootmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.realview.hdlcd.pio system.external_memory.port -slave=system.realview.hdlcd.dma system.system_port system.iocache.mem_side system.l2.mem_side - -[system.membus.badaddr_responder] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=0 -pio_latency=100000 -pio_size=8 -power_model= -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access=warn -pio=system.membus.default - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.realview] -type=RealView -children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake -eventq_index=0 -intrctrl=system.intrctrl -system=system - -[system.realview.aaci_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470024192 -pio_latency=100000 -power_model= -system=system -pio=system.iobus.master[16] - -[system.realview.cf_ctrl] -type=IdeController -BAR0=471465984 -BAR0LegacyIO=true -BAR0Size=256 -BAR1=471466240 -BAR1LegacyIO=true -BAR1Size=4096 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=1 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=2 -default_p_state=UNDEFINED -disks= -eventq_index=0 -host=system.realview.pci_host -io_shift=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=2 -pci_dev=0 -pci_func=0 -pio_latency=30000 -power_model= -system=system -dma=system.iobus.slave[2] -pio=system.iobus.master[8] - -[system.realview.clcd] -type=Pl111 -amba_id=1315089 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -enable_capture=true -eventq_index=0 -gic=system.realview.gic -int_num=46 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=471793664 -pio_latency=10000 -pixel_clock=41667 -power_model= -system=system -vnc=system.vncserver -dma=system.iobus.slave[1] -pio=system.iobus.master[5] - -[system.realview.dcc] -type=SubSystem -children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys -eventq_index=0 -thermal_domain=Null - -[system.realview.dcc.osc_cpu] -type=RealViewOsc -dcc=0 -device=0 -eventq_index=0 -freq=16667 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_ddr] -type=RealViewOsc -dcc=0 -device=8 -eventq_index=0 -freq=25000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_hsbm] -type=RealViewOsc -dcc=0 -device=4 -eventq_index=0 -freq=25000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_pxl] -type=RealViewOsc -dcc=0 -device=5 -eventq_index=0 -freq=42105 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_smb] -type=RealViewOsc -dcc=0 -device=6 -eventq_index=0 -freq=20000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_sys] -type=RealViewOsc -dcc=0 -device=7 -eventq_index=0 -freq=16667 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.energy_ctrl] -type=EnergyCtrl -clk_domain=system.clk_domain -default_p_state=UNDEFINED -dvfs_handler=system.dvfs_handler -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470286336 -pio_latency=100000 -power_model= -system=system -pio=system.iobus.master[20] - -[system.realview.ethernet] -type=IGbE -BAR0=0 -BAR0LegacyIO=false -BAR0Size=131072 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=0 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=4213 -ExpansionROM=0 -HeaderType=0 -InterruptLine=1 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=255 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=0 -Revision=0 -Status=0 -SubClassCode=0 -SubsystemID=4104 -SubsystemVendorID=32902 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -default_p_state=UNDEFINED -eventq_index=0 -fetch_comp_delay=10000 -fetch_delay=10000 -hardware_address=00:90:00:00:00:01 -host=system.realview.pci_host -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=0 -pci_func=0 -phy_epid=896 -phy_pid=680 -pio_latency=30000 -power_model= -rx_desc_cache_size=64 -rx_fifo_size=393216 -rx_write_delay=0 -system=system -tx_desc_cache_size=64 -tx_fifo_size=393216 -tx_read_delay=0 -wb_comp_delay=10000 -wb_delay=10000 -dma=system.iobus.slave[4] -pio=system.iobus.master[22] - -[system.realview.generic_timer] -type=GenericTimer -children=int_hyp int_phys_ns int_phys_s int_virt -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -int_hyp=system.realview.generic_timer.int_hyp -int_phys_ns=system.realview.generic_timer.int_phys_ns -int_phys_s=system.realview.generic_timer.int_phys_s -int_virt=system.realview.generic_timer.int_virt -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -system=system - -[system.realview.generic_timer.int_hyp] -type=ArmPPI -eventq_index=0 -num=26 -platform=system.realview - -[system.realview.generic_timer.int_phys_ns] -type=ArmPPI -eventq_index=0 -num=30 -platform=system.realview - -[system.realview.generic_timer.int_phys_s] -type=ArmPPI -eventq_index=0 -num=29 -platform=system.realview - -[system.realview.generic_timer.int_virt] -type=ArmPPI -eventq_index=0 -num=27 -platform=system.realview - -[system.realview.gic] -type=GicV2 -clk_domain=system.clk_domain -cpu_addr=738205696 -cpu_pio_delay=10000 -cpu_size=8192 -default_p_state=UNDEFINED -dist_addr=738201600 -dist_pio_delay=10000 -eventq_index=0 -gem5_extensions=false -int_latency=10000 -it_lines=128 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -platform=system.realview -power_model= -system=system -pio=system.membus.master[2] - -[system.realview.hdlcd] -type=HDLcd -amba_id=1314816 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -enable_capture=true -eventq_index=0 -frame_format=Auto -gic=system.realview.gic -int_num=117 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=721420288 -pio_latency=10000 -pixel_buffer_size=2048 -pixel_chunk=32 -power_model= -pxl_clk=system.realview.dcc.osc_pxl -system=system -virt_refresh_rate=50000000000 -vnc=system.vncserver -workaround_dma_line_count=true -workaround_swap_rb=true -dma=system.membus.slave[0] -pio=system.membus.master[5] - -[system.realview.ide] -type=IdeController -BAR0=1 -BAR0LegacyIO=false -BAR0Size=8 -BAR1=1 -BAR1LegacyIO=false -BAR1Size=4 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=0 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=2 -InterruptPin=2 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=0 -default_p_state=UNDEFINED -disks=system.cf0 -eventq_index=0 -host=system.realview.pci_host -io_shift=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=30000 -power_model= -system=system -dma=system.iobus.slave[3] -pio=system.iobus.master[21] - -[system.realview.kmi0] -type=Pl050 -children=ps2 -amba_id=1314896 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=100000 -int_num=44 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470155264 -pio_latency=100000 -power_model= -ps2=system.realview.kmi0.ps2 -system=system -pio=system.iobus.master[6] - -[system.realview.kmi0.ps2] -type=PS2Keyboard -eventq_index=0 -vnc=system.vncserver - -[system.realview.kmi1] -type=Pl050 -children=ps2 -amba_id=1314896 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=100000 -int_num=45 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470220800 -pio_latency=100000 -power_model= -ps2=system.realview.kmi1.ps2 -system=system -pio=system.iobus.master[7] - -[system.realview.kmi1.ps2] -type=PS2TouchKit -eventq_index=0 -vnc=system.vncserver - -[system.realview.l2x0_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=739246080 -pio_latency=100000 -pio_size=4095 -power_model= -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[10] - -[system.realview.lan_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=436207616 -pio_latency=100000 -pio_size=65535 -power_model= -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[17] - -[system.realview.local_cpu_timer] -type=CpuLocalTimer -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num_timer=29 -int_num_watchdog=30 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=738721792 -pio_latency=100000 -power_model= -system=system -pio=system.membus.master[4] - -[system.realview.mcc] -type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl -eventq_index=0 -thermal_domain=Null - -[system.realview.mcc.osc_clcd] -type=RealViewOsc -dcc=0 -device=1 -eventq_index=0 -freq=42105 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_mcc] -type=RealViewOsc -dcc=0 -device=0 -eventq_index=0 -freq=20000 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_peripheral] -type=RealViewOsc -dcc=0 -device=2 -eventq_index=0 -freq=41667 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_system_bus] -type=RealViewOsc -dcc=0 -device=4 -eventq_index=0 -freq=41667 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.temp_crtl] -type=RealViewTemperatureSensor -dcc=0 -device=0 -eventq_index=0 -parent=system.realview.realview_io -position=0 -site=0 -system=system - -[system.realview.mmc_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470089728 -pio_latency=100000 -power_model= -system=system -pio=system.iobus.master[19] - -[system.realview.pci_host] -type=GenericPciHost -clk_domain=system.clk_domain -conf_base=805306368 -conf_device_bits=16 -conf_size=268435456 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_dma_base=0 -pci_mem_base=0 -pci_pio_base=0 -platform=system.realview -power_model= -system=system -pio=system.iobus.master[2] - -[system.realview.realview_io] -type=RealViewCtrl -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -idreg=35979264 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=469827584 -pio_latency=100000 -power_model= -proc_id0=335544320 -proc_id1=335544320 -system=system -pio=system.iobus.master[1] - -[system.realview.rtc] -type=PL031 -amba_id=3412017 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=100000 -int_num=36 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=471269376 -pio_latency=100000 -power_model= -system=system -time=Thu Jan 1 00:00:00 2009 -pio=system.iobus.master[9] - -[system.realview.sp810_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=469893120 -pio_latency=100000 -power_model= -system=system -pio=system.iobus.master[14] - -[system.realview.timer0] -type=Sp804 -amba_id=1316868 -clk_domain=system.clk_domain -clock0=1000000 -clock1=1000000 -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num0=34 -int_num1=34 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470876160 -pio_latency=100000 -power_model= -system=system -pio=system.iobus.master[3] - -[system.realview.timer1] -type=Sp804 -amba_id=1316868 -clk_domain=system.clk_domain -clock0=1000000 -clock1=1000000 -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num0=35 -int_num1=35 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470941696 -pio_latency=100000 -power_model= -system=system -pio=system.iobus.master[4] - -[system.realview.uart] -type=Pl011 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -device=system.terminal -end_on_eot=false -eventq_index=0 -gic=system.realview.gic -int_delay=100000 -int_num=37 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470351872 -pio_latency=100000 -platform=system.realview -power_model= -system=system -pio=system.iobus.master[0] - -[system.realview.uart1_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470417408 -pio_latency=100000 -power_model= -system=system -pio=system.iobus.master[11] - -[system.realview.uart2_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470482944 -pio_latency=100000 -power_model= -system=system -pio=system.iobus.master[12] - -[system.realview.uart3_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470548480 -pio_latency=100000 -power_model= -system=system -pio=system.iobus.master[13] - -[system.realview.usb_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=452984832 -pio_latency=100000 -pio_size=131071 -power_model= -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[18] - -[system.realview.vgic] -type=VGic -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -hv_addr=738213888 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_delay=10000 -platform=system.realview -power_model= -ppint=25 -system=system -vcpu_addr=738222080 -pio=system.membus.master[3] - -[system.realview.vram] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=false -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -range=402653184:436207615:0:0:0:0 - -[system.realview.watchdog_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470745088 -pio_latency=100000 -power_model= -system=system -pio=system.iobus.master[15] - -[system.terminal] -type=Terminal -eventq_index=0 -number=0 -output=true -port=3456 - -[system.tol2bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -point_of_unification=true -power_model= -response_latency=1 -snoop_filter=system.tol2bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.l2.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port - -[system.tol2bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.vncserver] -type=VncServer -eventq_index=0 -frame_capture=false -img_format=Auto -number=0 -port=5900 - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.0 - diff --git a/DRAMSys/gem5/configs/dualElasticTraceReplay.dot.pdf b/DRAMSys/gem5/configs/dualElasticTraceReplay.dot.pdf deleted file mode 100644 index 723fe203..00000000 Binary files a/DRAMSys/gem5/configs/dualElasticTraceReplay.dot.pdf and /dev/null differ diff --git a/DRAMSys/gem5/configs/dualElasticTraceReplay.ini b/DRAMSys/gem5/configs/dualElasticTraceReplay.ini deleted file mode 100644 index e6cc4c1a..00000000 --- a/DRAMSys/gem5/configs/dualElasticTraceReplay.ini +++ /dev/null @@ -1,796 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu0 cpu1 cpu_clk_domain cpu_voltage_domain dvfs_handler membus1 membus2 physmem tlm1 tlm2 voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -kernel_extras= -load_addr_mask=18446744073709551615 -load_offset=0 -mem_mode=timing -mem_ranges=0:536870911:0:0:0:0 -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus1.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu0] -type=TraceCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer -checker=Null -clk_domain=system.clk_domain -cpu_id=0 -dataTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu0.dstage2_mmu -dtb=system.cpu0.dtb -enableEarlyExit=false -eventq_index=0 -freqMultiplier=1.0 -function_trace=false -function_trace_start=0 -instTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz -interrupts=system.cpu0.interrupts -isa=system.cpu0.isa -istage2_mmu=system.cpu0.istage2_mmu -itb=system.cpu0.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_gating_on_idle=false -power_model= -profile=0 -progressMsgInterval=0 -progress_interval=0 -pwr_gating_latency=300 -simpoint_start_insts= -sizeLoadBuffer=16 -sizeROB=40 -sizeStoreBuffer=16 -socket_id=0 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu0.tracer -wait_for_remote_gdb=false -workload= -dcache_port=system.cpu0.dcache.cpu_side -icache_port=system.cpu0.icache.cpu_side - -[system.cpu0.dcache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu0.dcache.replacement_policy -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu0.dcache.tags -tgts_per_mshr=20 -warmup_percentage=0 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu0.dcache_port -mem_side=system.membus1.slave[2] - -[system.cpu0.dcache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu0.dcache.tags] -type=BaseSetAssoc -assoc=2 -block_size=64 -clk_domain=system.clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu0.dcache.replacement_policy -sequential_access=false -size=32768 -tag_latency=2 -warmup_percentage=0 - -[system.cpu0.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu0.dtb - -[system.cpu0.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu0.dstage2_mmu.stage2_tlb.walker - -[system.cpu0.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu0.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu0.dtb.walker - -[system.cpu0.dtb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu0.icache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu0.icache.replacement_policy -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu0.icache.tags -tgts_per_mshr=20 -warmup_percentage=0 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu0.icache_port -mem_side=system.membus1.slave[1] - -[system.cpu0.icache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu0.icache.tags] -type=BaseSetAssoc -assoc=2 -block_size=64 -clk_domain=system.clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu0.icache.replacement_policy -sequential_access=false -size=32768 -tag_latency=2 -warmup_percentage=0 - -[system.cpu0.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu0.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -impdef_nop=false -midr=1091551472 -pmu=Null -system=system -vecRegRenameMode=Full - -[system.cpu0.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu0.itb - -[system.cpu0.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu0.istage2_mmu.stage2_tlb.walker - -[system.cpu0.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu0.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu0.itb.walker - -[system.cpu0.itb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu0.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu1] -type=TraceCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer -checker=Null -clk_domain=system.clk_domain -cpu_id=1 -dataTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu1.dstage2_mmu -dtb=system.cpu1.dtb -enableEarlyExit=false -eventq_index=0 -freqMultiplier=1.0 -function_trace=false -function_trace_start=0 -instTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz -interrupts=system.cpu1.interrupts -isa=system.cpu1.isa -istage2_mmu=system.cpu1.istage2_mmu -itb=system.cpu1.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_gating_on_idle=false -power_model= -profile=0 -progressMsgInterval=0 -progress_interval=0 -pwr_gating_latency=300 -simpoint_start_insts= -sizeLoadBuffer=16 -sizeROB=40 -sizeStoreBuffer=16 -socket_id=0 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu1.tracer -wait_for_remote_gdb=false -workload= -dcache_port=system.cpu1.dcache.cpu_side -icache_port=system.cpu1.icache.cpu_side - -[system.cpu1.dcache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu1.dcache.replacement_policy -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu1.dcache.tags -tgts_per_mshr=20 -warmup_percentage=0 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu1.dcache_port -mem_side=system.membus2.slave[1] - -[system.cpu1.dcache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu1.dcache.tags] -type=BaseSetAssoc -assoc=2 -block_size=64 -clk_domain=system.clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu1.dcache.replacement_policy -sequential_access=false -size=32768 -tag_latency=2 -warmup_percentage=0 - -[system.cpu1.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu1.dtb - -[system.cpu1.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu1.dstage2_mmu.stage2_tlb.walker - -[system.cpu1.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu1.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu1.dtb.walker - -[system.cpu1.dtb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu1.icache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu1.icache.replacement_policy -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu1.icache.tags -tgts_per_mshr=20 -warmup_percentage=0 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu1.icache_port -mem_side=system.membus2.slave[0] - -[system.cpu1.icache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu1.icache.tags] -type=BaseSetAssoc -assoc=2 -block_size=64 -clk_domain=system.clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu1.icache.replacement_policy -sequential_access=false -size=32768 -tag_latency=2 -warmup_percentage=0 - -[system.cpu1.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu1.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -impdef_nop=false -midr=1091551472 -pmu=Null -system=system -vecRegRenameMode=Full - -[system.cpu1.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu1.itb - -[system.cpu1.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu1.istage2_mmu.stage2_tlb.walker - -[system.cpu1.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu1.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu1.itb.walker - -[system.cpu1.itb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu1.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.cpu_voltage_domain - -[system.cpu_voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.0 - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus1] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -point_of_unification=true -power_model= -response_latency=2 -snoop_filter=system.membus1.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.tlm1.port -slave=system.system_port system.cpu0.icache.mem_side system.cpu0.dcache.mem_side - -[system.membus1.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.membus2] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -point_of_unification=true -power_model= -response_latency=2 -snoop_filter=system.membus2.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.tlm2.port -slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side - -[system.membus2.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -range=0:134217727:0:0:0:0 - -[system.tlm1] -type=ExternalSlave -addr_ranges=0:268435455:0:0:0:0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -port_data=transactor1 -port_type=tlm_slave -power_model= -port=system.membus1.master[0] - -[system.tlm2] -type=ExternalSlave -addr_ranges=0:268435455:0:0:0:0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -port_data=transactor2 -port_type=tlm_slave -power_model= -port=system.membus2.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.0 - diff --git a/DRAMSys/gem5/configs/nvdimmp.ini b/DRAMSys/gem5/configs/nvdimmp.ini deleted file mode 100644 index 5b7ef531..00000000 --- a/DRAMSys/gem5/configs/nvdimmp.ini +++ /dev/null @@ -1,1519 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=true -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=LinuxArmSystem -children=bridge disks clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler external_memory intrctrl iobus iocache l2 membus realview terminal tol2bus vncserver voltage_domain -atags_addr=134217728 -boot_loader=/Users/myzinsky/EMS/Programming/gem5.iso/binaries/boot_emm.arm -boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=512MB root=/dev/sda1 -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -dtb_filename=/Users/myzinsky/EMS/Programming/gem5.iso/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb -early_kernel_symbols=false -enable_context_switch_stats_dump=false -eventq_index=0 -exit_on_work_items=false -flags_addr=469827632 -gic_cpu_addr=738205696 -have_large_asid_64=false -have_lpae=true -have_security=false -have_virtualization=false -highest_el_is_64=false -init_param=0 -kernel=/Users/myzinsky/EMS/Programming/gem5.iso/binaries/vmlinux.aarch32.ll_20131205.0-gem5 -kernel_addr_check=false -load_addr_mask=268435455 -load_offset=2147483648 -m5ops_base=0 -machine_type=VExpress_EMM -mem_mode=timing -mem_ranges=2147483648:2684354559:0:0:0:0 -memories=system.realview.nvmem system.realview.vram -mmap_using_noreserve=false -multi_proc=true -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -panic_on_oops=false -panic_on_panic=false -phys_addr_range_64=40 -power_model=Null -readfile= -reset_addr_64=0 -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[1] - -[system.bridge] -type=Bridge -clk_domain=system.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -ranges=788529152:805306367:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0 -req_size=16 -resp_size=16 -master=system.iobus.slave[0] -slave=system.membus.master[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.tracer -workload= -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=65536 -system=system -tag_latency=2 -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.tol2bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=65536 -tag_latency=2 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.tol2bus.slave[3] - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.tol2bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 -tag_latency=2 - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -midr=1091551472 -pmu=Null -system=system -vecRegRenameMode=Full - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.tol2bus.slave[2] - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.cpu_voltage_domain - -[system.cpu_voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.external_memory] -type=ExternalSlave -addr_ranges=2147483648:2684354559:0:0:0:0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -port_data=transactor1 -port_type=tlm_slave -power_model=Null -port=system.membus.master[6] - -[system.intrctrl] -type=IntrControl -eventq_index=0 -sys=system - -[system.iobus] -type=NoncoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=1 -frontend_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -response_latency=2 -use_default_range=false -width=16 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ethernet.pio system.iocache.cpu_side -slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ethernet.dma - -[system.iocache] -type=Cache -children=tags -addr_ranges=2147483648:2684354559:0:0:0:0 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=50 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=50 -sequential_access=false -size=1024 -system=system -tag_latency=50 -tags=system.iocache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.iobus.master[22] -mem_side=system.membus.slave[2] - -[system.iocache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.clk_domain -data_latency=50 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=1024 -tag_latency=50 - -[system.l2] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=20 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tag_latency=20 -tags=system.l2.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.tol2bus.master[0] -mem_side=system.membus.slave[3] - -[system.l2.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=20 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 -tag_latency=20 - -[system.membus] -type=CoherentXBar -children=badaddr_responder snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.vgic.pio system.realview.local_cpu_timer.pio system.realview.hdlcd.pio system.external_memory.port -slave=system.realview.hdlcd.dma system.system_port system.iocache.mem_side system.l2.mem_side - -[system.membus.badaddr_responder] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=0 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access=warn -pio=system.membus.default - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.realview] -type=RealView -children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake -eventq_index=0 -intrctrl=system.intrctrl -system=system - -[system.realview.aaci_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470024192 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[16] - -[system.realview.cf_ctrl] -type=IdeController -BAR0=471465984 -BAR0LegacyIO=true -BAR0Size=256 -BAR1=471466240 -BAR1LegacyIO=true -BAR1Size=4096 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=1 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=2 -default_p_state=UNDEFINED -disks= -eventq_index=0 -host=system.realview.pci_host -io_shift=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=2 -pci_dev=0 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[2] -pio=system.iobus.master[8] - -[system.realview.clcd] -type=Pl111 -amba_id=1315089 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -enable_capture=true -eventq_index=0 -gic=system.realview.gic -int_num=46 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=471793664 -pio_latency=10000 -pixel_clock=41667 -power_model=Null -system=system -vnc=system.vncserver -dma=system.iobus.slave[1] -pio=system.iobus.master[5] - -[system.realview.dcc] -type=SubSystem -children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys -eventq_index=0 -thermal_domain=Null - -[system.realview.dcc.osc_cpu] -type=RealViewOsc -dcc=0 -device=0 -eventq_index=0 -freq=16667 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_ddr] -type=RealViewOsc -dcc=0 -device=8 -eventq_index=0 -freq=25000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_hsbm] -type=RealViewOsc -dcc=0 -device=4 -eventq_index=0 -freq=25000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_pxl] -type=RealViewOsc -dcc=0 -device=5 -eventq_index=0 -freq=42105 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_smb] -type=RealViewOsc -dcc=0 -device=6 -eventq_index=0 -freq=20000 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.dcc.osc_sys] -type=RealViewOsc -dcc=0 -device=7 -eventq_index=0 -freq=16667 -parent=system.realview.realview_io -position=0 -site=1 -voltage_domain=system.voltage_domain - -[system.realview.energy_ctrl] -type=EnergyCtrl -clk_domain=system.clk_domain -default_p_state=UNDEFINED -dvfs_handler=system.dvfs_handler -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470286336 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[20] - -[system.realview.ethernet] -type=IGbE -BAR0=0 -BAR0LegacyIO=false -BAR0Size=131072 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=0 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=4213 -ExpansionROM=0 -HeaderType=0 -InterruptLine=1 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=255 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=0 -Revision=0 -Status=0 -SubClassCode=0 -SubsystemID=4104 -SubsystemVendorID=32902 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -default_p_state=UNDEFINED -eventq_index=0 -fetch_comp_delay=10000 -fetch_delay=10000 -hardware_address=00:90:00:00:00:01 -host=system.realview.pci_host -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=0 -pci_func=0 -phy_epid=896 -phy_pid=680 -pio_latency=30000 -power_model=Null -rx_desc_cache_size=64 -rx_fifo_size=393216 -rx_write_delay=0 -system=system -tx_desc_cache_size=64 -tx_fifo_size=393216 -tx_read_delay=0 -wb_comp_delay=10000 -wb_delay=10000 -dma=system.iobus.slave[3] -pio=system.iobus.master[21] - -[system.realview.generic_timer] -type=GenericTimer -eventq_index=0 -gic=system.realview.gic -int_phys=29 -int_virt=27 -system=system - -[system.realview.gic] -type=Pl390 -clk_domain=system.clk_domain -cpu_addr=738205696 -cpu_pio_delay=10000 -default_p_state=UNDEFINED -dist_addr=738201600 -dist_pio_delay=10000 -eventq_index=0 -gem5_extensions=false -int_latency=10000 -it_lines=128 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -platform=system.realview -power_model=Null -system=system -pio=system.membus.master[2] - -[system.realview.hdlcd] -type=HDLcd -amba_id=1314816 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -enable_capture=true -eventq_index=0 -gic=system.realview.gic -int_num=117 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=721420288 -pio_latency=10000 -pixel_buffer_size=2048 -pixel_chunk=32 -power_model=Null -pxl_clk=system.realview.dcc.osc_pxl -system=system -virt_refresh_rate=50000000000 -vnc=system.vncserver -workaround_dma_line_count=true -workaround_swap_rb=true -dma=system.membus.slave[0] -pio=system.membus.master[5] - -[system.realview.ide] -type=ExternalSlave -children=disks -addr_ranges=0:67108863:0:0:0:0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -port_data=transactor2 -port_type=tlm_slave -power_model=Null - -[system.realview.ide.disks] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.realview.ide.disks.image - -[system.realview.ide.disks] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.realview.ide.disks.image - -[system.realview.ide.disks.image] -type=CowDiskImage -children=child -child=system.realview.ide.disks.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.realview.ide.disks.image] -type=CowDiskImage -children=child -child=system.realview.ide.disks.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.realview.ide.disks.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/Users/myzinsky/EMS/Programming/gem5.iso/disks/linux-aarch32-ael.img -read_only=true - -[system.realview.ide.disks.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/Users/myzinsky/EMS/Programming/gem5.iso/disks/linux-aarch32-ael.img -read_only=true - -[system.realview.kmi0] -type=Pl050 -amba_id=1314896 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=1000000 -int_num=44 -is_mouse=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470155264 -pio_latency=100000 -power_model=Null -system=system -vnc=system.vncserver -pio=system.iobus.master[6] - -[system.realview.kmi1] -type=Pl050 -amba_id=1314896 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=1000000 -int_num=45 -is_mouse=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470220800 -pio_latency=100000 -power_model=Null -system=system -vnc=system.vncserver -pio=system.iobus.master[7] - -[system.realview.l2x0_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=739246080 -pio_latency=100000 -pio_size=4095 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[10] - -[system.realview.lan_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=436207616 -pio_latency=100000 -pio_size=65535 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[17] - -[system.realview.local_cpu_timer] -type=CpuLocalTimer -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num_timer=29 -int_num_watchdog=30 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=738721792 -pio_latency=100000 -power_model=Null -system=system -pio=system.membus.master[4] - -[system.realview.mcc] -type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl -eventq_index=0 -thermal_domain=Null - -[system.realview.mcc.osc_clcd] -type=RealViewOsc -dcc=0 -device=1 -eventq_index=0 -freq=42105 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_mcc] -type=RealViewOsc -dcc=0 -device=0 -eventq_index=0 -freq=20000 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_peripheral] -type=RealViewOsc -dcc=0 -device=2 -eventq_index=0 -freq=41667 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.osc_system_bus] -type=RealViewOsc -dcc=0 -device=4 -eventq_index=0 -freq=41667 -parent=system.realview.realview_io -position=0 -site=0 -voltage_domain=system.voltage_domain - -[system.realview.mcc.temp_crtl] -type=RealViewTemperatureSensor -dcc=0 -device=0 -eventq_index=0 -parent=system.realview.realview_io -position=0 -site=0 -system=system - -[system.realview.mmc_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470089728 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[19] - -[system.realview.nvmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=false -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:67108863:0:0:0:0 -port=system.membus.master[1] - -[system.realview.pci_host] -type=GenericPciHost -clk_domain=system.clk_domain -conf_base=805306368 -conf_device_bits=16 -conf_size=268435456 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_dma_base=0 -pci_mem_base=0 -pci_pio_base=0 -platform=system.realview -power_model=Null -system=system -pio=system.iobus.master[2] - -[system.realview.realview_io] -type=RealViewCtrl -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -idreg=35979264 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=469827584 -pio_latency=100000 -power_model=Null -proc_id0=335544320 -proc_id1=335544320 -system=system -pio=system.iobus.master[1] - -[system.realview.rtc] -type=PL031 -amba_id=3412017 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_delay=100000 -int_num=36 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=471269376 -pio_latency=100000 -power_model=Null -system=system -time=Thu Jan 1 00:00:00 2009 -pio=system.iobus.master[9] - -[system.realview.sp810_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=469893120 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[14] - -[system.realview.timer0] -type=Sp804 -amba_id=1316868 -clk_domain=system.clk_domain -clock0=1000000 -clock1=1000000 -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num0=34 -int_num1=34 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470876160 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[3] - -[system.realview.timer1] -type=Sp804 -amba_id=1316868 -clk_domain=system.clk_domain -clock0=1000000 -clock1=1000000 -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -int_num0=35 -int_num1=35 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470941696 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[4] - -[system.realview.uart] -type=Pl011 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -end_on_eot=false -eventq_index=0 -gic=system.realview.gic -int_delay=100000 -int_num=37 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470351872 -pio_latency=100000 -platform=system.realview -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[0] - -[system.realview.uart1_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470417408 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[11] - -[system.realview.uart2_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470482944 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[12] - -[system.realview.uart3_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470548480 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[13] - -[system.realview.usb_fake] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=452984832 -pio_latency=100000 -pio_size=131071 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[18] - -[system.realview.vgic] -type=VGic -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -gic=system.realview.gic -hv_addr=738213888 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_delay=10000 -platform=system.realview -power_model=Null -ppint=25 -system=system -vcpu_addr=738222080 -pio=system.membus.master[3] - -[system.realview.vram] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=false -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=402653184:436207615:0:0:0:0 - -[system.realview.watchdog_fake] -type=AmbaFake -amba_id=0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -ignore_access=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=470745088 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[15] - -[system.terminal] -type=Terminal -eventq_index=0 -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.tol2bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.tol2bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.l2.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port - -[system.tol2bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.vncserver] -type=VncServer -eventq_index=0 -frame_capture=false -number=0 -port=5900 - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/DRAMSys/gem5/configs/singleElasticTraceReplay.dot.pdf b/DRAMSys/gem5/configs/singleElasticTraceReplay.dot.pdf deleted file mode 100644 index a11fdf37..00000000 Binary files a/DRAMSys/gem5/configs/singleElasticTraceReplay.dot.pdf and /dev/null differ diff --git a/DRAMSys/gem5/configs/singleElasticTraceReplay.ini b/DRAMSys/gem5/configs/singleElasticTraceReplay.ini deleted file mode 100644 index cec31376..00000000 --- a/DRAMSys/gem5/configs/singleElasticTraceReplay.ini +++ /dev/null @@ -1,448 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler membus physmem tlm voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -kernel_extras= -load_addr_mask=18446744073709551615 -load_offset=0 -mem_mode=timing -mem_ranges=0:536870911:0:0:0:0 -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TraceCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer -checker=Null -clk_domain=system.clk_domain -cpu_id=0 -dataTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.random.data.gz -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -enableEarlyExit=false -eventq_index=0 -freqMultiplier=1.0 -function_trace=false -function_trace_start=0 -instTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_gating_on_idle=false -power_model= -profile=0 -progressMsgInterval=0 -progress_interval=0 -pwr_gating_latency=300 -simpoint_start_insts= -sizeLoadBuffer=16 -sizeROB=40 -sizeStoreBuffer=16 -socket_id=0 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.tracer -wait_for_remote_gdb=false -workload= -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu.dcache.replacement_policy -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -warmup_percentage=0 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.membus.slave[2] - -[system.cpu.dcache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu.dcache.tags] -type=BaseSetAssoc -assoc=2 -block_size=64 -clk_domain=system.clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu.dcache.replacement_policy -sequential_access=false -size=32768 -tag_latency=2 -warmup_percentage=0 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.icache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu.icache.replacement_policy -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu.icache.tags -tgts_per_mshr=20 -warmup_percentage=0 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.membus.slave[1] - -[system.cpu.icache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu.icache.tags] -type=BaseSetAssoc -assoc=2 -block_size=64 -clk_domain=system.clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu.icache.replacement_policy -sequential_access=false -size=32768 -tag_latency=2 -warmup_percentage=0 - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -impdef_nop=false -midr=1091551472 -pmu=Null -system=system -vecRegRenameMode=Full - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.cpu_voltage_domain - -[system.cpu_voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.0 - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -point_of_unification=true -power_model= -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.tlm.port -slave=system.system_port system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -range=0:134217727:0:0:0:0 - -[system.tlm] -type=ExternalSlave -addr_ranges=0:536870911:0:0:0:0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -port_data=transactor -port_type=tlm_slave -power_model= -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.0 - diff --git a/DRAMSys/gem5/configs/singleElasticTraceReplayWithL2.dot.pdf b/DRAMSys/gem5/configs/singleElasticTraceReplayWithL2.dot.pdf deleted file mode 100644 index f7e3d3f9..00000000 Binary files a/DRAMSys/gem5/configs/singleElasticTraceReplayWithL2.dot.pdf and /dev/null differ diff --git a/DRAMSys/gem5/configs/singleElasticTraceReplayWithL2.ini b/DRAMSys/gem5/configs/singleElasticTraceReplayWithL2.ini deleted file mode 100644 index 5e8ef16a..00000000 --- a/DRAMSys/gem5/configs/singleElasticTraceReplayWithL2.ini +++ /dev/null @@ -1,534 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2cache membus physmem tlm tol2bus voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -kernel_extras= -load_addr_mask=18446744073709551615 -load_offset=0 -mem_mode=timing -mem_ranges=0:1073741823:0:0:0:0 -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TraceCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer -checker=Null -clk_domain=system.clk_domain -cpu_id=0 -dataTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -enableEarlyExit=false -eventq_index=0 -freqMultiplier=1.0 -function_trace=false -function_trace_start=0 -instTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_gating_on_idle=false -power_model= -profile=0 -progressMsgInterval=0 -progress_interval=0 -pwr_gating_latency=300 -simpoint_start_insts= -sizeLoadBuffer=16 -sizeROB=40 -sizeStoreBuffer=16 -socket_id=0 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.tracer -wait_for_remote_gdb=false -workload= -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu.dcache.replacement_policy -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -warmup_percentage=0 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.tol2bus.slave[1] - -[system.cpu.dcache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu.dcache.tags] -type=BaseSetAssoc -assoc=2 -block_size=64 -clk_domain=system.clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu.dcache.replacement_policy -sequential_access=false -size=32768 -tag_latency=2 -warmup_percentage=0 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.icache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu.icache.replacement_policy -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu.icache.tags -tgts_per_mshr=20 -warmup_percentage=0 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.tol2bus.slave[0] - -[system.cpu.icache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu.icache.tags] -type=BaseSetAssoc -assoc=2 -block_size=64 -clk_domain=system.clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu.icache.replacement_policy -sequential_access=false -size=32768 -tag_latency=2 -warmup_percentage=0 - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -impdef_nop=false -midr=1091551472 -pmu=Null -system=system -vecRegRenameMode=Full - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.cpu_voltage_domain - -[system.cpu_voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.0 - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.l2cache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=20 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.l2cache.replacement_policy -response_latency=20 -sequential_access=false -size=1048576 -system=system -tag_latency=20 -tags=system.l2cache.tags -tgts_per_mshr=12 -warmup_percentage=0 -write_buffers=8 -writeback_clean=false -cpu_side=system.tol2bus.master[0] -mem_side=system.membus.slave[1] - -[system.l2cache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.l2cache.tags] -type=BaseSetAssoc -assoc=8 -block_size=64 -clk_domain=system.clk_domain -data_latency=20 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.l2cache.replacement_policy -sequential_access=false -size=1048576 -tag_latency=20 -warmup_percentage=0 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -point_of_unification=true -power_model= -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.tlm.port -slave=system.system_port system.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -range=0:134217727:0:0:0:0 - -[system.tlm] -type=ExternalSlave -addr_ranges=0:4294967295:0:0:0:0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -port_data=transactor -port_type=tlm_slave -power_model= -port=system.membus.master[0] - -[system.tol2bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -point_of_unification=true -power_model= -response_latency=1 -snoop_filter=system.tol2bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.tol2bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.0 - diff --git a/DRAMSys/gem5/etrace_single/config.ini b/DRAMSys/gem5/etrace_single/config.ini deleted file mode 100644 index cec31376..00000000 --- a/DRAMSys/gem5/etrace_single/config.ini +++ /dev/null @@ -1,448 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler membus physmem tlm voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -kernel_extras= -load_addr_mask=18446744073709551615 -load_offset=0 -mem_mode=timing -mem_ranges=0:536870911:0:0:0:0 -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TraceCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer -checker=Null -clk_domain=system.clk_domain -cpu_id=0 -dataTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.random.data.gz -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -enableEarlyExit=false -eventq_index=0 -freqMultiplier=1.0 -function_trace=false -function_trace_start=0 -instTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_gating_on_idle=false -power_model= -profile=0 -progressMsgInterval=0 -progress_interval=0 -pwr_gating_latency=300 -simpoint_start_insts= -sizeLoadBuffer=16 -sizeROB=40 -sizeStoreBuffer=16 -socket_id=0 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.tracer -wait_for_remote_gdb=false -workload= -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu.dcache.replacement_policy -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -warmup_percentage=0 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.membus.slave[2] - -[system.cpu.dcache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu.dcache.tags] -type=BaseSetAssoc -assoc=2 -block_size=64 -clk_domain=system.clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu.dcache.replacement_policy -sequential_access=false -size=32768 -tag_latency=2 -warmup_percentage=0 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.icache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu.icache.replacement_policy -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu.icache.tags -tgts_per_mshr=20 -warmup_percentage=0 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.membus.slave[1] - -[system.cpu.icache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu.icache.tags] -type=BaseSetAssoc -assoc=2 -block_size=64 -clk_domain=system.clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu.icache.replacement_policy -sequential_access=false -size=32768 -tag_latency=2 -warmup_percentage=0 - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -impdef_nop=false -midr=1091551472 -pmu=Null -system=system -vecRegRenameMode=Full - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.cpu_voltage_domain - -[system.cpu_voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.0 - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -point_of_unification=true -power_model= -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.tlm.port -slave=system.system_port system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -range=0:134217727:0:0:0:0 - -[system.tlm] -type=ExternalSlave -addr_ranges=0:536870911:0:0:0:0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -port_data=transactor -port_type=tlm_slave -power_model= -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.0 - diff --git a/DRAMSys/gem5/etrace_single_L2/HPCG-47MB/config.ini b/DRAMSys/gem5/etrace_single_L2/HPCG-47MB/config.ini deleted file mode 100644 index 9fa2a700..00000000 --- a/DRAMSys/gem5/etrace_single_L2/HPCG-47MB/config.ini +++ /dev/null @@ -1,534 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2cache membus physmem tlm tol2bus voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -kernel_extras= -load_addr_mask=18446744073709551615 -load_offset=0 -mem_mode=timing -mem_ranges=0:1073741823:0:0:0:0 -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TraceCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer -checker=Null -clk_domain=system.clk_domain -cpu_id=0 -dataTraceFile=/media/disk2/traces/2016_07_Traces/2015_09_08/hpc_simpoints/HPCG-47MB-simpoints-1B/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.data.itrc.gz -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -enableEarlyExit=false -eventq_index=0 -freqMultiplier=1.0 -function_trace=false -function_trace_start=0 -instTraceFile=/media/disk2/traces/2016_07_Traces/2015_09_08/hpc_simpoints/HPCG-47MB-simpoints-1B/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.inst.ptrc.gz -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_gating_on_idle=false -power_model= -profile=0 -progressMsgInterval=0 -progress_interval=0 -pwr_gating_latency=300 -simpoint_start_insts= -sizeLoadBuffer=16 -sizeROB=40 -sizeStoreBuffer=16 -socket_id=0 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.tracer -wait_for_remote_gdb=false -workload= -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu.dcache.replacement_policy -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -warmup_percentage=0 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.tol2bus.slave[1] - -[system.cpu.dcache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu.dcache.tags] -type=BaseSetAssoc -assoc=2 -block_size=64 -clk_domain=system.clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu.dcache.replacement_policy -sequential_access=false -size=32768 -tag_latency=2 -warmup_percentage=0 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.icache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu.icache.replacement_policy -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu.icache.tags -tgts_per_mshr=20 -warmup_percentage=0 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.tol2bus.slave[0] - -[system.cpu.icache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu.icache.tags] -type=BaseSetAssoc -assoc=2 -block_size=64 -clk_domain=system.clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu.icache.replacement_policy -sequential_access=false -size=32768 -tag_latency=2 -warmup_percentage=0 - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -impdef_nop=false -midr=1091551472 -pmu=Null -system=system -vecRegRenameMode=Full - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.cpu_voltage_domain - -[system.cpu_voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.0 - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.l2cache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=20 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.l2cache.replacement_policy -response_latency=20 -sequential_access=false -size=1048576 -system=system -tag_latency=20 -tags=system.l2cache.tags -tgts_per_mshr=12 -warmup_percentage=0 -write_buffers=8 -writeback_clean=false -cpu_side=system.tol2bus.master[0] -mem_side=system.membus.slave[1] - -[system.l2cache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.l2cache.tags] -type=BaseSetAssoc -assoc=8 -block_size=64 -clk_domain=system.clk_domain -data_latency=20 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.l2cache.replacement_policy -sequential_access=false -size=1048576 -tag_latency=20 -warmup_percentage=0 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -point_of_unification=true -power_model= -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.tlm.port -slave=system.system_port system.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -range=0:134217727:0:0:0:0 - -[system.tlm] -type=ExternalSlave -addr_ranges=0:4294967295:0:0:0:0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -port_data=transactor -port_type=tlm_slave -power_model= -port=system.membus.master[0] - -[system.tol2bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -point_of_unification=true -power_model= -response_latency=1 -snoop_filter=system.tol2bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.tol2bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.0 - diff --git a/DRAMSys/gem5/etrace_single_L2/Pathfinder/config.ini b/DRAMSys/gem5/etrace_single_L2/Pathfinder/config.ini deleted file mode 100644 index 3c4db357..00000000 --- a/DRAMSys/gem5/etrace_single_L2/Pathfinder/config.ini +++ /dev/null @@ -1,534 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2cache membus physmem tlm tol2bus voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -kernel_extras= -load_addr_mask=18446744073709551615 -load_offset=0 -mem_mode=timing -mem_ranges=0:1073741823:0:0:0:0 -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TraceCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer -checker=Null -clk_domain=system.clk_domain -cpu_id=0 -dataTraceFile=/media/disk2/traces/2016_07_Traces/2015_09_08/hpc_simpoints/Pathfinder-medsmall1-simpoints-1B-1sim/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.data.itrc.gz -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -enableEarlyExit=false -eventq_index=0 -freqMultiplier=1.0 -function_trace=false -function_trace_start=0 -instTraceFile=/media/disk2/traces/2016_07_Traces/2015_09_08/hpc_simpoints/Pathfinder-medsmall1-simpoints-1B-1sim/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.inst.ptrc.gz -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_gating_on_idle=false -power_model= -profile=0 -progressMsgInterval=0 -progress_interval=0 -pwr_gating_latency=300 -simpoint_start_insts= -sizeLoadBuffer=16 -sizeROB=40 -sizeStoreBuffer=16 -socket_id=0 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.tracer -wait_for_remote_gdb=false -workload= -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu.dcache.replacement_policy -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -warmup_percentage=0 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.tol2bus.slave[1] - -[system.cpu.dcache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu.dcache.tags] -type=BaseSetAssoc -assoc=2 -block_size=64 -clk_domain=system.clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu.dcache.replacement_policy -sequential_access=false -size=32768 -tag_latency=2 -warmup_percentage=0 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.icache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu.icache.replacement_policy -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu.icache.tags -tgts_per_mshr=20 -warmup_percentage=0 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.tol2bus.slave[0] - -[system.cpu.icache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu.icache.tags] -type=BaseSetAssoc -assoc=2 -block_size=64 -clk_domain=system.clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu.icache.replacement_policy -sequential_access=false -size=32768 -tag_latency=2 -warmup_percentage=0 - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -impdef_nop=false -midr=1091551472 -pmu=Null -system=system -vecRegRenameMode=Full - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.cpu_voltage_domain - -[system.cpu_voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.0 - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.l2cache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=20 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.l2cache.replacement_policy -response_latency=20 -sequential_access=false -size=1048576 -system=system -tag_latency=20 -tags=system.l2cache.tags -tgts_per_mshr=12 -warmup_percentage=0 -write_buffers=8 -writeback_clean=false -cpu_side=system.tol2bus.master[0] -mem_side=system.membus.slave[1] - -[system.l2cache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.l2cache.tags] -type=BaseSetAssoc -assoc=8 -block_size=64 -clk_domain=system.clk_domain -data_latency=20 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.l2cache.replacement_policy -sequential_access=false -size=1048576 -tag_latency=20 -warmup_percentage=0 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -point_of_unification=true -power_model= -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.tlm.port -slave=system.system_port system.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -range=0:134217727:0:0:0:0 - -[system.tlm] -type=ExternalSlave -addr_ranges=0:4294967295:0:0:0:0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -port_data=transactor -port_type=tlm_slave -power_model= -port=system.membus.master[0] - -[system.tol2bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -point_of_unification=true -power_model= -response_latency=1 -snoop_filter=system.tol2bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.tol2bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.0 - diff --git a/DRAMSys/gem5/etrace_single_L2/config.ini b/DRAMSys/gem5/etrace_single_L2/config.ini deleted file mode 100644 index 5e8ef16a..00000000 --- a/DRAMSys/gem5/etrace_single_L2/config.ini +++ /dev/null @@ -1,534 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2cache membus physmem tlm tol2bus voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -kernel_extras= -load_addr_mask=18446744073709551615 -load_offset=0 -mem_mode=timing -mem_ranges=0:1073741823:0:0:0:0 -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TraceCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer -checker=Null -clk_domain=system.clk_domain -cpu_id=0 -dataTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -enableEarlyExit=false -eventq_index=0 -freqMultiplier=1.0 -function_trace=false -function_trace_start=0 -instTraceFile=../../DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_gating_on_idle=false -power_model= -profile=0 -progressMsgInterval=0 -progress_interval=0 -pwr_gating_latency=300 -simpoint_start_insts= -sizeLoadBuffer=16 -sizeROB=40 -sizeStoreBuffer=16 -socket_id=0 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.tracer -wait_for_remote_gdb=false -workload= -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu.dcache.replacement_policy -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -warmup_percentage=0 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.tol2bus.slave[1] - -[system.cpu.dcache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu.dcache.tags] -type=BaseSetAssoc -assoc=2 -block_size=64 -clk_domain=system.clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu.dcache.replacement_policy -sequential_access=false -size=32768 -tag_latency=2 -warmup_percentage=0 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.icache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu.icache.replacement_policy -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu.icache.tags -tgts_per_mshr=20 -warmup_percentage=0 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.tol2bus.slave[0] - -[system.cpu.icache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu.icache.tags] -type=BaseSetAssoc -assoc=2 -block_size=64 -clk_domain=system.clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu.icache.replacement_policy -sequential_access=false -size=32768 -tag_latency=2 -warmup_percentage=0 - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -impdef_nop=false -midr=1091551472 -pmu=Null -system=system -vecRegRenameMode=Full - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.cpu_voltage_domain - -[system.cpu_voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.0 - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.l2cache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=20 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.l2cache.replacement_policy -response_latency=20 -sequential_access=false -size=1048576 -system=system -tag_latency=20 -tags=system.l2cache.tags -tgts_per_mshr=12 -warmup_percentage=0 -write_buffers=8 -writeback_clean=false -cpu_side=system.tol2bus.master[0] -mem_side=system.membus.slave[1] - -[system.l2cache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.l2cache.tags] -type=BaseSetAssoc -assoc=8 -block_size=64 -clk_domain=system.clk_domain -data_latency=20 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.l2cache.replacement_policy -sequential_access=false -size=1048576 -tag_latency=20 -warmup_percentage=0 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -point_of_unification=true -power_model= -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.tlm.port -slave=system.system_port system.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -range=0:134217727:0:0:0:0 - -[system.tlm] -type=ExternalSlave -addr_ranges=0:4294967295:0:0:0:0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -port_data=transactor -port_type=tlm_slave -power_model= -port=system.membus.master[0] - -[system.tol2bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -point_of_unification=true -power_model= -response_latency=1 -snoop_filter=system.tol2bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.tol2bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.0 - diff --git a/DRAMSys/gem5/etrace_single_L2/hpcc-dgemm/config.ini b/DRAMSys/gem5/etrace_single_L2/hpcc-dgemm/config.ini deleted file mode 100644 index eccee094..00000000 --- a/DRAMSys/gem5/etrace_single_L2/hpcc-dgemm/config.ini +++ /dev/null @@ -1,534 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2cache membus physmem tlm tol2bus voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -kernel_extras= -load_addr_mask=18446744073709551615 -load_offset=0 -mem_mode=timing -mem_ranges=0:1073741823:0:0:0:0 -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TraceCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer -checker=Null -clk_domain=system.clk_domain -cpu_id=0 -dataTraceFile=/media/disk2/traces/2016_07_Traces/2015_09_08/hpc_simpoints/hpcc-dgemm-simpoints-1B/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.data.itrc.gz -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -enableEarlyExit=false -eventq_index=0 -freqMultiplier=1.0 -function_trace=false -function_trace_start=0 -instTraceFile=/media/disk2/traces/2016_07_Traces/2015_09_08/hpc_simpoints/hpcc-dgemm-simpoints-1B/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.inst.ptrc.gz -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_gating_on_idle=false -power_model= -profile=0 -progressMsgInterval=0 -progress_interval=0 -pwr_gating_latency=300 -simpoint_start_insts= -sizeLoadBuffer=16 -sizeROB=40 -sizeStoreBuffer=16 -socket_id=0 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.tracer -wait_for_remote_gdb=false -workload= -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu.dcache.replacement_policy -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -warmup_percentage=0 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.tol2bus.slave[1] - -[system.cpu.dcache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu.dcache.tags] -type=BaseSetAssoc -assoc=2 -block_size=64 -clk_domain=system.clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu.dcache.replacement_policy -sequential_access=false -size=32768 -tag_latency=2 -warmup_percentage=0 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.icache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu.icache.replacement_policy -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu.icache.tags -tgts_per_mshr=20 -warmup_percentage=0 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.tol2bus.slave[0] - -[system.cpu.icache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu.icache.tags] -type=BaseSetAssoc -assoc=2 -block_size=64 -clk_domain=system.clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu.icache.replacement_policy -sequential_access=false -size=32768 -tag_latency=2 -warmup_percentage=0 - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -impdef_nop=false -midr=1091551472 -pmu=Null -system=system -vecRegRenameMode=Full - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.cpu_voltage_domain - -[system.cpu_voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.0 - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.l2cache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=20 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.l2cache.replacement_policy -response_latency=20 -sequential_access=false -size=1048576 -system=system -tag_latency=20 -tags=system.l2cache.tags -tgts_per_mshr=12 -warmup_percentage=0 -write_buffers=8 -writeback_clean=false -cpu_side=system.tol2bus.master[0] -mem_side=system.membus.slave[1] - -[system.l2cache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.l2cache.tags] -type=BaseSetAssoc -assoc=8 -block_size=64 -clk_domain=system.clk_domain -data_latency=20 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.l2cache.replacement_policy -sequential_access=false -size=1048576 -tag_latency=20 -warmup_percentage=0 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -point_of_unification=true -power_model= -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.tlm.port -slave=system.system_port system.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -range=0:134217727:0:0:0:0 - -[system.tlm] -type=ExternalSlave -addr_ranges=0:4294967295:0:0:0:0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -port_data=transactor -port_type=tlm_slave -power_model= -port=system.membus.master[0] - -[system.tol2bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -point_of_unification=true -power_model= -response_latency=1 -snoop_filter=system.tol2bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.tol2bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.0 - diff --git a/DRAMSys/gem5/etrace_single_L2/hpcc-fft/config.ini b/DRAMSys/gem5/etrace_single_L2/hpcc-fft/config.ini deleted file mode 100644 index 86c95ecd..00000000 --- a/DRAMSys/gem5/etrace_single_L2/hpcc-fft/config.ini +++ /dev/null @@ -1,534 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2cache membus physmem tlm tol2bus voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -kernel_extras= -load_addr_mask=18446744073709551615 -load_offset=0 -mem_mode=timing -mem_ranges=0:1073741823:0:0:0:0 -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TraceCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer -checker=Null -clk_domain=system.clk_domain -cpu_id=0 -dataTraceFile=/media/disk2/traces/2016_07_Traces/2015_09_08/hpc_simpoints/hpcc-fft/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.data.itrc.gz -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -enableEarlyExit=false -eventq_index=0 -freqMultiplier=1.0 -function_trace=false -function_trace_start=0 -instTraceFile=/media/disk2/traces/2016_07_Traces/2015_09_08/hpc_simpoints/hpcc-fft/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.inst.ptrc.gz -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_gating_on_idle=false -power_model= -profile=0 -progressMsgInterval=0 -progress_interval=0 -pwr_gating_latency=300 -simpoint_start_insts= -sizeLoadBuffer=16 -sizeROB=40 -sizeStoreBuffer=16 -socket_id=0 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.tracer -wait_for_remote_gdb=false -workload= -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu.dcache.replacement_policy -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -warmup_percentage=0 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.tol2bus.slave[1] - -[system.cpu.dcache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu.dcache.tags] -type=BaseSetAssoc -assoc=2 -block_size=64 -clk_domain=system.clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu.dcache.replacement_policy -sequential_access=false -size=32768 -tag_latency=2 -warmup_percentage=0 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.icache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu.icache.replacement_policy -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu.icache.tags -tgts_per_mshr=20 -warmup_percentage=0 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.tol2bus.slave[0] - -[system.cpu.icache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu.icache.tags] -type=BaseSetAssoc -assoc=2 -block_size=64 -clk_domain=system.clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu.icache.replacement_policy -sequential_access=false -size=32768 -tag_latency=2 -warmup_percentage=0 - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -impdef_nop=false -midr=1091551472 -pmu=Null -system=system -vecRegRenameMode=Full - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.cpu_voltage_domain - -[system.cpu_voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.0 - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.l2cache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=20 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.l2cache.replacement_policy -response_latency=20 -sequential_access=false -size=1048576 -system=system -tag_latency=20 -tags=system.l2cache.tags -tgts_per_mshr=12 -warmup_percentage=0 -write_buffers=8 -writeback_clean=false -cpu_side=system.tol2bus.master[0] -mem_side=system.membus.slave[1] - -[system.l2cache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.l2cache.tags] -type=BaseSetAssoc -assoc=8 -block_size=64 -clk_domain=system.clk_domain -data_latency=20 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.l2cache.replacement_policy -sequential_access=false -size=1048576 -tag_latency=20 -warmup_percentage=0 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -point_of_unification=true -power_model= -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.tlm.port -slave=system.system_port system.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -range=0:134217727:0:0:0:0 - -[system.tlm] -type=ExternalSlave -addr_ranges=0:4294967295:0:0:0:0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -port_data=transactor -port_type=tlm_slave -power_model= -port=system.membus.master[0] - -[system.tol2bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -point_of_unification=true -power_model= -response_latency=1 -snoop_filter=system.tol2bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.tol2bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.0 - diff --git a/DRAMSys/gem5/etrace_single_L2/hpcc-gups/config.ini b/DRAMSys/gem5/etrace_single_L2/hpcc-gups/config.ini deleted file mode 100644 index 9ff3f326..00000000 --- a/DRAMSys/gem5/etrace_single_L2/hpcc-gups/config.ini +++ /dev/null @@ -1,534 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2cache membus physmem tlm tol2bus voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -kernel_extras= -load_addr_mask=18446744073709551615 -load_offset=0 -mem_mode=timing -mem_ranges=0:1073741823:0:0:0:0 -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TraceCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer -checker=Null -clk_domain=system.clk_domain -cpu_id=0 -dataTraceFile=/media/disk2/traces/2016_07_Traces/2015_09_08/hpc_simpoints/hpcc-gups/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.data.itrc.gz -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -enableEarlyExit=false -eventq_index=0 -freqMultiplier=1.0 -function_trace=false -function_trace_start=0 -instTraceFile=/media/disk2/traces/2016_07_Traces/2015_09_08/hpc_simpoints/hpcc-gups/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.inst.ptrc.gz -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_gating_on_idle=false -power_model= -profile=0 -progressMsgInterval=0 -progress_interval=0 -pwr_gating_latency=300 -simpoint_start_insts= -sizeLoadBuffer=16 -sizeROB=40 -sizeStoreBuffer=16 -socket_id=0 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.tracer -wait_for_remote_gdb=false -workload= -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu.dcache.replacement_policy -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -warmup_percentage=0 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.tol2bus.slave[1] - -[system.cpu.dcache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu.dcache.tags] -type=BaseSetAssoc -assoc=2 -block_size=64 -clk_domain=system.clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu.dcache.replacement_policy -sequential_access=false -size=32768 -tag_latency=2 -warmup_percentage=0 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.icache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu.icache.replacement_policy -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu.icache.tags -tgts_per_mshr=20 -warmup_percentage=0 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.tol2bus.slave[0] - -[system.cpu.icache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu.icache.tags] -type=BaseSetAssoc -assoc=2 -block_size=64 -clk_domain=system.clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu.icache.replacement_policy -sequential_access=false -size=32768 -tag_latency=2 -warmup_percentage=0 - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -impdef_nop=false -midr=1091551472 -pmu=Null -system=system -vecRegRenameMode=Full - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.cpu_voltage_domain - -[system.cpu_voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.0 - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.l2cache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=20 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.l2cache.replacement_policy -response_latency=20 -sequential_access=false -size=1048576 -system=system -tag_latency=20 -tags=system.l2cache.tags -tgts_per_mshr=12 -warmup_percentage=0 -write_buffers=8 -writeback_clean=false -cpu_side=system.tol2bus.master[0] -mem_side=system.membus.slave[1] - -[system.l2cache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.l2cache.tags] -type=BaseSetAssoc -assoc=8 -block_size=64 -clk_domain=system.clk_domain -data_latency=20 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.l2cache.replacement_policy -sequential_access=false -size=1048576 -tag_latency=20 -warmup_percentage=0 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -point_of_unification=true -power_model= -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.tlm.port -slave=system.system_port system.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -range=0:134217727:0:0:0:0 - -[system.tlm] -type=ExternalSlave -addr_ranges=0:4294967295:0:0:0:0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -port_data=transactor -port_type=tlm_slave -power_model= -port=system.membus.master[0] - -[system.tol2bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -point_of_unification=true -power_model= -response_latency=1 -snoop_filter=system.tol2bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.tol2bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.0 - diff --git a/DRAMSys/gem5/etrace_single_L2/hpcc-linpack/config.ini b/DRAMSys/gem5/etrace_single_L2/hpcc-linpack/config.ini deleted file mode 100644 index 7885c812..00000000 --- a/DRAMSys/gem5/etrace_single_L2/hpcc-linpack/config.ini +++ /dev/null @@ -1,534 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler l2cache membus physmem tlm tol2bus voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -kernel_extras= -load_addr_mask=18446744073709551615 -load_offset=0 -mem_mode=timing -mem_ranges=0:1073741823:0:0:0:0 -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TraceCPU -children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer -checker=Null -clk_domain=system.clk_domain -cpu_id=0 -dataTraceFile=/media/disk2/traces/2016_07_Traces/2015_09_08/hpc_simpoints/hpcc-linpack-simpoints-1B/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.data.itrc.gz -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -enableEarlyExit=false -eventq_index=0 -freqMultiplier=1.0 -function_trace=false -function_trace_start=0 -instTraceFile=/media/disk2/traces/2016_07_Traces/2015_09_08/hpc_simpoints/hpcc-linpack-simpoints-1B/l1-base_l2-none_l3-base_mem-simple1/system.cluster.cpu.ElasticTrace.inst.ptrc.gz -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_gating_on_idle=false -power_model= -profile=0 -progressMsgInterval=0 -progress_interval=0 -pwr_gating_latency=300 -simpoint_start_insts= -sizeLoadBuffer=16 -sizeROB=40 -sizeStoreBuffer=16 -socket_id=0 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.tracer -wait_for_remote_gdb=false -workload= -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu.dcache.replacement_policy -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -warmup_percentage=0 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.tol2bus.slave[1] - -[system.cpu.dcache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu.dcache.tags] -type=BaseSetAssoc -assoc=2 -block_size=64 -clk_domain=system.clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu.dcache.replacement_policy -sequential_access=false -size=32768 -tag_latency=2 -warmup_percentage=0 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.icache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu.icache.replacement_policy -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu.icache.tags -tgts_per_mshr=20 -warmup_percentage=0 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.tol2bus.slave[0] - -[system.cpu.icache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu.icache.tags] -type=BaseSetAssoc -assoc=2 -block_size=64 -clk_domain=system.clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu.icache.replacement_policy -sequential_access=false -size=32768 -tag_latency=2 -warmup_percentage=0 - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -impdef_nop=false -midr=1091551472 -pmu=Null -system=system -vecRegRenameMode=Full - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -sys=system -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.cpu_voltage_domain - -[system.cpu_voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.0 - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.l2cache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -data_latency=20 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.l2cache.replacement_policy -response_latency=20 -sequential_access=false -size=1048576 -system=system -tag_latency=20 -tags=system.l2cache.tags -tgts_per_mshr=12 -warmup_percentage=0 -write_buffers=8 -writeback_clean=false -cpu_side=system.tol2bus.master[0] -mem_side=system.membus.slave[1] - -[system.l2cache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.l2cache.tags] -type=BaseSetAssoc -assoc=8 -block_size=64 -clk_domain=system.clk_domain -data_latency=20 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.l2cache.replacement_policy -sequential_access=false -size=1048576 -tag_latency=20 -warmup_percentage=0 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -point_of_unification=true -power_model= -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.tlm.port -slave=system.system_port system.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -range=0:134217727:0:0:0:0 - -[system.tlm] -type=ExternalSlave -addr_ranges=0:4294967295:0:0:0:0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -port_data=transactor -port_type=tlm_slave -power_model= -port=system.membus.master[0] - -[system.tol2bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -point_of_unification=true -power_model= -response_latency=1 -snoop_filter=system.tol2bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.tol2bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.0 - diff --git a/DRAMSys/gem5/examples/tlm_elastic_slave.py b/DRAMSys/gem5/examples/tlm_elastic_slave.py deleted file mode 100644 index 488251f4..00000000 --- a/DRAMSys/gem5/examples/tlm_elastic_slave.py +++ /dev/null @@ -1,126 +0,0 @@ -# Copyright (c) 2016, Technische Universität Kaiserslautern -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the copyright holder nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Matthias Jung - -import m5 -import optparse - -from m5.objects import * -from m5.util import addToPath, fatal - -addToPath('../../../configs/common/') - -from Caches import * - -# This configuration shows a simple setup of a Elastic Trace Player (eTraceCPU) -# and an external TLM port for SystemC co-simulation. -# -# We assume a DRAM size of 512MB and L1 cache sizes of 32KB. -# -# Base System Architecture: -# -# +-----------+ ^ -# +-------------+ | eTraceCPU | | -# | System Port | +-----+-----+ | -# +------+------+ | $D1 | $I1 | | -# | +--+--+--+--+ | -# | | | | gem5 World -# | | | | (see this file) -# | | | | -# +------v------------v-----v--+ | -# | Membus | v -# +----------------+-----------+ External Port (see sc_port.*) -# | ^ -# +---v---+ | TLM World -# | TLM | | (see sc_target.*) -# +-------+ v -# -# -# Create a system with a Crossbar and an Elastic Trace Player as CPU: - -# Setup System: -system = System(cpu=TraceCPU(cpu_id=0), - mem_mode='timing', - mem_ranges = [AddrRange('512MB')], - cache_line_size = 64) - -# Create a top-level voltage domain: -system.voltage_domain = VoltageDomain() - -# Create a source clock for the system. This is used as the clock period for -# xbar and memory: -system.clk_domain = SrcClockDomain(clock = '1GHz', - voltage_domain = system.voltage_domain) - -system.cpu.createThreads() - -# Create a CPU voltage domain: -system.cpu_voltage_domain = VoltageDomain() - -# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock -# is actually used only by the caches connected to the CPU: -system.cpu_clk_domain = SrcClockDomain(clock = '1GHz', - voltage_domain = system.cpu_voltage_domain) - -# Setup CPU and its L1 caches: -system.cpu.createInterruptController() -system.cpu.icache = L1_ICache(size="32kB") -system.cpu.dcache = L1_DCache(size="32kB") -system.cpu.icache.cpu_side = system.cpu.icache_port -system.cpu.dcache.cpu_side = system.cpu.dcache_port - -# XXX: Assign input trace files to the eTraceCPU (you have to set this path -# properly before running gem5): -system.cpu.instTraceFile="dram.sys/DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz" -system.cpu.dataTraceFile="dram.sys/DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz" - -# Setting up L1 BUS: -system.membus = IOXBar(width = 16) -system.physmem = SimpleMemory() # This must be instantiated, even if not needed - -# Create a external TLM port: -system.tlm = ExternalSlave() -system.tlm.addr_ranges = [AddrRange('512MB')] -system.tlm.port_type = "tlm_slave" -system.tlm.port_data = "transactor" - -# Connect everything: -system.membus = SystemXBar() -system.system_port = system.membus.slave -system.cpu.icache.mem_side = system.membus.slave -system.cpu.dcache.mem_side = system.membus.slave -system.membus.master = system.tlm.port - -# Start the simulation: -root = Root(full_system = False, system = system) -root.system.mem_mode = 'timing' -m5.instantiate() -m5.simulate() #Simulation time specified later on commandline diff --git a/DRAMSys/gem5/examples/tlm_elastic_slave_mc_direct.py b/DRAMSys/gem5/examples/tlm_elastic_slave_mc_direct.py deleted file mode 100644 index 6d660437..00000000 --- a/DRAMSys/gem5/examples/tlm_elastic_slave_mc_direct.py +++ /dev/null @@ -1,145 +0,0 @@ -# Copyright (c) 2016, Technische Universität Kaiserslautern -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the copyright holder nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Matthias Jung - -import m5 -import optparse - -from m5.objects import * -from m5.util import addToPath, fatal - -addToPath('../../../configs/common/') - -from Caches import * - -# This configuration shows a simple setup of a Elastic Trace Player (eTraceCPU) -# and an external TLM port for SystemC co-simulation. -# -# We assume a DRAM size of 512MB and L1 cache sizes of 32KB. -# -# Base System Architecture: -# -# +--------+ +-----------+ +-----------+ ^ -# | System | | eTraceCPU | | eTraceCPU | | -# | Port | +-----+-----+ +-----+-----+ | -# +----+---+ | $D1 | $I1 | | $D1 | $I1 | | -# | +--+--+--+--+ +--+--+--+--+ | -# | | | | | | gem5 World -# | | | | | | (see this file) -# | | | | | | -# +----v--------v-----v--------v-----v-+ | -# | Membus | v -# +----------------+-------------------+ External Port (see sc_port.*) -# | ^ -# +---v---+ | TLM World -# | TLM | | (see sc_target.*) -# +-------+ v -# -# -# Create a system with a Crossbar and Elastic Trace Player CPUs: - -# Setup System: -system = System(cpu=[TraceCPU(cpu_id=i) for i in xrange(2)], - mem_mode='timing', - mem_ranges = [AddrRange('512MB')], - cache_line_size = 64) - -# Create a top-level voltage domain: -system.voltage_domain = VoltageDomain() - -# Create a source clock for the system. This is used as the clock period for -# xbar and memory: -system.clk_domain = SrcClockDomain(clock = '1GHz', - voltage_domain = system.voltage_domain) - -# Create a CPU voltage domain: -system.cpu_voltage_domain = VoltageDomain() - -# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock -# is actually used only by the caches connected to the CPU: -system.cpu_clk_domain = SrcClockDomain(clock = '1GHz', - voltage_domain = system.cpu_voltage_domain) - -# Setup CPUs and their L1 caches: -system.cpu[0].createInterruptController() -system.cpu[0].icache = L1_ICache(size="32kB") -system.cpu[0].dcache = L1_DCache(size="32kB") -system.cpu[0].icache.cpu_side = system.cpu[0].icache_port -system.cpu[0].dcache.cpu_side = system.cpu[0].dcache_port -system.cpu[0].createThreads() - -system.cpu[1].createInterruptController() -system.cpu[1].icache = L1_ICache(size="32kB") -system.cpu[1].dcache = L1_DCache(size="32kB") -system.cpu[1].icache.cpu_side = system.cpu[1].icache_port -system.cpu[1].dcache.cpu_side = system.cpu[1].dcache_port -system.cpu[1].createThreads() - -# XXX: Assign input trace files to the eTraceCPU (you have to set this path -# properly before running gem5): -system.cpu[0].instTraceFile="dram.sys/DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz" -system.cpu[0].dataTraceFile="dram.sys/DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz" -system.cpu[1].instTraceFile="dram.sys/DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz" -system.cpu[1].dataTraceFile="dram.sys/DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz" - -# Setting up memory BUS: -system.physmem = SimpleMemory() # This must be instantiated, even if not needed - -# Create a external TLM port: -system.tlm1 = ExternalSlave() -system.tlm1.addr_ranges = [AddrRange('256MB')] -system.tlm1.port_type = "tlm_slave" -system.tlm1.port_data = "transactor1" - -system.tlm2 = ExternalSlave() -system.tlm2.addr_ranges = [AddrRange('256MB')] -system.tlm2.port_type = "tlm_slave" -system.tlm2.port_data = "transactor2" - -# Build Helpting Busses: -system.membus1 = SystemXBar() -system.membus2 = SystemXBar() - -# Connect everything: -system.system_port = system.membus1.slave -system.cpu[0].icache.mem_side = system.membus1.slave -system.cpu[0].dcache.mem_side = system.membus1.slave -system.cpu[1].icache.mem_side = system.membus2.slave -system.cpu[1].dcache.mem_side = system.membus2.slave -system.membus1.master = system.tlm1.port -system.membus2.master = system.tlm2.port - - -# Start the simulation: -root = Root(full_system = False, system = system) -root.system.mem_mode = 'timing' -m5.instantiate() -m5.simulate() #Simulation time specified later on commandline diff --git a/DRAMSys/gem5/examples/tlm_elastic_slave_with_l2.py b/DRAMSys/gem5/examples/tlm_elastic_slave_with_l2.py deleted file mode 100644 index a4f93482..00000000 --- a/DRAMSys/gem5/examples/tlm_elastic_slave_with_l2.py +++ /dev/null @@ -1,135 +0,0 @@ -# Copyright (c) 2016, Technische Universität Kaiserslautern -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the copyright holder nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Matthias Jung - -import m5 -import optparse - -from m5.objects import * -from m5.util import addToPath, fatal - -addToPath('../../../configs/common/') - -from Caches import * - -# This configuration shows a simple setup of a Elastic Trace Player (eTraceCPU) -# and an external TLM port for SystemC co-simulation. -# -# We assume a DRAM size of 512MB and L1 cache sizes of 32KB. -# -# Base System Architecture: -# -# +-----------+ ^ -# +-------------+ | eTraceCPU | | -# | System Port | +-----+-----+ | -# +------+------+ | $D1 | $I1 | | -# | +--+--+--+--+ | -# | | | | gem5 World (see this file) -# | +--v-----v--+ | -# | | toL2Bus | | -# | +-----+-----+ | -# | | | -# | +-----v-----+ | -# | | L2 | | -# | +-----+-----+ | -# | | | -# +------v---------------v-----+ | -# | Membus | v -# +----------------+-----------+ External Port (see sc_port.*) -# | ^ -# +---v---+ | TLM World -# | TLM | | (see sc_target.*) -# +-------+ v -# -# -# Create a system with a Crossbar and an Elastic Trace Player as CPU: - -# Setup System: -system = System(cpu=TraceCPU(cpu_id=0), - mem_mode='timing', - mem_ranges = [AddrRange('1024MB')], - cache_line_size = 64) - -# Create a top-level voltage domain: -system.voltage_domain = VoltageDomain() - -# Create a source clock for the system. This is used as the clock period for -# xbar and memory: -system.clk_domain = SrcClockDomain(clock = '1GHz', - voltage_domain = system.voltage_domain) - -system.cpu.createThreads() - -# Create a CPU voltage domain: -system.cpu_voltage_domain = VoltageDomain() - -# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock -# is actually used only by the caches connected to the CPU: -system.cpu_clk_domain = SrcClockDomain(clock = '1GHz', - voltage_domain = system.cpu_voltage_domain) - -# Setup CPU and its L1 caches: -system.cpu.createInterruptController() -system.cpu.icache = L1_ICache(size="32kB") -system.cpu.dcache = L1_DCache(size="32kB") -system.cpu.icache.cpu_side = system.cpu.icache_port -system.cpu.dcache.cpu_side = system.cpu.dcache_port - -# XXX: Assign input trace files to the eTraceCPU (you have to set this path -# properly before running gem5): -system.cpu.instTraceFile="dram.sys/DRAMSys/gem5/etraces/system.cpu.traceListener.inst.gz" -system.cpu.dataTraceFile="dram.sys/DRAMSys/gem5/etraces/system.cpu.traceListener.data.gz" - -# Setting up L1 BUS: -system.tol2bus = L2XBar() -system.l2cache = L2Cache(size="1MB") -system.physmem = SimpleMemory() # This must be instantiated, even if not needed - -# Create a external TLM port: -system.tlm = ExternalSlave() -system.tlm.addr_ranges = [AddrRange('4096MB')] -system.tlm.port_type = "tlm_slave" -system.tlm.port_data = "transactor" - -# Connect everything: -system.membus = SystemXBar() -system.system_port = system.membus.slave -system.cpu.icache.mem_side = system.tol2bus.slave -system.cpu.dcache.mem_side = system.tol2bus.slave -system.tol2bus.master = system.l2cache.cpu_side -system.l2cache.mem_side = system.membus.slave -system.membus.master = system.tlm.port - -# Start the simulation: -root = Root(full_system = False, system = system) -root.system.mem_mode = 'timing' -m5.instantiate() -m5.simulate() diff --git a/DRAMSys/gem5/gem5_se/almabench/almabench.log b/DRAMSys/gem5/gem5_se/almabench/almabench.log deleted file mode 100644 index c1e5536d..00000000 --- a/DRAMSys/gem5/gem5_se/almabench/almabench.log +++ /dev/null @@ -1,13 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2018 11:41:41 -gem5 started Nov 8 2018 17:18:25 -gem5 executing on botanix, pid 6721 -command line: build/ARM/gem5.opt -d se_output_2018.11.08-17.18.24/almabench configs/example/arm/starter_se.py --cpu=hpi --num-cores=1 --mem-channels=1 --tlm-memory=transactor /home/eder/gem5_tnt/benchmarks/test-suite/SingleSource/Benchmarks/CoyoteBench/almabench - -info: Standard input is not a terminal, disabling listeners. -info: 1. command and arguments: ['/home/eder/gem5_tnt/benchmarks/test-suite/SingleSource/Benchmarks/CoyoteBench/almabench'] -Global frequency set at 1000000000000 ticks per second -fatal: Can't find port handler type 'tlm_slave' -Memory Usage: 285396 KBytes diff --git a/DRAMSys/gem5/gem5_se/almabench/config.dot b/DRAMSys/gem5/gem5_se/almabench/config.dot deleted file mode 100644 index f2e2d7b0..00000000 --- a/DRAMSys/gem5/gem5_se/almabench/config.dot +++ /dev/null @@ -1,6731 +0,0 @@ -digraph G { -ranksep="1.3"; -subgraph cluster_root { -color="#000000"; -fillcolor="#bab6ae"; -fontcolor="#000000"; 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system_cpu_cluster_toL2Bus_slave; -system_cpu_cluster_cpus_itb_walker_port -> system_cpu_cluster_cpus_itb_walker_cache_cpu_side; -system_cpu_cluster_cpus_dcache_mem_side -> system_cpu_cluster_toL2Bus_slave; -} diff --git a/DRAMSys/gem5/gem5_se/almabench/config.dot.pdf b/DRAMSys/gem5/gem5_se/almabench/config.dot.pdf deleted file mode 100644 index 9e5641a7..00000000 Binary files a/DRAMSys/gem5/gem5_se/almabench/config.dot.pdf and /dev/null differ diff --git a/DRAMSys/gem5/gem5_se/almabench/config.dot.svg b/DRAMSys/gem5/gem5_se/almabench/config.dot.svg deleted file mode 100644 index d24fe15a..00000000 --- a/DRAMSys/gem5/gem5_se/almabench/config.dot.svg +++ /dev/null @@ -1,301 +0,0 @@ - - - - - - -G - -cluster_root - - -root -: Root - - - -cluster_system - - -system -: SimpleSeSystem - - - -cluster_system_membus - - -membus -: SystemXBar - - - -cluster_system_cpu_cluster - - -cpu_cluster -: CpuCluster - - - -cluster_system_cpu_cluster_toL2Bus - - -toL2Bus -: L2XBar - - - -cluster_system_cpu_cluster_l2 - - -l2 -: HPI_L2 - - - -cluster_system_cpu_cluster_cpus - - -cpus -: HPI - - - -cluster_system_cpu_cluster_cpus_dtb_walker_cache - - -dtb_walker_cache -: HPI_WalkCache - - - -cluster_system_cpu_cluster_cpus_icache - - -icache -: HPI_ICache - - - -cluster_system_cpu_cluster_cpus_dtb - - -dtb -: HPI_DTB - - - -cluster_system_cpu_cluster_cpus_dtb_walker - - -walker -: ArmTableWalker - - - -cluster_system_cpu_cluster_cpus_itb_walker_cache - - -itb_walker_cache -: HPI_WalkCache - - - -cluster_system_cpu_cluster_cpus_itb - - -itb -: HPI_ITB - - - -cluster_system_cpu_cluster_cpus_itb_walker - - -walker -: ArmTableWalker - - - -cluster_system_cpu_cluster_cpus_dcache - - -dcache -: HPI_DCache - - - -cluster_system_external_memory - - -external_memory -: ExternalSlave - - - - -system_system_port - -system_port - - -system_membus_slave - -slave - - -system_system_port->system_membus_slave - - - - -system_membus_master - -master - - -system_external_memory_port - -port - - -system_membus_master->system_external_memory_port - - - - -system_cpu_cluster_toL2Bus_master - -master - - -system_cpu_cluster_l2_cpu_side - -cpu_side - - -system_cpu_cluster_toL2Bus_master->system_cpu_cluster_l2_cpu_side - - - - -system_cpu_cluster_toL2Bus_slave - -slave - - -system_cpu_cluster_l2_mem_side - -mem_side - - -system_cpu_cluster_l2_mem_side->system_membus_slave - - - - -system_cpu_cluster_cpus_icache_port - -icache_port - - -system_cpu_cluster_cpus_icache_cpu_side - -cpu_side - - -system_cpu_cluster_cpus_icache_port->system_cpu_cluster_cpus_icache_cpu_side - - - - -system_cpu_cluster_cpus_dcache_port - -dcache_port - - -system_cpu_cluster_cpus_dcache_cpu_side - -cpu_side - - -system_cpu_cluster_cpus_dcache_port->system_cpu_cluster_cpus_dcache_cpu_side - - - - -system_cpu_cluster_cpus_dtb_walker_cache_mem_side - -mem_side - - -system_cpu_cluster_cpus_dtb_walker_cache_mem_side->system_cpu_cluster_toL2Bus_slave - - - - -system_cpu_cluster_cpus_dtb_walker_cache_cpu_side - -cpu_side - - -system_cpu_cluster_cpus_icache_mem_side - -mem_side - - -system_cpu_cluster_cpus_icache_mem_side->system_cpu_cluster_toL2Bus_slave - - - - -system_cpu_cluster_cpus_dtb_walker_port - -port - - -system_cpu_cluster_cpus_dtb_walker_port->system_cpu_cluster_cpus_dtb_walker_cache_cpu_side - - - - -system_cpu_cluster_cpus_itb_walker_cache_mem_side - -mem_side - - -system_cpu_cluster_cpus_itb_walker_cache_mem_side->system_cpu_cluster_toL2Bus_slave - - - - -system_cpu_cluster_cpus_itb_walker_cache_cpu_side - -cpu_side - - -system_cpu_cluster_cpus_itb_walker_port - -port - - -system_cpu_cluster_cpus_itb_walker_port->system_cpu_cluster_cpus_itb_walker_cache_cpu_side - - - - -system_cpu_cluster_cpus_dcache_mem_side - -mem_side - - -system_cpu_cluster_cpus_dcache_mem_side->system_cpu_cluster_toL2Bus_slave - - - - - diff --git a/DRAMSys/gem5/gem5_se/almabench/config.ini b/DRAMSys/gem5/gem5_se/almabench/config.ini deleted file mode 100644 index 6f51141d..00000000 --- a/DRAMSys/gem5/gem5_se/almabench/config.ini +++ /dev/null @@ -1,5019 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu_cluster dvfs_handler external_memory membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=false -kernel_extras= -load_addr_mask=18446744073709551615 -load_offset=0 -mem_mode=timing -mem_ranges=0:2147483647:0:0:0:0 -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu_cluster] -type=SubSystem -children=clk_domain cpus l2 toL2Bus voltage_domain -eventq_index=0 -thermal_domain=Null - -[system.cpu_cluster.clk_domain] -type=SrcClockDomain -clock=250 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.cpu_cluster.voltage_domain - -[system.cpu_cluster.cpus] -type=MinorCPU -children=branchPred dcache dstage2_mmu dtb dtb_walker_cache executeFuncUnits icache interrupts isa istage2_mmu itb itb_walker_cache tracer workload -branchPred=system.cpu_cluster.cpus.branchPred -checker=Null -clk_domain=system.cpu_cluster.clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu_cluster.cpus.dstage2_mmu -dtb=system.cpu_cluster.cpus.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu_cluster.cpus.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu_cluster.cpus.interrupts -isa=system.cpu_cluster.cpus.isa -istage2_mmu=system.cpu_cluster.cpus.istage2_mmu -itb=system.cpu_cluster.cpus.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_gating_on_idle=false -power_model= -profile=0 -progress_interval=0 -pwr_gating_latency=300 -simpoint_start_insts= -socket_id=0 -switched_out=false -syscallRetryLatency=10000 -system=system -threadPolicy=RoundRobin -tracer=system.cpu_cluster.cpus.tracer -wait_for_remote_gdb=false -workload=system.cpu_cluster.cpus.workload -dcache_port=system.cpu_cluster.cpus.dcache.cpu_side -icache_port=system.cpu_cluster.cpus.icache.cpu_side - -[system.cpu_cluster.cpus.branchPred] -type=TournamentBP -BTBEntries=128 -BTBTagSize=18 -RASSize=8 -choiceCtrBits=2 -choicePredictorSize=1024 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=1024 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=64 -localPredictorSize=64 -numThreads=1 -useIndirect=true - -[system.cpu_cluster.cpus.dcache] -type=Cache -children=prefetcher replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=4 -clk_domain=system.cpu_cluster.clk_domain -clusivity=mostly_incl -data_latency=1 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=system.cpu_cluster.cpus.dcache.prefetcher -replacement_policy=system.cpu_cluster.cpus.dcache.replacement_policy -response_latency=1 -sequential_access=false -size=32768 -system=system -tag_latency=1 -tags=system.cpu_cluster.cpus.dcache.tags -tgts_per_mshr=8 -warmup_percentage=0 -write_buffers=4 -writeback_clean=false -cpu_side=system.cpu_cluster.cpus.dcache_port -mem_side=system.cpu_cluster.toL2Bus.slave[1] - -[system.cpu_cluster.cpus.dcache.prefetcher] -type=StridePrefetcher -cache_snoop=false -clk_domain=system.cpu_cluster.clk_domain -default_p_state=UNDEFINED -degree=4 -eventq_index=0 -latency=1 -max_conf=7 -min_conf=0 -on_data=true -on_inst=true -on_miss=false -on_read=true -on_write=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -queue_filter=true -queue_size=4 -queue_squash=true -start_conf=4 -sys=system -table_assoc=4 -table_sets=16 -tag_prefetch=true -thresh_conf=4 -use_master_id=true - -[system.cpu_cluster.cpus.dcache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu_cluster.cpus.dcache.tags] -type=BaseSetAssoc -assoc=4 -block_size=64 -clk_domain=system.cpu_cluster.clk_domain -data_latency=1 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu_cluster.cpus.dcache.replacement_policy -sequential_access=false -size=32768 -tag_latency=1 -warmup_percentage=0 - -[system.cpu_cluster.cpus.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu_cluster.cpus.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu_cluster.cpus.dtb - -[system.cpu_cluster.cpus.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu_cluster.cpus.dstage2_mmu.stage2_tlb.walker - -[system.cpu_cluster.cpus.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_cluster.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu_cluster.cpus.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=256 -sys=system -walker=system.cpu_cluster.cpus.dtb.walker - -[system.cpu_cluster.cpus.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_cluster.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system -port=system.cpu_cluster.cpus.dtb_walker_cache.cpu_side - -[system.cpu_cluster.cpus.dtb_walker_cache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_cluster.clk_domain -clusivity=mostly_incl -data_latency=4 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=6 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu_cluster.cpus.dtb_walker_cache.replacement_policy -response_latency=4 -sequential_access=false -size=1024 -system=system -tag_latency=4 -tags=system.cpu_cluster.cpus.dtb_walker_cache.tags -tgts_per_mshr=8 -warmup_percentage=0 -write_buffers=16 -writeback_clean=false -cpu_side=system.cpu_cluster.cpus.dtb.walker.port -mem_side=system.cpu_cluster.toL2Bus.slave[3] - -[system.cpu_cluster.cpus.dtb_walker_cache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu_cluster.cpus.dtb_walker_cache.tags] -type=BaseSetAssoc -assoc=8 -block_size=64 -clk_domain=system.cpu_cluster.clk_domain -data_latency=4 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu_cluster.cpus.dtb_walker_cache.replacement_policy -sequential_access=false -size=1024 -tag_latency=4 -warmup_percentage=0 - -[system.cpu_cluster.cpus.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu_cluster.cpus.executeFuncUnits.funcUnits0 system.cpu_cluster.cpus.executeFuncUnits.funcUnits1 system.cpu_cluster.cpus.executeFuncUnits.funcUnits2 system.cpu_cluster.cpus.executeFuncUnits.funcUnits3 system.cpu_cluster.cpus.executeFuncUnits.funcUnits4 system.cpu_cluster.cpus.executeFuncUnits.funcUnits5 system.cpu_cluster.cpus.executeFuncUnits.funcUnits6 - -[system.cpu_cluster.cpus.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings00 timings01 timings02 timings03 timings04 timings05 timings06 timings07 timings08 timings09 timings10 timings11 timings12 timings13 timings14 timings15 timings16 timings17 timings18 timings19 timings20 timings21 timings22 timings23 timings24 timings25 timings26 timings27 timings28 timings29 timings30 timings31 timings32 timings33 timings34 timings35 timings36 timings37 timings38 timings39 timings40 timings41 timings42 -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings00 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings01 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings02 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings03 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings04 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings05 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings06 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings07 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings08 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings09 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings10 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings11 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings12 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings13 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings14 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings15 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings16 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings17 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings18 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings19 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings20 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings21 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings22 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings23 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings24 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings25 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings26 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings27 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings28 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings29 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings30 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings31 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings32 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings33 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings34 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings35 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings36 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings37 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings38 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings39 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings40 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings41 system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings42 - -[system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings00] -type=MinorFUTiming -children=opClasses -description=HPI_SSAT_USAT_no_shift_A1 -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=120521232368 -match=111149072 -opClasses=system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings00.opClasses -srcRegsRelativeLats=0 0 0 2 0 -suppress=false - -[system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings00.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings01] -type=MinorFUTiming -children=opClasses -description=HPI_SSAT_USAT_shift_A1 -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=120521228336 -match=111149072 -opClasses=system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings01.opClasses -srcRegsRelativeLats=0 0 0 1 0 -suppress=false - -[system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings01.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings02] -type=MinorFUTiming -children=opClasses -description=HPI_SSAT16_USAT16_A1 -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=120522277104 -match=111149104 -opClasses=system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings02.opClasses -srcRegsRelativeLats=0 0 0 2 0 -suppress=false - -[system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings02.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu_cluster.cpus.executeFuncUnits.funcUnits0.timings03] -type=MinorFUTiming -children=opClasses -description=HPI_QADD_QSUB_A1 -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null 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-tag_latency=1 -warmup_percentage=0 - -[system.cpu_cluster.cpus.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu_cluster.cpus.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -impdef_nop=false -midr=1091551472 -pmu=Null -system=system -vecRegRenameMode=Full - -[system.cpu_cluster.cpus.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu_cluster.cpus.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu_cluster.cpus.itb - -[system.cpu_cluster.cpus.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -sys=system -walker=system.cpu_cluster.cpus.istage2_mmu.stage2_tlb.walker - -[system.cpu_cluster.cpus.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_cluster.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system - -[system.cpu_cluster.cpus.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=256 -sys=system -walker=system.cpu_cluster.cpus.itb.walker - -[system.cpu_cluster.cpus.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_cluster.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -sys=system -port=system.cpu_cluster.cpus.itb_walker_cache.cpu_side - -[system.cpu_cluster.cpus.itb_walker_cache] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_cluster.clk_domain -clusivity=mostly_incl -data_latency=4 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=6 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu_cluster.cpus.itb_walker_cache.replacement_policy -response_latency=4 -sequential_access=false -size=1024 -system=system -tag_latency=4 -tags=system.cpu_cluster.cpus.itb_walker_cache.tags -tgts_per_mshr=8 -warmup_percentage=0 -write_buffers=16 -writeback_clean=false -cpu_side=system.cpu_cluster.cpus.itb.walker.port -mem_side=system.cpu_cluster.toL2Bus.slave[2] - -[system.cpu_cluster.cpus.itb_walker_cache.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu_cluster.cpus.itb_walker_cache.tags] -type=BaseSetAssoc -assoc=8 -block_size=64 -clk_domain=system.cpu_cluster.clk_domain -data_latency=4 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu_cluster.cpus.itb_walker_cache.replacement_policy -sequential_access=false -size=1024 -tag_latency=4 -warmup_percentage=0 - -[system.cpu_cluster.cpus.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_cluster.cpus.workload] -type=Process -cmd=../../DRAMSys/gem5/gem5_se/almabench/almabench -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=../../DRAMSys/gem5/gem5_se/almabench/almabench -gid=100 -input=cin -kvmInSE=false -maxStackSize=67108864 -output=cout -pgid=100 -pid=100 -ppid=0 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_cluster.l2] -type=Cache -children=replacement_policy tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=16 -clk_domain=system.cpu_cluster.clk_domain -clusivity=mostly_incl -data_latency=13 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -prefetch_on_access=false -prefetcher=Null -replacement_policy=system.cpu_cluster.l2.replacement_policy -response_latency=5 -sequential_access=false -size=1048576 -system=system -tag_latency=13 -tags=system.cpu_cluster.l2.tags -tgts_per_mshr=8 -warmup_percentage=0 -write_buffers=16 -writeback_clean=false -cpu_side=system.cpu_cluster.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu_cluster.l2.replacement_policy] -type=LRURP -eventq_index=0 - -[system.cpu_cluster.l2.tags] -type=BaseSetAssoc -assoc=16 -block_size=64 -clk_domain=system.cpu_cluster.clk_domain -data_latency=13 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -replacement_policy=system.cpu_cluster.l2.replacement_policy -sequential_access=false -size=1048576 -tag_latency=13 -warmup_percentage=0 - -[system.cpu_cluster.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_cluster.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -point_of_unification=true -power_model= -response_latency=1 -snoop_filter=system.cpu_cluster.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=64 -master=system.cpu_cluster.l2.cpu_side -slave=system.cpu_cluster.cpus.icache.mem_side system.cpu_cluster.cpus.dcache.mem_side system.cpu_cluster.cpus.itb_walker_cache.mem_side system.cpu_cluster.cpus.dtb_walker_cache.mem_side - -[system.cpu_cluster.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu_cluster.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.2 - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.external_memory] -type=ExternalSlave -addr_ranges=0:2147483647:0:0:0:0 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -port_data=transactor -port_type=tlm_slave -power_model= -port=system.membus.master[0] - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -point_of_unification=true -power_model= -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.external_memory.port -slave=system.system_port system.cpu_cluster.l2.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model= -range=0:134217727:0:0:0:0 - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=3.3 - diff --git a/DRAMSys/gem5/gem5_se/almabench/config.json b/DRAMSys/gem5/gem5_se/almabench/config.json deleted file mode 100644 index a90d64c5..00000000 --- a/DRAMSys/gem5/gem5_se/almabench/config.json +++ /dev/null @@ -1,7803 +0,0 @@ -{ - "name": null, - "sim_quantum": 0, - "system": { - "kernel": "", - "mmap_using_noreserve": false, - "kernel_addr_check": false, - "membus": { - "point_of_coherency": true, - "system": "system", - "response_latency": 2, - "cxx_class": "CoherentXBar", - "forward_latency": 4, - "clk_domain": "system.clk_domain", - "point_of_unification": true, - "width": 16, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "master": { - "peer": [ - "system.external_memory.port" - ], - "role": "MASTER" - }, - "type": "CoherentXBar", - "frontend_latency": 3, - "slave": { - "peer": [ - "system.system_port", - "system.cpu_cluster.l2.mem_side" - ], - "role": "SLAVE" - }, - "p_state_clk_gate_min": 1000, - "snoop_filter": { - "name": "snoop_filter", - "system": "system", - "max_capacity": 8388608, - "eventq_index": 0, - "cxx_class": "SnoopFilter", - "path": "system.membus.snoop_filter", - "type": "SnoopFilter", - "lookup_latency": 1 - }, - "power_model": [], - "path": "system.membus", - "snoop_response_latency": 4, - "name": "membus", - "p_state_clk_gate_bins": 20, - "use_default_range": false - }, - "symbolfile": "", - "readfile": "", - "thermal_model": null, - "cxx_class": "System", - "work_begin_cpu_id_exit": -1, - "load_offset": 0, - "work_begin_exit_count": 0, - "p_state_clk_gate_min": 1000, - "memories": [ - "system.physmem" - ], - "work_begin_ckpt_count": 0, - "clk_domain": { - "name": "clk_domain", - "clock": [ - 1000 - ], - "init_perf_level": 0, - "voltage_domain": "system.voltage_domain", - "eventq_index": 0, - "cxx_class": "SrcClockDomain", - "path": "system.clk_domain", - "type": "SrcClockDomain", - "domain_id": -1 - }, - "mem_ranges": [ - "0:2147483647:0:0:0:0" - ], - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "dvfs_handler": { - "enable": false, - "name": "dvfs_handler", - "sys_clk_domain": "system.clk_domain", - "transition_latency": 100000000, - "eventq_index": 0, - "cxx_class": "DVFSHandler", - "domains": [], - "path": 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"work_cpus_ckpt_count": 0, - "thermal_components": [], - "path": "system", - "work_end_ckpt_count": 0, - "mem_mode": "timing", - "name": "system", - "init_param": 0, - "p_state_clk_gate_bins": 20, - "kernel_extras": [], - "load_addr_mask": 18446744073709551615, - "cpu_cluster": { - "name": "cpu_cluster", - "thermal_domain": null, - "voltage_domain": { - "name": "voltage_domain", - "eventq_index": 0, - "voltage": [ - 1.2 - ], - "cxx_class": "VoltageDomain", - "path": "system.cpu_cluster.voltage_domain", - "type": "VoltageDomain" - }, - "clk_domain": { - "name": "clk_domain", - "clock": [ - 250 - ], - "init_perf_level": 0, - "voltage_domain": "system.cpu_cluster.voltage_domain", - "eventq_index": 0, - "cxx_class": "SrcClockDomain", - "path": "system.cpu_cluster.clk_domain", - "type": "SrcClockDomain", - "domain_id": -1 - }, - "cpus": [ - { - "max_insts_any_thread": 0, - "itb_walker_cache": { - "replacement_policy": { - "eventq_index": 0, - "path": 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"default_p_state": "UNDEFINED", - "clk_domain": "system.cpu_cluster.clk_domain", - "power_model": [], - "sequential_access": false, - "assoc": 8, - "warmup_percentage": 0, - "cxx_class": "BaseSetAssoc", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu_cluster.cpus.itb_walker_cache.tags", - "block_size": 64, - "type": "BaseSetAssoc", - "data_latency": 4 - }, - "tgts_per_mshr": 8, - "demand_mshr_reserve": 1, - "power_model": [], - "addr_ranges": [ - "0:18446744073709551615:0:0:0:0" - ], - "is_read_only": false, - "warmup_percentage": 0, - "prefetch_on_access": false, - "path": "system.cpu_cluster.cpus.itb_walker_cache", - "data_latency": 4, - "tag_latency": 4, - "name": "itb_walker_cache", - "p_state_clk_gate_bins": 20, - "sequential_access": false, - "assoc": 8 - }, - "do_statistics_insts": true, - "numThreads": 1, - "fetch1LineSnapWidth": 0, - "fetch1ToFetch2BackwardDelay": 1, - "fetch1FetchLimit": 1, - "executeIssueLimit": 2, - "power_gating_on_idle": false, - "istage2_mmu": { - "name": "istage2_mmu", - "tlb": "system.cpu_cluster.cpus.itb", - "sys": "system", - "stage2_tlb": { - "name": "stage2_tlb", - "is_stage2": true, - "sys": "system", - "eventq_index": 0, - "cxx_class": "ArmISA::TLB", - "walker": { - "p_state_clk_gate_min": 1000, - "name": "walker", - "is_stage2": true, - "p_state_clk_gate_bins": 20, - "cxx_class": "ArmISA::TableWalker", - "clk_domain": "system.cpu_cluster.clk_domain", - "power_model": [], - "sys": "system", - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu_cluster.cpus.istage2_mmu.stage2_tlb.walker", - "type": "ArmTableWalker", - "num_squash_per_cycle": 2 - }, - "path": "system.cpu_cluster.cpus.istage2_mmu.stage2_tlb", - "type": "ArmTLB", - "size": 32 - }, - "eventq_index": 0, - "cxx_class": "ArmISA::Stage2MMU", - "path": "system.cpu_cluster.cpus.istage2_mmu", - "type": "ArmStage2MMU" - }, - "executeLSQMaxStoreBufferStoresPerCycle": 2, - "icache": { - "replacement_policy": { - "eventq_index": 0, - "path": "system.cpu_cluster.cpus.icache.replacement_policy", - "type": "LRURP", - "name": "replacement_policy", - "cxx_class": "LRURP" - }, - "cpu_side": { - "peer": "system.cpu_cluster.cpus.icache_port", - "role": "SLAVE" - }, - "clusivity": "mostly_incl", - "prefetcher": null, - "system": "system", - "write_buffers": 8, - "response_latency": 1, - "cxx_class": "Cache", - "size": 32768, - "type": "Cache", - "clk_domain": "system.cpu_cluster.clk_domain", - "max_miss_count": 0, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "mem_side": { - "peer": "system.cpu_cluster.toL2Bus.slave[0]", - "role": "MASTER" - }, - "mshrs": 2, - "writeback_clean": false, - "p_state_clk_gate_min": 1000, - "tags": { - "size": 32768, - "tag_latency": 1, - "replacement_policy": "system.cpu_cluster.cpus.icache.replacement_policy", - "name": "tags", - "p_state_clk_gate_min": 1000, - "eventq_index": 0, - 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"cpu_side": { - "peer": "system.cpu_cluster.cpus.dcache_port", - "role": "SLAVE" - }, - "clusivity": "mostly_incl", - "prefetcher": { - "queue_squash": true, - "on_miss": false, - "tag_prefetch": true, - "cache_snoop": false, - "cxx_class": "StridePrefetcher", - "latency": 1, - "use_master_id": true, - "degree": 4, - "max_conf": 7, - "on_inst": true, - "clk_domain": "system.cpu_cluster.clk_domain", - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "on_read": true, - "queue_filter": true, - "start_conf": 4, - "type": "StridePrefetcher", - "p_state_clk_gate_min": 1000, - "on_data": true, - "on_write": true, - "power_model": [], - "sys": "system", - "queue_size": 4, - "path": "system.cpu_cluster.cpus.dcache.prefetcher", - "table_assoc": 4, - "table_sets": 16, - "name": "prefetcher", - "p_state_clk_gate_bins": 20, - "min_conf": 0, - "thresh_conf": 4 - }, - "system": "system", - "write_buffers": 4, - "response_latency": 1, - "cxx_class": "Cache", - "size": 32768, - "type": "Cache", - "clk_domain": "system.cpu_cluster.clk_domain", - "max_miss_count": 0, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "mem_side": { - "peer": "system.cpu_cluster.toL2Bus.slave[1]", - "role": "MASTER" - }, - "mshrs": 4, - "writeback_clean": false, - "p_state_clk_gate_min": 1000, - "tags": { - "size": 32768, - "tag_latency": 1, - "replacement_policy": "system.cpu_cluster.cpus.dcache.replacement_policy", - "name": "tags", - "p_state_clk_gate_min": 1000, - "eventq_index": 0, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "clk_domain": "system.cpu_cluster.clk_domain", - "power_model": [], - "sequential_access": false, - "assoc": 4, - "warmup_percentage": 0, - "cxx_class": "BaseSetAssoc", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu_cluster.cpus.dcache.tags", - "block_size": 64, - "type": "BaseSetAssoc", - "data_latency": 1 - }, - "tgts_per_mshr": 8, - "demand_mshr_reserve": 1, - "power_model": [], - "addr_ranges": [ - "0:18446744073709551615:0:0:0:0" - ], - "is_read_only": false, - "warmup_percentage": 0, - "prefetch_on_access": false, - "path": "system.cpu_cluster.cpus.dcache", - "data_latency": 1, - "tag_latency": 1, - "name": "dcache", - "p_state_clk_gate_bins": 20, - "sequential_access": false, - "assoc": 4 - }, - "path": "system.cpu_cluster.cpus", - "fetch1ToFetch2ForwardDelay": 1, - "decodeInputBufferSize": 3 - } - ], - "l2": { - "replacement_policy": { - "eventq_index": 0, - "path": "system.cpu_cluster.l2.replacement_policy", - "type": "LRURP", - "name": "replacement_policy", - "cxx_class": "LRURP" - }, - "cpu_side": { - "peer": "system.cpu_cluster.toL2Bus.master[0]", - "role": "SLAVE" - }, - "clusivity": "mostly_incl", - "prefetcher": null, - "system": "system", - "write_buffers": 16, - "response_latency": 5, - "cxx_class": "Cache", - "size": 1048576, - "type": "Cache", - "clk_domain": "system.cpu_cluster.clk_domain", - "max_miss_count": 0, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "mem_side": { - "peer": "system.membus.slave[1]", - "role": "MASTER" - }, - "mshrs": 4, - "writeback_clean": false, - "p_state_clk_gate_min": 1000, - "tags": { - "size": 1048576, - "tag_latency": 13, - "replacement_policy": "system.cpu_cluster.l2.replacement_policy", - "name": "tags", - "p_state_clk_gate_min": 1000, - "eventq_index": 0, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "clk_domain": "system.cpu_cluster.clk_domain", - "power_model": [], - "sequential_access": false, - "assoc": 16, - "warmup_percentage": 0, - "cxx_class": "BaseSetAssoc", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu_cluster.l2.tags", - "block_size": 64, - "type": "BaseSetAssoc", - "data_latency": 13 - }, - "tgts_per_mshr": 8, - "demand_mshr_reserve": 1, - "power_model": [], - "addr_ranges": [ - "0:18446744073709551615:0:0:0:0" - ], - "is_read_only": false, - "warmup_percentage": 0, - "prefetch_on_access": false, - "path": "system.cpu_cluster.l2", - "data_latency": 13, - "tag_latency": 13, - "name": "l2", - "p_state_clk_gate_bins": 20, - "sequential_access": false, - "assoc": 16 - }, - "eventq_index": 0, - "cxx_class": "SubSystem", - "path": "system.cpu_cluster", - "toL2Bus": { - "point_of_coherency": false, - "system": "system", - "response_latency": 1, - "cxx_class": "CoherentXBar", - "forward_latency": 0, - "clk_domain": "system.cpu_cluster.clk_domain", - "point_of_unification": true, - "width": 64, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "master": { - "peer": [ - "system.cpu_cluster.l2.cpu_side" - ], - "role": "MASTER" - }, - "type": "CoherentXBar", - "frontend_latency": 1, - "slave": { - "peer": [ - "system.cpu_cluster.cpus.icache.mem_side", - "system.cpu_cluster.cpus.dcache.mem_side", - "system.cpu_cluster.cpus.itb_walker_cache.mem_side", - "system.cpu_cluster.cpus.dtb_walker_cache.mem_side" - ], - "role": "SLAVE" - }, - "p_state_clk_gate_min": 1000, - "snoop_filter": { - "name": "snoop_filter", - "system": "system", - "max_capacity": 8388608, - "eventq_index": 0, - "cxx_class": "SnoopFilter", - "path": "system.cpu_cluster.toL2Bus.snoop_filter", - "type": "SnoopFilter", - "lookup_latency": 0 - }, - "power_model": [], - "path": "system.cpu_cluster.toL2Bus", - "snoop_response_latency": 1, - "name": "toL2Bus", - "p_state_clk_gate_bins": 20, - "use_default_range": false - }, - "type": "SubSystem" - }, - "multi_thread": false, - "external_memory": { - "name": "external_memory", - "p_state_clk_gate_min": 1000, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "clk_domain": "system.clk_domain", - "power_model": [], - "addr_ranges": [ - "0:2147483647:0:0:0:0" - ], - "eventq_index": 0, - "port_type": "tlm_slave", - "cxx_class": "ExternalSlave", - "p_state_clk_gate_max": 1000000000000, - "path": "system.external_memory", - "type": "ExternalSlave", - "port": { - "peer": "system.membus.master[0]", - "role": "SLAVE" - }, - "port_data": "transactor" - }, - "exit_on_work_items": false, - "work_item_id": -1, - "num_work_ids": 16 - }, - "time_sync_period": 100000000000, - "eventq_index": 0, - "time_sync_spin_threshold": 100000000, - "cxx_class": "Root", - "path": "root", - "time_sync_enable": false, - "type": "Root", - "full_system": false -} \ No newline at end of file diff --git a/DRAMSys/gem5/gem5_se/hello b/DRAMSys/gem5/gem5_se/hello-ARM/hello old mode 100755 new mode 100644 similarity index 100% rename from DRAMSys/gem5/gem5_se/hello rename to DRAMSys/gem5/gem5_se/hello-ARM/hello diff --git a/DRAMSys/gem5/configs/hello.ini b/DRAMSys/gem5/gem5_se/hello-ARM/hello.ini similarity index 99% rename from DRAMSys/gem5/configs/hello.ini rename to DRAMSys/gem5/gem5_se/hello-ARM/hello.ini index 68e4e31e..065f0e52 100644 --- a/DRAMSys/gem5/configs/hello.ini +++ b/DRAMSys/gem5/gem5_se/hello-ARM/hello.ini @@ -355,7 +355,7 @@ eventq_index=0 [system.cpu.workload] type=Process -cmd=../../DRAMSys/gem5/gem5_se/hello +cmd=../../DRAMSys/gem5/gem5_se/hello-ARM/hello cwd= drivers= egid=100 @@ -363,7 +363,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=../../DRAMSys/gem5/gem5_se/hello +executable=../../DRAMSys/gem5/gem5_se/hello-ARM/hello gid=100 input=cin kvmInSE=false diff --git a/DRAMSys/gem5/gem5_se/hello-x86/config.dot b/DRAMSys/gem5/gem5_se/hello-x86/config.dot deleted file mode 100644 index 8b3a6ae1..00000000 --- a/DRAMSys/gem5/gem5_se/hello-x86/config.dot +++ /dev/null @@ -1,275 +0,0 @@ -digraph G { -ranksep="1.3"; -subgraph cluster_root { -color="#000000"; -fillcolor="#bab6ae"; -fontcolor="#000000"; -fontname=Arial; -fontsize=14; -label="root \n: Root"; -shape=Mrecord; -style="rounded, filled"; -tooltip="eventq_index=0 full_system=false sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000"; -subgraph cluster_system { -color="#000000"; -fillcolor="#e4e7eb"; -fontcolor="#000000"; -fontname=Arial; -fontsize=14; -label="system \n: System"; -shape=Mrecord; -style="rounded, filled"; -tooltip="boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 exit_on_work_items=false init_param=0 kernel= kernel_addr_check=false kernel_extras= kvm_vm=Null load_addr_mask=18446744073709551615 load_offset=0 mem_mode=timing mem_ranges=0:536870911:0:0:0:0 memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model= readfile= symbolfile= thermal_components= thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 work_cpus_ckpt_count=0 work_end_ckpt_count=0 work_end_exit_count=0 work_item_id=-1"; -system_system_port [color="#000000", fillcolor="#b6b8bc", fontcolor="#000000", fontname=Arial, fontsize=14, label=system_port, shape=Mrecord, style="rounded, filled"]; -subgraph cluster_system_membus { -color="#000000"; -fillcolor="#6f798c"; -fontcolor="#000000"; -fontname=Arial; -fontsize=14; -label="membus \n: SystemXBar"; -shape=Mrecord; -style="rounded, filled"; -tooltip="clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 point_of_coherency=true point_of_unification=true power_model= response_latency=2 snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false width=16"; -system_membus_master [color="#000000", fillcolor="#586070", fontcolor="#000000", fontname=Arial, fontsize=14, label=master, shape=Mrecord, style="rounded, filled"]; -system_membus_slave [color="#000000", fillcolor="#586070", fontcolor="#000000", fontname=Arial, fontsize=14, label=slave, shape=Mrecord, style="rounded, filled"]; -subgraph cluster_system_membus_snoop_filter { -color="#000000"; -fillcolor="#bab6ae"; -fontcolor="#000000"; -fontname=Arial; -fontsize=14; -label="snoop_filter \n: SnoopFilter"; -shape=Mrecord; -style="rounded, filled"; -tooltip="eventq_index=0 lookup_latency=1 max_capacity=8388608 system=system"; -} - -} - -subgraph cluster_system_external_memory { -color="#000000"; -fillcolor="#bab6ae"; -fontcolor="#000000"; -fontname=Arial; -fontsize=14; -label="external_memory \n: ExternalSlave"; -shape=Mrecord; -style="rounded, filled"; -tooltip="addr_ranges=0:536870911:0:0:0:0 clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 port_data=transactor port_type=tlm_slave power_model="; -system_external_memory_port [color="#000000", fillcolor="#94918b", fontcolor="#000000", fontname=Arial, fontsize=14, label=port, shape=Mrecord, style="rounded, filled"]; -} - -subgraph cluster_system_voltage_domain { -color="#000000"; -fillcolor="#bab6ae"; -fontcolor="#000000"; -fontname=Arial; -fontsize=14; -label="voltage_domain \n: VoltageDomain"; -shape=Mrecord; -style="rounded, filled"; -tooltip="eventq_index=0 voltage=1.0"; -} - -subgraph cluster_system_physmem { -color="#000000"; -fillcolor="#5e5958"; -fontcolor="#000000"; -fontname=Arial; -fontsize=14; -label="physmem \n: SimpleMemory"; -shape=Mrecord; -style="rounded, filled"; -tooltip="bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true kvm_map=true latency=30000 latency_var=0 null=false p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model= range=0:134217727:0:0:0:0"; -} - -subgraph cluster_system_clk_domain { -color="#000000"; -fillcolor="#bab6ae"; -fontcolor="#000000"; -fontname=Arial; -fontsize=14; -label="clk_domain \n: SrcClockDomain"; -shape=Mrecord; -style="rounded, filled"; -tooltip="clock=1000 domain_id=-1 eventq_index=0 init_perf_level=0 voltage_domain=system.voltage_domain"; -} - -subgraph cluster_system_cpu_voltage_domain { -color="#000000"; -fillcolor="#bab6ae"; -fontcolor="#000000"; -fontname=Arial; -fontsize=14; -label="cpu_voltage_domain \n: VoltageDomain"; -shape=Mrecord; -style="rounded, filled"; -tooltip="eventq_index=0 voltage=1.0"; -} - -subgraph cluster_system_dvfs_handler { -color="#000000"; -fillcolor="#bab6ae"; -fontcolor="#000000"; -fontname=Arial; -fontsize=14; -label="dvfs_handler \n: DVFSHandler"; -shape=Mrecord; -style="rounded, filled"; -tooltip="domains= enable=false eventq_index=0 sys_clk_domain=system.clk_domain transition_latency=100000000"; -} - -subgraph cluster_system_cpu_clk_domain { -color="#000000"; -fillcolor="#bab6ae"; -fontcolor="#000000"; -fontname=Arial; -fontsize=14; -label="cpu_clk_domain \n: SrcClockDomain"; -shape=Mrecord; -style="rounded, filled"; -tooltip="clock=500 domain_id=-1 eventq_index=0 init_perf_level=0 voltage_domain=system.cpu_voltage_domain"; -} - -subgraph cluster_system_cpu { -color="#000000"; -fillcolor="#bbc6d9"; -fontcolor="#000000"; -fontname=Arial; -fontsize=14; -label="cpu \n: TimingSimpleCPU"; -shape=Mrecord; -style="rounded, filled"; -tooltip="branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts isa=system.cpu.isa itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_gating_on_idle=false power_model= profile=0 progress_interval=0 pwr_gating_latency=300 simpoint_start_insts= socket_id=0 switched_out=false syscallRetryLatency=10000 system=system tracer=system.cpu.tracer wait_for_remote_gdb=false workload=system.cpu.workload"; -system_cpu_icache_port [color="#000000", fillcolor="#959ead", fontcolor="#000000", fontname=Arial, fontsize=14, label=icache_port, shape=Mrecord, style="rounded, filled"]; -system_cpu_dcache_port [color="#000000", fillcolor="#959ead", fontcolor="#000000", fontname=Arial, fontsize=14, label=dcache_port, shape=Mrecord, style="rounded, filled"]; -subgraph cluster_system_cpu_workload { -color="#000000"; -fillcolor="#bab6ae"; -fontcolor="#000000"; -fontname=Arial; -fontsize=14; -label="workload \n: Process"; -shape=Mrecord; -style="rounded, filled"; -tooltip="cmd=tests/test-progs/hello/bin/x86/linux/hello cwd=/media/disk2/gem5_tnt/gem5 drivers= egid=100 env= errout=cerr euid=100 eventq_index=0 executable=tests/test-progs/hello/bin/x86/linux/hello gid=100 input=cin kvmInSE=false maxStackSize=67108864 output=cout pgid=100 pid=100 ppid=0 simpoint=0 system=system uid=100 useArchPT=false"; -} - -subgraph cluster_system_cpu_apic_clk_domain { -color="#000000"; -fillcolor="#bab6ae"; -fontcolor="#000000"; -fontname=Arial; -fontsize=14; -label="apic_clk_domain \n: DerivedClockDomain"; -shape=Mrecord; -style="rounded, filled"; -tooltip="clk_divider=16 clk_domain=system.cpu_clk_domain eventq_index=0"; -} - -subgraph cluster_system_cpu_dtb { -color="#000000"; -fillcolor="#bab6ae"; -fontcolor="#000000"; -fontname=Arial; -fontsize=14; -label="dtb \n: X86TLB"; -shape=Mrecord; -style="rounded, filled"; -tooltip="eventq_index=0 size=64 walker=system.cpu.dtb.walker"; -subgraph cluster_system_cpu_dtb_walker { -color="#000000"; -fillcolor="#9f9c95"; -fontcolor="#000000"; -fontname=Arial; -fontsize=14; -label="walker \n: X86PagetableWalker"; -shape=Mrecord; -style="rounded, filled"; -tooltip="clk_domain=system.cpu_clk_domain default_p_state=UNDEFINED eventq_index=0 num_squash_per_cycle=4 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model= system=system"; -system_cpu_dtb_walker_port [color="#000000", fillcolor="#7f7c77", fontcolor="#000000", fontname=Arial, fontsize=14, label=port, shape=Mrecord, style="rounded, filled"]; -} - -} - -subgraph cluster_system_cpu_interrupts { -color="#000000"; -fillcolor="#c7a793"; -fontcolor="#000000"; -fontname=Arial; -fontsize=14; -label="interrupts \n: X86LocalApic"; -shape=Mrecord; -style="rounded, filled"; -tooltip="clk_domain=system.cpu.apic_clk_domain default_p_state=UNDEFINED eventq_index=0 int_latency=1000 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 pio_addr=2305843009213693952 pio_latency=100000 power_model= system=system"; -system_cpu_interrupts_int_slave [color="#000000", fillcolor="#9f8575", fontcolor="#000000", fontname=Arial, fontsize=14, label=int_slave, shape=Mrecord, style="rounded, filled"]; -system_cpu_interrupts_int_master [color="#000000", fillcolor="#9f8575", fontcolor="#000000", fontname=Arial, fontsize=14, label=int_master, shape=Mrecord, style="rounded, filled"]; -system_cpu_interrupts_pio [color="#000000", fillcolor="#9f8575", fontcolor="#000000", fontname=Arial, fontsize=14, label=pio, shape=Mrecord, style="rounded, filled"]; -} - -subgraph cluster_system_cpu_itb { -color="#000000"; -fillcolor="#bab6ae"; -fontcolor="#000000"; -fontname=Arial; -fontsize=14; -label="itb \n: X86TLB"; -shape=Mrecord; -style="rounded, filled"; -tooltip="eventq_index=0 size=64 walker=system.cpu.itb.walker"; -subgraph cluster_system_cpu_itb_walker { -color="#000000"; -fillcolor="#9f9c95"; -fontcolor="#000000"; -fontname=Arial; -fontsize=14; -label="walker \n: X86PagetableWalker"; -shape=Mrecord; -style="rounded, filled"; -tooltip="clk_domain=system.cpu_clk_domain default_p_state=UNDEFINED eventq_index=0 num_squash_per_cycle=4 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model= system=system"; -system_cpu_itb_walker_port [color="#000000", fillcolor="#7f7c77", fontcolor="#000000", fontname=Arial, fontsize=14, label=port, shape=Mrecord, style="rounded, filled"]; -} - -} - -subgraph cluster_system_cpu_isa { -color="#000000"; -fillcolor="#bab6ae"; -fontcolor="#000000"; -fontname=Arial; -fontsize=14; -label="isa \n: X86ISA"; -shape=Mrecord; -style="rounded, filled"; -tooltip="eventq_index=0"; -} - -subgraph cluster_system_cpu_tracer { -color="#000000"; -fillcolor="#bab6ae"; -fontcolor="#000000"; -fontname=Arial; -fontsize=14; -label="tracer \n: ExeTracer"; -shape=Mrecord; -style="rounded, filled"; -tooltip="eventq_index=0"; -} - -} - -} - -} - -system_system_port -> system_membus_slave; -system_membus_master -> system_cpu_interrupts_pio; -system_membus_master -> system_cpu_interrupts_int_slave; -system_membus_master -> system_external_memory_port; -system_cpu_icache_port -> system_membus_slave; -system_cpu_dcache_port -> system_membus_slave; -system_cpu_dtb_walker_port -> system_membus_slave; -system_cpu_interrupts_int_master -> system_membus_slave; -system_cpu_itb_walker_port -> system_membus_slave; -} diff --git a/DRAMSys/gem5/gem5_se/hello-x86/config.dot.pdf b/DRAMSys/gem5/gem5_se/hello-x86/config.dot.pdf deleted file mode 100644 index e1f465e9..00000000 Binary files a/DRAMSys/gem5/gem5_se/hello-x86/config.dot.pdf and /dev/null differ diff --git a/DRAMSys/gem5/gem5_se/hello-x86/config.dot.svg b/DRAMSys/gem5/gem5_se/hello-x86/config.dot.svg deleted file mode 100644 index d2c806f2..00000000 --- a/DRAMSys/gem5/gem5_se/hello-x86/config.dot.svg +++ /dev/null @@ -1,193 +0,0 @@ - - - - - - -G - -cluster_root - - -root -: Root - - - -cluster_system - - -system -: System - - - -cluster_system_membus - - -membus -: SystemXBar - - - -cluster_system_external_memory - - -external_memory -: ExternalSlave - - - -cluster_system_cpu - - -cpu -: TimingSimpleCPU - - - -cluster_system_cpu_dtb - - -dtb -: X86TLB - - - -cluster_system_cpu_dtb_walker - - -walker -: X86PagetableWalker - - - -cluster_system_cpu_interrupts - - -interrupts -: X86LocalApic - - - -cluster_system_cpu_itb - - -itb -: X86TLB - - - -cluster_system_cpu_itb_walker - - -walker -: X86PagetableWalker - - - - -system_system_port - -system_port - - -system_membus_slave - -slave - - -system_system_port->system_membus_slave - - - - -system_membus_master - -master - - -system_external_memory_port - -port - - -system_membus_master->system_external_memory_port - - - - -system_cpu_interrupts_int_slave - -int_slave - - -system_membus_master->system_cpu_interrupts_int_slave - - - - -system_cpu_interrupts_pio - -pio - - -system_membus_master->system_cpu_interrupts_pio - - - - -system_cpu_icache_port - -icache_port - - -system_cpu_icache_port->system_membus_slave - - - - -system_cpu_dcache_port - -dcache_port - - -system_cpu_dcache_port->system_membus_slave - - - - -system_cpu_dtb_walker_port - -port - - -system_cpu_dtb_walker_port->system_membus_slave - - - - -system_cpu_interrupts_int_master - -int_master - - -system_cpu_interrupts_int_master->system_membus_slave - - - - -system_cpu_itb_walker_port - -port - - -system_cpu_itb_walker_port->system_membus_slave - - - - - diff --git a/DRAMSys/gem5/gem5_se/hello-x86/config.json b/DRAMSys/gem5/gem5_se/hello-x86/config.json deleted file mode 100644 index 8b3e80bc..00000000 --- a/DRAMSys/gem5/gem5_se/hello-x86/config.json +++ /dev/null @@ -1,397 +0,0 @@ -{ - "name": null, - "sim_quantum": 0, - "system": { - "kernel": "", - "mmap_using_noreserve": false, - "kernel_addr_check": false, - "membus": { - "point_of_coherency": true, - "system": "system", - "response_latency": 2, - "cxx_class": "CoherentXBar", - "forward_latency": 4, - "clk_domain": "system.clk_domain", - "point_of_unification": true, - "width": 16, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "master": { - "peer": [ - "system.cpu.interrupts.pio", - "system.cpu.interrupts.int_slave", - "system.external_memory.port" - ], - "role": "MASTER" - }, - "type": "CoherentXBar", - "frontend_latency": 3, - "slave": { - "peer": [ - "system.system_port", - "system.cpu.icache_port", - "system.cpu.dcache_port", - "system.cpu.itb.walker.port", - "system.cpu.dtb.walker.port", - "system.cpu.interrupts.int_master" - ], - "role": "SLAVE" - }, - "p_state_clk_gate_min": 1000, - "snoop_filter": { - "name": "snoop_filter", - "system": "system", - "max_capacity": 8388608, - "eventq_index": 0, - "cxx_class": "SnoopFilter", - "path": "system.membus.snoop_filter", - "type": "SnoopFilter", - "lookup_latency": 1 - }, - "power_model": [], - "path": "system.membus", - "snoop_response_latency": 4, - "name": "membus", - "p_state_clk_gate_bins": 20, - "use_default_range": false - }, - "symbolfile": "", - "kvm_vm": null, - "readfile": "", - "thermal_model": null, - "cxx_class": "System", - "work_begin_cpu_id_exit": -1, - "load_offset": 0, - "work_begin_exit_count": 0, - "p_state_clk_gate_min": 1000, - "memories": [ - "system.physmem" - ], - "work_begin_ckpt_count": 0, - "clk_domain": { - "name": "clk_domain", - "clock": [ - 1000 - ], - "init_perf_level": 0, - "voltage_domain": "system.voltage_domain", - "eventq_index": 0, - "cxx_class": "SrcClockDomain", - "path": "system.clk_domain", - "type": "SrcClockDomain", - "domain_id": -1 - }, - "mem_ranges": [ - "0:536870911:0:0:0:0" - ], - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "dvfs_handler": { - "enable": false, - "name": "dvfs_handler", - "sys_clk_domain": "system.clk_domain", - "transition_latency": 100000000, - "eventq_index": 0, - "cxx_class": "DVFSHandler", - "domains": [], - "path": "system.dvfs_handler", - "type": "DVFSHandler" - }, - "work_end_exit_count": 0, - "type": "System", - "voltage_domain": { - "name": "voltage_domain", - "eventq_index": 0, - "voltage": [ - 1.0 - ], - "cxx_class": "VoltageDomain", - "path": "system.voltage_domain", - "type": "VoltageDomain" - }, - "cache_line_size": 64, - "external_memory": { - "name": "external_memory", - "p_state_clk_gate_min": 1000, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "clk_domain": "system.clk_domain", - "power_model": [], - "addr_ranges": [ - "0:536870911:0:0:0:0" - ], - "eventq_index": 0, - "port_type": "tlm_slave", - "cxx_class": "ExternalSlave", - "p_state_clk_gate_max": 1000000000000, - "path": "system.external_memory", - "type": "ExternalSlave", - "port": { - "peer": "system.membus.master[2]", - "role": "SLAVE" - }, - "port_data": "transactor" - }, - "boot_osflags": "a", - "system_port": { - "peer": "system.membus.slave[0]", - "role": "MASTER" - }, - "physmem": { - "range": "0:134217727:0:0:0:0", - "latency": 30000, - "name": "physmem", - "p_state_clk_gate_min": 1000, - "eventq_index": 0, - "p_state_clk_gate_bins": 20, - "default_p_state": "UNDEFINED", - "kvm_map": true, - "clk_domain": "system.clk_domain", - "power_model": [], - "latency_var": 0, - "bandwidth": "73.000000", - "conf_table_reported": true, - "cxx_class": "SimpleMemory", - "p_state_clk_gate_max": 1000000000000, - "path": "system.physmem", - "null": false, - "type": "SimpleMemory", - "in_addr_map": true - }, - "power_model": [], - "work_cpus_ckpt_count": 0, - "thermal_components": [], - "path": "system", - "cpu_clk_domain": { - "name": "cpu_clk_domain", - "clock": [ - 500 - ], - "init_perf_level": 0, - "voltage_domain": "system.cpu_voltage_domain", - "eventq_index": 0, - "cxx_class": "SrcClockDomain", - "path": "system.cpu_clk_domain", - "type": "SrcClockDomain", - "domain_id": -1 - }, - "work_end_ckpt_count": 0, - "mem_mode": "timing", - "name": "system", - "init_param": 0, - "p_state_clk_gate_bins": 20, - "kernel_extras": [], - "load_addr_mask": 18446744073709551615, - "cpu": [ - { - "do_statistics_insts": true, - "numThreads": 1, - "itb": { - "name": "itb", - "eventq_index": 0, - "cxx_class": "X86ISA::TLB", - "walker": { - "name": "walker", - "p_state_clk_gate_min": 1000, - "p_state_clk_gate_bins": 20, - "cxx_class": "X86ISA::Walker", - "clk_domain": "system.cpu_clk_domain", - "power_model": [], - "system": "system", - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu.itb.walker", - "type": "X86PagetableWalker", - "port": { - "peer": "system.membus.slave[3]", - "role": "MASTER" - }, - "num_squash_per_cycle": 4 - }, - "path": "system.cpu.itb", - "type": "X86TLB", - "size": 64 - }, - "power_gating_on_idle": false, - "function_trace": false, - "do_checkpoint_insts": true, - "cxx_class": "TimingSimpleCPU", - "max_loads_all_threads": 0, - "system": "system", - "apic_clk_domain": { - "name": "apic_clk_domain", - "clk_domain": "system.cpu_clk_domain", - "eventq_index": 0, - "cxx_class": "DerivedClockDomain", - "path": "system.cpu.apic_clk_domain", - "type": "DerivedClockDomain", - "clk_divider": 16 - }, - "clk_domain": "system.cpu_clk_domain", - "function_trace_start": 0, - "cpu_id": 0, - "checker": null, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "do_quiesce": true, - "type": "TimingSimpleCPU", - "profile": 0, - "icache_port": { - "peer": "system.membus.slave[1]", - "role": "MASTER" - }, - "p_state_clk_gate_bins": 20, - "p_state_clk_gate_min": 1000, - "syscallRetryLatency": 10000, - "interrupts": [ - { - "int_master": { - "peer": "system.membus.slave[5]", - "role": "MASTER" - }, - "name": "interrupts", - "p_state_clk_gate_min": 1000, - "pio": { - "peer": "system.membus.master[0]", - "role": "SLAVE" - }, - "int_slave": { - "peer": "system.membus.master[1]", - "role": "SLAVE" - }, - "p_state_clk_gate_bins": 20, - "cxx_class": "X86ISA::Interrupts", - "pio_latency": 100000, - "clk_domain": "system.cpu.apic_clk_domain", - "power_model": [], - "system": "system", - "int_latency": 1000, - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu.interrupts", - "pio_addr": 2305843009213693952, - "type": "X86LocalApic" - } - ], - "dcache_port": { - "peer": "system.membus.slave[2]", - "role": "MASTER" - }, - "socket_id": 0, - "power_model": [], - "max_insts_all_threads": 0, - "path": "system.cpu", - "pwr_gating_latency": 300, - "max_loads_any_thread": 0, - "switched_out": false, - "workload": [ - { - "uid": 100, - "pid": 100, - "kvmInSE": false, - "cxx_class": "Process", - "executable": "tests/test-progs/hello/bin/x86/linux/hello", - "drivers": [], - "system": "system", - "gid": 100, - "eventq_index": 0, - "env": [], - "maxStackSize": 67108864, - "ppid": 0, - "type": "Process", - "cwd": "/media/disk2/gem5_tnt/gem5", - "pgid": 100, - "simpoint": 0, - "euid": 100, - "input": "cin", - "path": "system.cpu.workload", - "name": "workload", - "cmd": [ - "tests/test-progs/hello/bin/x86/linux/hello" - ], - "errout": "cerr", - "useArchPT": false, - "egid": 100, - "output": "cout" - } - ], - "name": "cpu", - "wait_for_remote_gdb": false, - "dtb": { - "name": "dtb", - "eventq_index": 0, - "cxx_class": "X86ISA::TLB", - "walker": { - "name": "walker", - "p_state_clk_gate_min": 1000, - "p_state_clk_gate_bins": 20, - "cxx_class": "X86ISA::Walker", - "clk_domain": "system.cpu_clk_domain", - "power_model": [], - "system": "system", - "eventq_index": 0, - "default_p_state": "UNDEFINED", - "p_state_clk_gate_max": 1000000000000, - "path": "system.cpu.dtb.walker", - "type": "X86PagetableWalker", - "port": { - "peer": "system.membus.slave[4]", - "role": "MASTER" - }, - "num_squash_per_cycle": 4 - }, - "path": "system.cpu.dtb", - "type": "X86TLB", - "size": 64 - }, - "simpoint_start_insts": [], - "max_insts_any_thread": 0, - "progress_interval": 0, - "branchPred": null, - "isa": [ - { - "eventq_index": 0, - "path": "system.cpu.isa", - "type": "X86ISA", - "name": "isa", - "cxx_class": "X86ISA::ISA" - } - ], - "tracer": { - "eventq_index": 0, - "path": "system.cpu.tracer", - "type": "ExeTracer", - "name": "tracer", - "cxx_class": "Trace::ExeTracer" - } - } - ], - "multi_thread": false, - "cpu_voltage_domain": { - "name": "cpu_voltage_domain", - "eventq_index": 0, - "voltage": [ - 1.0 - ], - "cxx_class": "VoltageDomain", - "path": "system.cpu_voltage_domain", - "type": "VoltageDomain" - }, - "num_work_ids": 16, - "work_item_id": -1, - "exit_on_work_items": false - }, - "time_sync_period": 100000000000, - "eventq_index": 0, - "time_sync_spin_threshold": 100000000, - "cxx_class": "Root", - "path": "root", - "time_sync_enable": false, - "type": "Root", - "full_system": false -} \ No newline at end of file diff --git a/DRAMSys/gem5/gem5_se/run.sh b/DRAMSys/gem5/gem5_se/run.sh deleted file mode 100755 index 196d3fe8..00000000 --- a/DRAMSys/gem5/gem5_se/run.sh +++ /dev/null @@ -1,105 +0,0 @@ -#! /bin/bash - -# Copyright (c) 2018, Technische Universität Kaiserslautern -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the copyright holder nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER -# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Author: Éder F. Zulian - -simfiles=" -ddr3-gem5-se.xml -" - -bins=" -8_cores -Bubblesort -chomp -exptree -FloatMM -IntMM -misr -Oscar -Perm -Puzzle -Queens -Quicksort -RealMM -Towers -Treesort -" - -DIR="$(cd "$(dirname "$0")" && pwd)" -basedir="$DIR/../../.." -sfpath="../../DRAMSys/library/resources/simulations" -elf="DRAMSys_gem5" - -if [[ -z "${GEM5}" ]]; then - echo "GEM5 environment variable is undefined" - exit 1 -fi - -proj_build() { - if [[ $(hostname -s) =~ ^head[0-9]+$ ]] || [[ $(hostname -s) =~ ^node[0-9]+$ ]]; then - # Elwetritsch cluster - heads or nodes - module load qt/latest - #module load anaconda3/latest - fi - cd $basedir - rm -rf build - mkdir -p build - cd build - qmake ../DRAMSys/DRAMSys.pro - nprocs=$(cat /proc/cpuinfo | grep processor | wc -l) - make -j$nprocs -} - -proj_build - -cd $basedir/build/gem5 -if [ ! -f ${elf} ]; then - echo "${elf} could not be found" - exit 1 -fi - -for s in $simfiles; do - sf="${sfpath}/${s}" - sfn="${s%.*}" - ext="${s##*.}" - for bin in $bins; do - `sed -i s/id=\".*\"/id=\"${sfn}_${bin}\"/g $sf` - simulation="${sfpath}/${sfn}_${bin}.${ext}" - cp $sf $simulation - logfile=${sfn}_${bin}.log - # LD_PRELOAD=/usr/lib/libtcmalloc.so ./${elf} ${simulation} ../../DRAMSys/gem5/gem5_se/${bin}/config.ini 1 > ${logfile} 2>&1 & - date >> ${logfile} - time ./${elf} ${simulation} ../../DRAMSys/gem5/gem5_se/${bin}/config.ini 1 >> ${logfile} 2>&1 - date >> ${logfile} - done -done - diff --git a/DRAMSys/gem5/images/gem5_se_mode_arch.svg b/DRAMSys/gem5/images/gem5_se_mode_arch.svg deleted file mode 100644 index e7ba558a..00000000 --- a/DRAMSys/gem5/images/gem5_se_mode_arch.svg +++ /dev/null @@ -1,247 +0,0 @@ - - - - - - -G - -cluster_root - - -root -: Root - - - -cluster_system - - -system -: System - - - -cluster_system_membus - - -membus -: SystemXBar - - - -cluster_system_external_memory - - -external_memory -: ExternalSlave - - - -cluster_system_tol2bus - - -tol2bus -: L2XBar - - - -cluster_system_l2 - - -l2 -: L2Cache - - - -cluster_system_cpu - - -cpu -: TimingSimpleCPU - - - -cluster_system_cpu_dtb - - -dtb -: ArmTLB - - - -cluster_system_cpu_dtb_walker - - -walker -: ArmTableWalker - - - -cluster_system_cpu_itb - - -itb -: ArmTLB - - - -cluster_system_cpu_itb_walker - - -walker -: ArmTableWalker - - - -cluster_system_cpu_icache - - -icache -: L1_ICache - - - -cluster_system_cpu_dcache - - -dcache -: L1_DCache - - - - -system_system_port - -system_port - - -system_membus_slave - -slave - - -system_system_port->system_membus_slave - - - - -system_membus_master - -master - - -system_external_memory_port - -port - - -system_membus_master->system_external_memory_port - - - - -system_tol2bus_master - -master - - -system_l2_cpu_side - -cpu_side - - -system_tol2bus_master->system_l2_cpu_side - - - - -system_tol2bus_slave - -slave - - -system_l2_mem_side - -mem_side - - -system_l2_mem_side->system_membus_slave - - - - -system_cpu_icache_port - -icache_port - - -system_cpu_icache_cpu_side - -cpu_side - - -system_cpu_icache_port->system_cpu_icache_cpu_side - - - - -system_cpu_dcache_port - -dcache_port - - -system_cpu_dcache_cpu_side - -cpu_side - - -system_cpu_dcache_port->system_cpu_dcache_cpu_side - - - - -system_cpu_dtb_walker_port - -port - - -system_cpu_dtb_walker_port->system_tol2bus_slave - - - - -system_cpu_itb_walker_port - -port - - -system_cpu_itb_walker_port->system_tol2bus_slave - - - - -system_cpu_icache_mem_side - -mem_side - - -system_cpu_icache_mem_side->system_tol2bus_slave - - - - -system_cpu_dcache_mem_side - -mem_side - - -system_cpu_dcache_mem_side->system_tol2bus_slave - - - - -