diff --git a/DRAMSys/library/src/common/TlmRecorder.cpp b/DRAMSys/library/src/common/TlmRecorder.cpp index f4c23c03..4357843a 100644 --- a/DRAMSys/library/src/common/TlmRecorder.cpp +++ b/DRAMSys/library/src/common/TlmRecorder.cpp @@ -259,14 +259,6 @@ void TlmRecorder::setUpTransactionTerminatingPhases() (END_PDNP)); transactionTerminatingPhases.push_back(static_cast (END_SREF)); - - // Phases for Power Down Bankwise - transactionTerminatingPhases.push_back(static_cast - (END_PDNAB)); - transactionTerminatingPhases.push_back(static_cast - (END_PDNPB)); - transactionTerminatingPhases.push_back(static_cast - (END_SREFB)); } void TlmRecorder::prepareSqlStatements() diff --git a/DRAMSys/library/src/common/protocol.h b/DRAMSys/library/src/common/protocol.h index 986ef847..e8851b88 100644 --- a/DRAMSys/library/src/common/protocol.h +++ b/DRAMSys/library/src/common/protocol.h @@ -38,54 +38,32 @@ #ifndef PROTOCOL_H #define PROTOCOL_H -// DRAM Control Phases -DECLARE_EXTENDED_PHASE(BEGIN_PRE); -DECLARE_EXTENDED_PHASE(END_PRE); - -DECLARE_EXTENDED_PHASE(BEGIN_PREA); -DECLARE_EXTENDED_PHASE(END_PREA); - -DECLARE_EXTENDED_PHASE(BEGIN_ACT); -DECLARE_EXTENDED_PHASE(END_ACT); - -DECLARE_EXTENDED_PHASE(BEGIN_REFA); -DECLARE_EXTENDED_PHASE(END_REFA); - -DECLARE_EXTENDED_PHASE(BEGIN_REFB); -DECLARE_EXTENDED_PHASE(END_REFB); - -// Phases for Read and Write -DECLARE_EXTENDED_PHASE(BEGIN_WR); -DECLARE_EXTENDED_PHASE(END_WR); - +// DO NOT CHANGE THE ORDER! DECLARE_EXTENDED_PHASE(BEGIN_RD); -DECLARE_EXTENDED_PHASE(END_RD); - -DECLARE_EXTENDED_PHASE(BEGIN_WRA); -DECLARE_EXTENDED_PHASE(END_WRA); - +DECLARE_EXTENDED_PHASE(BEGIN_WR); DECLARE_EXTENDED_PHASE(BEGIN_RDA); -DECLARE_EXTENDED_PHASE(END_RDA); - -// Phases for Power Down -DECLARE_EXTENDED_PHASE(BEGIN_PDNP); -DECLARE_EXTENDED_PHASE(END_PDNP); - +DECLARE_EXTENDED_PHASE(BEGIN_WRA); +DECLARE_EXTENDED_PHASE(BEGIN_PRE); +DECLARE_EXTENDED_PHASE(BEGIN_ACT); +DECLARE_EXTENDED_PHASE(BEGIN_REFB); +DECLARE_EXTENDED_PHASE(BEGIN_PREA); +DECLARE_EXTENDED_PHASE(BEGIN_REFA); DECLARE_EXTENDED_PHASE(BEGIN_PDNA); DECLARE_EXTENDED_PHASE(END_PDNA); - +DECLARE_EXTENDED_PHASE(BEGIN_PDNP); +DECLARE_EXTENDED_PHASE(END_PDNP); DECLARE_EXTENDED_PHASE(BEGIN_SREF); DECLARE_EXTENDED_PHASE(END_SREF); -// Phases for Power Down Bankwise -DECLARE_EXTENDED_PHASE(BEGIN_PDNPB); -DECLARE_EXTENDED_PHASE(END_PDNPB); - -DECLARE_EXTENDED_PHASE(BEGIN_PDNAB); -DECLARE_EXTENDED_PHASE(END_PDNAB); - -DECLARE_EXTENDED_PHASE(BEGIN_SREFB); -DECLARE_EXTENDED_PHASE(END_SREFB); +DECLARE_EXTENDED_PHASE(END_RD); +DECLARE_EXTENDED_PHASE(END_WR); +DECLARE_EXTENDED_PHASE(END_RDA); +DECLARE_EXTENDED_PHASE(END_WRA); +DECLARE_EXTENDED_PHASE(END_PRE); +DECLARE_EXTENDED_PHASE(END_ACT); +DECLARE_EXTENDED_PHASE(END_REFB); +DECLARE_EXTENDED_PHASE(END_PREA); +DECLARE_EXTENDED_PHASE(END_REFA); #endif // PROTOCOL_H diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp index b6f74ddd..b0396643 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.cpp +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.cpp @@ -47,16 +47,6 @@ MemSpec::MemSpec() commandLengthInCycles = std::vector(numberOfCommands(), 1); } -const std::vector &MemSpec::getBanks() const -{ - static std::vector banks; - if (banks.size() == 0) { - for (unsigned int i = 0; i < numberOfBanks; i++) - banks.push_back(Bank(i)); - } - return banks; -} - sc_time MemSpec::getCommandLength(Command command) const { return tCK * commandLengthInCycles[command]; diff --git a/DRAMSys/library/src/configuration/memspec/MemSpec.h b/DRAMSys/library/src/configuration/memspec/MemSpec.h index 5589a767..b56a03fb 100644 --- a/DRAMSys/library/src/configuration/memspec/MemSpec.h +++ b/DRAMSys/library/src/configuration/memspec/MemSpec.h @@ -51,8 +51,6 @@ struct MemSpec MemSpec(); virtual ~MemSpec() {} - const std::vector &getBanks() const; - virtual sc_time getRefreshIntervalAB() const = 0; virtual sc_time getRefreshIntervalPB() const = 0; diff --git a/DRAMSys/library/src/controller/Command.cpp b/DRAMSys/library/src/controller/Command.cpp index 290f7c44..1a534ccb 100644 --- a/DRAMSys/library/src/controller/Command.cpp +++ b/DRAMSys/library/src/controller/Command.cpp @@ -40,86 +40,26 @@ std::string commandToString(Command command) -{ - switch (command) { - case Command::RD: - return "RD"; - break; - case Command::RDA: - return "RDA"; - break; - case Command::WR: - return "WR"; - break; - case Command::WRA: - return "WRA"; - break; - case Command::PRE: - return "PRE"; - break; - case Command::ACT: - return "ACT"; - break; - case Command::PREA: - return "PREA"; - break; - case Command::REFA: - return "REFA"; - break; - case Command::REFB: - return "REFB"; - break; - case Command::PDEA: - return "PDEA"; - break; - case Command::PDXA: - return "PDXA"; - break; - case Command::PDEP: - return "PDEP"; - break; - case Command::PDXP: - return "PDXP"; - break; - case Command::SREFEN: - return "SREFEN"; - break; - case Command::SREFEX: - return "SREFEX"; - break; - - case Command::NOP: - return "NOP"; - break; - - default: - SC_REPORT_FATAL("command", "commandToString was called with unknown command"); - break; - } - - return ""; -} - -const std::vector &getAllCommands() -{ - static std::vector allCommands( { Command::NOP, - Command::RD, - Command::WR, - Command::RDA, - Command::WRA, - Command::PRE, - Command::ACT, - Command::REFB, - Command::PREA, - Command::REFA, - Command::PDEA, - Command::PDXA, - Command::PDEP, - Command::PDXP, - Command::SREFEN, - Command::SREFEX - }); - return allCommands; +{ + assert(command >= 0 && command <= 15); + static std::array stringOfCommand = + {"NOP", + "RD", + "WR", + "RDA", + "WRA", + "PRE", + "ACT", + "REFB", + "PREA", + "REFA", + "PDEA", + "PDXA", + "PDEP", + "PDXP", + "SREFEN", + "SREFEX"}; + return stringOfCommand[command]; } unsigned numberOfCommands() @@ -127,48 +67,49 @@ unsigned numberOfCommands() return 16; } -bool commandIsIn(Command command, std::vector commands) +tlm_phase commandToPhase(Command command) { - for (Command c : commands) { - if (c == command) - return true; - } - return false; + assert(command >= 0 && command <= 15); + static std::array phaseOfCommand = + {UNINITIALIZED_PHASE, + BEGIN_RD, + BEGIN_WR, + BEGIN_RDA, + BEGIN_WRA, + BEGIN_PRE, + BEGIN_ACT, + BEGIN_REFB, + BEGIN_PREA, + BEGIN_REFA, + BEGIN_PDNA, + END_PDNA, + BEGIN_PDNP, + END_PDNP, + BEGIN_SREF, + END_SREF}; + return phaseOfCommand[command]; } -std::array phaseOfCommand = {UNINITIALIZED_PHASE, - BEGIN_RD, - BEGIN_WR, - BEGIN_RDA, - BEGIN_WRA, - BEGIN_PRE, - BEGIN_ACT, - BEGIN_REFB, - BEGIN_PREA, - BEGIN_REFA, - BEGIN_PDNA, - END_PDNA, - BEGIN_PDNP, - END_PDNP, - BEGIN_SREF, - END_SREF}; - bool isBankCommand(Command command) { + assert(command >= 0 && command <= 15); return (command <= 7); } bool isRankCommand(Command command) { + assert(command >= 0 && command <= 15); return (command >= 8); } bool isCasCommand(Command command) { + assert(command >= 0 && command <= 15); return (command <= 4); } bool isRasCommand(Command command) { + assert(command >= 0 && command <= 15); return (command >= 5); } diff --git a/DRAMSys/library/src/controller/Command.h b/DRAMSys/library/src/controller/Command.h index 8365ef4d..f0902670 100644 --- a/DRAMSys/library/src/controller/Command.h +++ b/DRAMSys/library/src/controller/Command.h @@ -64,15 +64,12 @@ enum Command SREFEX }; -std::string commandToString(Command command); -const std::vector &getAllCommands(); +std::string commandToString(Command); +tlm_phase commandToPhase(Command); unsigned numberOfCommands(); -bool commandIsIn(Command command, std::vector commands); -bool isBankCommand(Command command); -bool isRankCommand(Command command); -bool isCasCommand(Command command); -bool isRasCommand(Command command); - -extern std::array phaseOfCommand; +bool isBankCommand(Command); +bool isRankCommand(Command); +bool isCasCommand(Command); +bool isRasCommand(Command); #endif // COMMAND_H diff --git a/DRAMSys/library/src/controller/Controller.cpp b/DRAMSys/library/src/controller/Controller.cpp index 6aeecb1a..f533cd5f 100644 --- a/DRAMSys/library/src/controller/Controller.cpp +++ b/DRAMSys/library/src/controller/Controller.cpp @@ -37,6 +37,7 @@ #include "../configuration/Configuration.h" #include "../common/dramExtensions.h" #include "../common/protocol.h" +#include "Command.h" #include "checker/CheckerDDR3.h" #include "checker/CheckerDDR4.h" #include "checker/CheckerWideIO.h" @@ -445,7 +446,7 @@ void Controller::sendToFrontend(tlm_generic_payload *payload, tlm_phase phase) void Controller::sendToDram(Command command, tlm_generic_payload *payload) { sc_time delay = SC_ZERO_TIME; - tlm_phase phase = phaseOfCommand[command]; + tlm_phase phase = commandToPhase(command); iSocket->nb_transport_fw(*payload, phase, delay); } diff --git a/DRAMSys/library/src/controller/ControllerRecordable.cpp b/DRAMSys/library/src/controller/ControllerRecordable.cpp index aa2c7722..97b1a542 100644 --- a/DRAMSys/library/src/controller/ControllerRecordable.cpp +++ b/DRAMSys/library/src/controller/ControllerRecordable.cpp @@ -60,7 +60,7 @@ void ControllerRecordable::sendToFrontend(tlm_generic_payload *payload, tlm_phas void ControllerRecordable::sendToDram(Command command, tlm_generic_payload *payload) { - if (commandIsIn(command, {Command::RD, Command::RDA, Command::WR, Command::WRA})) + if (isCasCommand(command)) { TimeInterval dataStrobe = Configuration::getInstance().memSpec->getIntervalOnDataStrobe(command); tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, *payload); diff --git a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp index b3474777..8aa14629 100644 --- a/DRAMSys/library/src/simulation/dram/DramRecordable.cpp +++ b/DRAMSys/library/src/simulation/dram/DramRecordable.cpp @@ -88,11 +88,11 @@ tlm_sync_enum DramRecordable::nb_transport_fw(tlm_generic_payload &pay // These are terminating phases recorded by the DRAM. The execution // time of the related command must be taken into consideration. - if (phase == END_PDNA || phase == END_PDNAB) + if (phase == END_PDNA) recTime += this->memSpec->getCommandLength(Command::PDXA); - else if (phase == END_PDNP || phase == END_PDNPB) + else if (phase == END_PDNP) recTime += this->memSpec->getCommandLength(Command::PDXP); - else if (phase == END_SREF || phase == END_SREFB) + else if (phase == END_SREF) recTime += this->memSpec->getCommandLength(Command::SREFEX); unsigned int thr __attribute__((unused)) = DramExtension::getExtension(payload).getThread().ID(); diff --git a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp index b0339631..fb3c1731 100644 --- a/DRAMSys/library/src/simulation/dram/DramWideIO.cpp +++ b/DRAMSys/library/src/simulation/dram/DramWideIO.cpp @@ -176,7 +176,7 @@ tlm_sync_enum DramWideIO::nb_transport_fw(tlm_generic_payload &payload, unsigned int bank = DramExtension::getExtension(payload).getBank().ID(); // This is only needed for power simulation: - unsigned long long cycle = sc_time_stamp().value() / memSpec->tCK.value(); + unsigned long long cycle = sc_time_stamp() / memSpec->tCK; if (phase == BEGIN_PRE) {