diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp index 72ee2b2d..9ec6afb7 100644 --- a/DRAMSys/library/src/controller/ControllerNew.cpp +++ b/DRAMSys/library/src/controller/ControllerNew.cpp @@ -21,13 +21,13 @@ ControllerNew::ControllerNew(sc_module_name name, TlmRecorder *tlmRecorder) : state = new ControllerState("Controller", &Configuration::getInstance()); checker = new CheckerDDR3New(Configuration::getInstance(), *state); - scheduler = new SchedulerFrFcfs(); + scheduler = new SchedulerFifo(); for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) { bankMachines[Bank(bankID)] = new BankMachine(scheduler, checker, Bank(bankID)); commandFinishedTime[Bank(bankID)] = SC_ZERO_TIME; } - commandMux = new CmdMuxOldest(); + commandMux = new CmdMuxStrict(); } ControllerNew::~ControllerNew() @@ -155,12 +155,9 @@ void ControllerNew::controllerMethod() if (payloadToRelease == nullptr && !responseQueue.empty()) sendToFrontend(); - // (5) Start bank machines to issue new requests + // (5) Start bank machines to issue new requests for current time for (auto it : bankMachines) - { - sc_time delay = it.second->startBankMachine(); - triggerEventAfterDelay(delay); - } + it.second->startBankMachine(); // (6) Choose one request and send it to DRAM std::vector> readyCommands; @@ -243,14 +240,14 @@ void ControllerNew::sendToDram(Command command, tlm_generic_payload *payload) else if (command == Command::RD) { phase = BEGIN_RD; - ScheduledCommand scheduledCommand = state->getLastCommand(command, bank); + ScheduledCommand scheduledCommand = state->getLastCommandOnBank(command, bank); TimeInterval dataStrobe = scheduledCommand.getIntervalOnDataStrobe(); tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, *payload); } else if (command == Command::WR) { phase = BEGIN_WR; - ScheduledCommand scheduledCommand = state->getLastCommand(command, bank); + ScheduledCommand scheduledCommand = state->getLastCommandOnBank(command, bank); TimeInterval dataStrobe = scheduledCommand.getIntervalOnDataStrobe(); tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, *payload); } diff --git a/DRAMSys/library/src/controller/ControllerState.cpp b/DRAMSys/library/src/controller/ControllerState.cpp index fc56c269..494d5ab3 100644 --- a/DRAMSys/library/src/controller/ControllerState.cpp +++ b/DRAMSys/library/src/controller/ControllerState.cpp @@ -41,7 +41,7 @@ using namespace std; -const ScheduledCommand ControllerState::getLastCommand(Command command, +const ScheduledCommand ControllerState::getLastCommandOnBank(Command command, Bank bank) //TODO const reference? and make const { return lastScheduledByCommandAndBank[command][bank]; @@ -52,7 +52,7 @@ const ScheduledCommand ControllerState::getLastCommand(Command command) ScheduledCommand max; for (unsigned int i = 0; i < config->memSpec->NumberOfBanks; ++i) { - ScheduledCommand current = getLastCommand(command, Bank(i)); + ScheduledCommand current = getLastCommandOnBank(command, Bank(i)); if (current.getStart() > max.getStart()) max = current; } diff --git a/DRAMSys/library/src/controller/ControllerState.h b/DRAMSys/library/src/controller/ControllerState.h index 19cde85b..58bdcd8c 100644 --- a/DRAMSys/library/src/controller/ControllerState.h +++ b/DRAMSys/library/src/controller/ControllerState.h @@ -48,15 +48,19 @@ class ControllerState { public: - ControllerState(std::string ownerName, - Configuration *config) : bus(config->memSpec->clk), ownerName(ownerName), + ControllerState(std::string ownerName, Configuration *config) + : bus(config->memSpec->clk), ownerName(ownerName), config(config) { rowBufferStates = new RowBufferState(ownerName); } - virtual ~ControllerState() {} - const ScheduledCommand getLastCommand(Command command, Bank bank); + virtual ~ControllerState() + { + delete rowBufferStates; + } + + const ScheduledCommand getLastCommandOnBank(Command command, Bank bank); const ScheduledCommand getLastCommand(Command command); const ScheduledCommand getLastScheduledCommand(Bank bank); const ScheduledCommand getLastScheduledCommand(); @@ -70,9 +74,9 @@ public: std::map > lastScheduledByCommandAndBank; // TODO: remove - std::map lastScheduledByCommand; - std::map lastScheduledByBank; - ScheduledCommand lastScheduled; + //std::map lastScheduledByCommand; + //std::map lastScheduledByBank; + //ScheduledCommand lastScheduled; Slots bus; std::vector lastDataStrobeCommands; diff --git a/DRAMSys/library/src/controller/RecordableController.cpp b/DRAMSys/library/src/controller/RecordableController.cpp index 9fd2d70d..4b762fa2 100644 --- a/DRAMSys/library/src/controller/RecordableController.cpp +++ b/DRAMSys/library/src/controller/RecordableController.cpp @@ -84,7 +84,7 @@ void RecordableController::schedule(Command command, gp &payload) { Controller::schedule(command, payload); if (commandIsIn(command, {Command::RD, Command::RDA, Command::WR, Command::WRA})) { - ScheduledCommand scheduledCommand = controllerCore->state->getLastCommand( + ScheduledCommand scheduledCommand = controllerCore->state->getLastCommandOnBank( command, DramExtension::getBank(payload)); TimeInterval dataStrobe = scheduledCommand.getIntervalOnDataStrobe(); tlmRecorder->updateDataStrobe(dataStrobe.start, dataStrobe.end, payload); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp index 31c33d15..6f6bb260 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActBChecker.cpp @@ -88,12 +88,12 @@ void ActBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const void ActBChecker::delay_to_satisfy_activateToActivate_sameBank( ScheduledCommand &cmd) const { - ScheduledCommand lastActOnBank = state.getLastCommand(Command::ACT, + ScheduledCommand lastActOnBank = state.getLastCommandOnBank(Command::ACT, cmd.getBank()); if (lastActOnBank.isValidCommand()) { cmd.establishMinDistanceFromStart(lastActOnBank.getStart(), config.memSpec->tRC); } - ScheduledCommand lastActBOnBank = state.getLastCommand(Command::ACTB, + ScheduledCommand lastActBOnBank = state.getLastCommandOnBank(Command::ACTB, cmd.getBank()); if (lastActBOnBank.isValidCommand()) { cmd.establishMinDistanceFromStart(lastActBOnBank.getStart(), diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp index db6e0b86..6b64d156 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ActivateChecker.cpp @@ -92,14 +92,14 @@ void ActivateChecker::delayToSatisfyConstraints(ScheduledCommand &command) const void ActivateChecker::delay_to_satisfy_activateToActivate_sameBank( ScheduledCommand &command) const { - ScheduledCommand lastActivateOnBank = state.getLastCommand(Command::ACT, + ScheduledCommand lastActivateOnBank = state.getLastCommandOnBank(Command::ACT, command.getBank()); if (lastActivateOnBank.isValidCommand()) { command.establishMinDistanceFromStart(lastActivateOnBank.getStart(), config.memSpec->tRC); } - ScheduledCommand lastActBOnBank = state.getLastCommand(Command::ACTB, + ScheduledCommand lastActBOnBank = state.getLastCommandOnBank(Command::ACTB, command.getBank()); if (lastActBOnBank.isValidCommand()) { command.establishMinDistanceFromStart(lastActivateOnBank.getStart(), diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp index 068a57a9..58cc1437 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3.cpp @@ -14,14 +14,14 @@ using namespace std; void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const { ScheduledCommand lastCommandOnBank = state.getLastScheduledCommand(command.getBank()); - Command LastCmd = lastCommandOnBank.getCommand(); - Command NextCmd = command.getCommand(); + Command lastCmd = lastCommandOnBank.getCommand(); + Command nextCmd = command.getCommand(); - if (NextCmd == Command::ACT) + if (nextCmd == Command::ACT) { if (lastCommandOnBank.isValidCommand()) { - switch (LastCmd) + switch (lastCmd) { case Command::PRE: case Command::PREA: @@ -52,7 +52,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; default: reportFatal("Checker DDR3", - "Activate can not follow " + commandToString(LastCmd)); + "Activate can not follow " + commandToString(lastCmd)); } } @@ -64,12 +64,12 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const command.delayStart(memSpec->clk); } } - else if (NextCmd == Command::RD || NextCmd == Command::RDA) + else if (nextCmd == Command::RD || nextCmd == Command::RDA) { delayToSatisfyDLL(command); if (lastCommandOnBank.isValidCommand()) { - switch (LastCmd) + switch (lastCmd) { case Command::ACT: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), @@ -90,17 +90,17 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; default: reportFatal("Checker DDR3", - "Read can not follow " + commandToString(LastCmd) + "First: Activate!"); + "Read can not follow " + commandToString(lastCmd) + "First: Activate!"); } } while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe_RD(command)) command.delayStart(memSpec->clk); } - else if (NextCmd == Command::WR || NextCmd == Command::WRA) + else if (nextCmd == Command::WR || nextCmd == Command::WRA) { if (lastCommandOnBank.isValidCommand()) { - switch (LastCmd) + switch (lastCmd) { case Command::ACT: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), @@ -120,17 +120,17 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const memSpec->tXP); break; default: - reportFatal("Checker DDR3", "Write can not follow " + commandToString(LastCmd)); + reportFatal("Checker DDR3", "Write can not follow " + commandToString(lastCmd)); } } while (!state.bus.isFree(command.getStart()) || collidesOnDataStrobe_WR(command)) command.delayStart(memSpec->clk); } - else if (NextCmd == Command::PRE) + else if (nextCmd == Command::PRE) { if (lastCommandOnBank.isValidCommand()) { - switch (LastCmd) + switch (lastCmd) { case Command::PRE: command.establishMinDistanceFromStart(lastCommandOnBank.getStart(), @@ -155,16 +155,16 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; default: reportFatal("Checker DDR3", - "Precharge can not follow " + commandToString(LastCmd)); + "Precharge can not follow " + commandToString(lastCmd)); } } - ScheduledCommand lastActivate = state.getLastCommand(Command::ACT, command.getBank()); + ScheduledCommand lastActivate = state.getLastCommandOnBank(Command::ACT, command.getBank()); if (lastActivate.isValidCommand()) command.establishMinDistanceFromStart(lastActivate.getStart(), memSpec->tRAS); state.bus.moveCommandToNextFreeSlot(command); } - else if (NextCmd == Command::PREA) + else if (nextCmd == Command::PREA) { for (unsigned int bank = 0; bank < memSpec->NumberOfBanks; bank++) { @@ -214,21 +214,21 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; default: reportFatal("Checker_DDR3", - "Precharge All can not follow " + commandToString(LastCmd)); + "Precharge All can not follow " + commandToString(lastCmd)); } } } - ScheduledCommand lastActivate = state.getLastCommand(Command::ACT, command.getBank()); + ScheduledCommand lastActivate = state.getLastCommandOnBank(Command::ACT, command.getBank()); if (lastActivate.isValidCommand()) command.establishMinDistanceFromStart(lastActivate.getStart(), memSpec->tRAS); state.bus.moveCommandToNextFreeSlot(command); } - else if (NextCmd == Command::PDEA || NextCmd == Command::PDEP || NextCmd == Command::SREFEN ) + else if (nextCmd == Command::PDEA || nextCmd == Command::PDEP || nextCmd == Command::SREFEN ) { if (lastCommandOnBank.isValidCommand()) { - switch (LastCmd) + switch (lastCmd) { case Command::PRE: case Command::PREA: @@ -265,39 +265,39 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const memSpec->tXS); break; default: - reportFatal("Checker DDR3", commandToString(NextCmd) + " can not follow " - + commandToString(LastCmd) + ".First: Precharge!"); + reportFatal("Checker DDR3", commandToString(nextCmd) + " can not follow " + + commandToString(lastCmd) + ".First: Precharge!"); } } state.bus.moveCommandToNextFreeSlot(command); } - else if (NextCmd == Command::PDXA) + else if (nextCmd == Command::PDXA) { // Leaving Precharge Power Down - command.establishMinDistanceFromStart(state.getLastCommand(Command::PDEA, + command.establishMinDistanceFromStart(state.getLastCommandOnBank(Command::PDEA, command.getBank()).getStart(), memSpec->tCKE); state.bus.moveCommandToNextFreeSlot(command); } - else if (NextCmd == Command::PDXP) + else if (nextCmd == Command::PDXP) { // Leaving Precharge Power Down - command.establishMinDistanceFromStart(state.getLastCommand(Command::PDEP, + command.establishMinDistanceFromStart(state.getLastCommandOnBank(Command::PDEP, command.getBank()).getStart(), memSpec->tCKE); state.bus.moveCommandToNextFreeSlot(command); } - else if (NextCmd == Command::SREFEX) + else if (nextCmd == Command::SREFEX) { // Leaving Self Refresh - command.establishMinDistanceFromStart(state.getLastCommand(Command::SREFEN, + command.establishMinDistanceFromStart(state.getLastCommandOnBank(Command::SREFEN, command.getBank()).getStart(), memSpec->tCKESR); state.bus.moveCommandToNextFreeSlot(command); } - else if (NextCmd == Command::REFA) + else if (nextCmd == Command::REFA) { if (config.BankwiseLogic) { if (lastCommandOnBank.isValidCommand()) { - switch (LastCmd) + switch (lastCmd) { case Command::PRE: case Command::PREA: @@ -328,7 +328,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; default: reportFatal("Checker DDR3", - "Refresh can not follow " + commandToString(LastCmd)); + "Refresh can not follow " + commandToString(lastCmd)); } } } @@ -375,7 +375,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const break; default: reportFatal("Checker DDR3", - "Refresh can not follow " + commandToString(LastCmd)); + "Refresh can not follow " + commandToString(lastCmd)); } } } @@ -390,7 +390,7 @@ void CheckerDDR3::delayToSatisfyConstraints(ScheduledCommand &command) const void CheckerDDR3::delay_to_satisfy_activateToActivate_sameBank(ScheduledCommand &command) const { - ScheduledCommand lastActivateOnBank = state.getLastCommand(Command::ACT, command.getBank()); + ScheduledCommand lastActivateOnBank = state.getLastCommandOnBank(Command::ACT, command.getBank()); if (lastActivateOnBank.isValidCommand()) command.establishMinDistanceFromStart(lastActivateOnBank.getStart(), memSpec->tRC); } @@ -477,7 +477,7 @@ bool CheckerDDR3::collidesWithStrobeCommand_RD(ScheduledCommand &read, void CheckerDDR3::delayToSatisfyDLL(ScheduledCommand &read) const { - ScheduledCommand lastSREFX = state.getLastCommand(Command::SREFEX, read.getBank()); + ScheduledCommand lastSREFX = state.getLastCommandOnBank(Command::SREFEX, read.getBank()); if (lastSREFX.isValidCommand()) read.establishMinDistanceFromStart(lastSREFX.getStart(), memSpec->tXSDLL_old); } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp index 696f7b02..42988069 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/CheckerDDR3New.cpp @@ -19,45 +19,45 @@ sc_time CheckerDDR3New::delayToSatisfyConstraints(Command command, Bank bank) if (command == Command::ACT) { - lastCommand = state.getLastCommand(Command::RDA, bank); + lastCommand = state.getLastCommandOnBank(Command::RDA, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRTP + memSpec->tRP); - lastCommand = state.getLastCommand(Command::WRA, bank); + lastCommand = state.getLastCommandOnBank(Command::WRA, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR + memSpec->tRP); - lastCommand = state.getLastCommand(Command::PRE, bank); + lastCommand = state.getLastCommandOnBank(Command::PRE, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRP); - lastCommand = state.getLastCommand(Command::PREA, bank); + lastCommand = state.getLastCommandOnBank(Command::PREA, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRP); - lastCommand = state.getLastCommand(Command::PDXA, bank); + lastCommand = state.getLastCommandOnBank(Command::PDXA, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); - lastCommand = state.getLastCommand(Command::PDXP, bank); + lastCommand = state.getLastCommandOnBank(Command::PDXP, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); - lastCommand = state.getLastCommand(Command::REFA, bank); + lastCommand = state.getLastCommandOnBank(Command::REFA, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRFC); - lastCommand = state.getLastCommand(Command::SREFEX, bank); + lastCommand = state.getLastCommandOnBank(Command::SREFEX, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXS); - lastCommand = state.getLastCommand(Command::ACT, bank); + lastCommand = state.getLastCommandOnBank(Command::ACT, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRC); for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) { - lastCommand = state.getLastCommand(Command::ACT, Bank(bankID)); + lastCommand = state.getLastCommandOnBank(Command::ACT, Bank(bankID)); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRRD); } @@ -67,7 +67,7 @@ sc_time CheckerDDR3New::delayToSatisfyConstraints(Command command, Bank bank) } else if (command == Command::RD || command == Command::RDA) { - lastCommand = state.getLastCommand(Command::ACT, bank); + lastCommand = state.getLastCommandOnBank(Command::ACT, bank); //if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRCD); @@ -79,11 +79,11 @@ sc_time CheckerDDR3New::delayToSatisfyConstraints(Command command, Bank bank) // if (lastCommand.isValidCommand()) // minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); - lastCommand = state.getLastCommand(Command::PDXA, bank); + lastCommand = state.getLastCommandOnBank(Command::PDXA, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); - lastCommand = state.getLastCommand(Command::SREFEX, bank); + lastCommand = state.getLastCommandOnBank(Command::SREFEX, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXSDLL); @@ -92,18 +92,18 @@ sc_time CheckerDDR3New::delayToSatisfyConstraints(Command command, Bank bank) for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) { - lastCommand = state.getLastCommand(Command::RD, Bank(bankID)); + lastCommand = state.getLastCommandOnBank(Command::RD, Bank(bankID)); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tCCD); - lastCommand = state.getLastCommand(Command::WR, Bank(bankID)); + lastCommand = state.getLastCommandOnBank(Command::WR, Bank(bankID)); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWTR); } } else if (command == Command::WR || command == Command::WRA) { - lastCommand = state.getLastCommand(Command::ACT, bank); + lastCommand = state.getLastCommandOnBank(Command::ACT, bank); //if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRCD); @@ -115,11 +115,11 @@ sc_time CheckerDDR3New::delayToSatisfyConstraints(Command command, Bank bank) // if (lastCommand.isValidCommand()) // minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tCCD); - lastCommand = state.getLastCommand(Command::PDXA, bank); + lastCommand = state.getLastCommandOnBank(Command::PDXA, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); - lastCommand = state.getLastCommand(Command::SREFEX, bank); + lastCommand = state.getLastCommandOnBank(Command::SREFEX, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXSDLL); @@ -128,30 +128,30 @@ sc_time CheckerDDR3New::delayToSatisfyConstraints(Command command, Bank bank) for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++) { - lastCommand = state.getLastCommand(Command::RD, Bank(bankID)); + lastCommand = state.getLastCommandOnBank(Command::RD, Bank(bankID)); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRL + memSpec->tCCD + 2 * memSpec->clk - memSpec->tWL); - lastCommand = state.getLastCommand(Command::WR, Bank(bankID)); + lastCommand = state.getLastCommandOnBank(Command::WR, Bank(bankID)); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tCCD); } } else if (command == Command::PRE) { - lastCommand = state.getLastCommand(Command::ACT, bank); + lastCommand = state.getLastCommandOnBank(Command::ACT, bank); //if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRAS); - lastCommand = state.getLastCommand(Command::RD, bank); + lastCommand = state.getLastCommandOnBank(Command::RD, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tRTP); - lastCommand = state.getLastCommand(Command::WR, bank); + lastCommand = state.getLastCommandOnBank(Command::WR, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tWL + memSpec->tCCD + memSpec->tWR); - lastCommand = state.getLastCommand(Command::PDXA, bank); + lastCommand = state.getLastCommandOnBank(Command::PDXA, bank); if (lastCommand.isValidCommand()) minTimeToWait = max(minTimeToWait, lastCommand.getStart() + memSpec->tXP); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp index 48c35d9e..16ace13e 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PowerDownChecker.cpp @@ -81,17 +81,17 @@ const } else if (pdnCmd == Command::PDXA) { // Leaving Active Power Down timeConstraint = config.memSpec->tCKE; - command.establishMinDistanceFromStart(state.getLastCommand(Command::PDEA, + command.establishMinDistanceFromStart(state.getLastCommandOnBank(Command::PDEA, bank).getStart(), timeConstraint); } else if (pdnCmd == Command::PDXP) { // Leaving Precharge Power Down timeConstraint = config.memSpec->tCKE; - command.establishMinDistanceFromStart(state.getLastCommand(Command::PDEP, + command.establishMinDistanceFromStart(state.getLastCommandOnBank(Command::PDEP, bank).getStart(), timeConstraint); } else if (pdnCmd == Command::SREFEX) { // Leaving Self Refresh timeConstraint = config.memSpec->tCKESR; - command.establishMinDistanceFromStart(state.getLastCommand(Command::SREFEN, + command.establishMinDistanceFromStart(state.getLastCommandOnBank(Command::SREFEN, bank).getStart(), timeConstraint); } diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp index 907dcb73..5a0f7229 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PreBChecker.cpp @@ -71,11 +71,11 @@ void PreBChecker::delayToSatisfyConstraints(ScheduledCommand &cmd) const cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec->tRP_old); } // ------------ - if ((lc = state.getLastCommand(Command::ACT, + if ((lc = state.getLastCommandOnBank(Command::ACT, cmd.getBank())).isValidCommand()) { cmd.establishMinDistanceFromStart(lc.getStart(), config.memSpec->tRAS); } - if ((lc = state.getLastCommand(Command::ACTB, + if ((lc = state.getLastCommandOnBank(Command::ACTB, cmd.getBank())).isValidCommand()) { cmd.establishMinDistanceFromStart(lc.getStart(), Configuration::getInstance().getTrasb()); diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp index aede0f2d..45380a72 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeAllChecker.cpp @@ -90,7 +90,7 @@ const } } - ScheduledCommand lastActivate = state.getLastCommand(Command::ACT, + ScheduledCommand lastActivate = state.getLastCommandOnBank(Command::ACT, command.getBank()); // TODO: Why do we only check the ACT of one bank? (always bank 0) if (lastActivate.isValidCommand()) { diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp index 50c67c43..3666f5f3 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/PrechargeChecker.cpp @@ -75,7 +75,7 @@ const "PRE can not follow " + commandToString(lastCommand.getCommand())); } - ScheduledCommand lastActivate = state.getLastCommand(Command::ACT, + ScheduledCommand lastActivate = state.getLastCommandOnBank(Command::ACT, command.getBank()); if (lastActivate.isValidCommand()) { command.establishMinDistanceFromStart(lastActivate.getStart(), diff --git a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp index 1683a30b..769624cc 100644 --- a/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp +++ b/DRAMSys/library/src/controller/core/scheduling/checker/ReadChecker.cpp @@ -108,7 +108,7 @@ bool ReadChecker::collidesWithStrobeCommand(ScheduledCommand &read, void ReadChecker::delayToSatisfyDLL(ScheduledCommand &read) const { - ScheduledCommand lastSREFX = state.getLastCommand(Command::SREFEX, + ScheduledCommand lastSREFX = state.getLastCommandOnBank(Command::SREFEX, read.getBank()); if (lastSREFX.isValidCommand()) read.establishMinDistanceFromStart(lastSREFX.getStart(),