diff --git a/DRAMSys/library/src/common/DebugManager.cpp b/DRAMSys/library/src/common/DebugManager.cpp
index 51e2380e..e58ec8f5 100644
--- a/DRAMSys/library/src/common/DebugManager.cpp
+++ b/DRAMSys/library/src/common/DebugManager.cpp
@@ -65,7 +65,7 @@ void DebugManager::openDebugFile(string filename)
 }
 
 DebugManager::DebugManager() :
-    writeToConsole(true), writeToFile(true)
+    writeToConsole(false), writeToFile(false)
 {
 }
 
diff --git a/DRAMSys/library/src/controller/BankMachine.cpp b/DRAMSys/library/src/controller/BankMachine.cpp
index 2a2e09e0..65f51c20 100644
--- a/DRAMSys/library/src/controller/BankMachine.cpp
+++ b/DRAMSys/library/src/controller/BankMachine.cpp
@@ -27,7 +27,7 @@ sc_time BankMachine::startBankMachine()
 {
     if (currentPayload == nullptr)
     {
-        currentPayload = scheduler->getNextRequest(bank, currentState, currentRow);
+        currentPayload = scheduler->getNextRequest(bank, this);
         if (currentPayload == nullptr)
             return SC_ZERO_TIME;
     }
@@ -90,3 +90,13 @@ void BankMachine::updateState(Command command)
     else
         SC_REPORT_FATAL("BankMachine", "Unknown phase");
 }
+
+Row BankMachine::getOpenRow()
+{
+    return currentRow;
+}
+
+BmState BankMachine::getState()
+{
+    return currentState;
+}
diff --git a/DRAMSys/library/src/controller/BankMachine.h b/DRAMSys/library/src/controller/BankMachine.h
index 535b1296..383a7e4c 100644
--- a/DRAMSys/library/src/controller/BankMachine.h
+++ b/DRAMSys/library/src/controller/BankMachine.h
@@ -33,6 +33,10 @@ public:
     sc_time startBankMachine();
     std::pair<Command, tlm_generic_payload *> getNextCommand();
     void updateState(Command);
+
+    Row getOpenRow();
+    BmState getState();
+
 private:
     tlm_generic_payload *currentPayload = nullptr;
     BmState currentState = BmState::Precharged;
diff --git a/DRAMSys/library/src/controller/ControllerNew.cpp b/DRAMSys/library/src/controller/ControllerNew.cpp
index 9ec6afb7..49c9adaf 100644
--- a/DRAMSys/library/src/controller/ControllerNew.cpp
+++ b/DRAMSys/library/src/controller/ControllerNew.cpp
@@ -21,13 +21,13 @@ ControllerNew::ControllerNew(sc_module_name name, TlmRecorder *tlmRecorder) :
 
     state = new ControllerState("Controller", &Configuration::getInstance());
     checker = new CheckerDDR3New(Configuration::getInstance(), *state);
-    scheduler = new SchedulerFifo();
+    scheduler = new SchedulerFrFcfs();
     for (unsigned bankID = 0; bankID < Configuration::getInstance().memSpec->NumberOfBanks; bankID++)
     {
         bankMachines[Bank(bankID)] = new BankMachine(scheduler, checker, Bank(bankID));
         commandFinishedTime[Bank(bankID)] = SC_ZERO_TIME;
     }
-    commandMux = new CmdMuxStrict();
+    commandMux = new CmdMuxOldest();
 }
 
 ControllerNew::~ControllerNew()
@@ -134,11 +134,13 @@ void ControllerNew::controllerMethod()
             releasePayload();
 
         // (2) Accept new request from arbiter
-        if (sc_time_stamp() >= timeToAcquire && payloadToAcquire != nullptr
-                && numberOfPayloads < Configuration::getInstance().MaxNrOfTransactions)
-            acquirePayload();
-        else
-            printDebugMessage("Total number of payloads exceeded, backpressure!");
+        if (sc_time_stamp() >= timeToAcquire && payloadToAcquire != nullptr)
+        {
+            if (numberOfPayloads < Configuration::getInstance().MaxNrOfTransactions)
+                acquirePayload();
+            else
+                printDebugMessage("Total number of payloads exceeded, backpressure!");
+        }
 
         // (3) Update states of bank machines and get results if ready
         for (auto it : bankMachines)
diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp
index 1e459590..00055677 100644
--- a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp
+++ b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.cpp
@@ -6,7 +6,7 @@ void SchedulerFifo::storeRequest(tlm_generic_payload *payload)
     buffer[bank].push(payload);
 }
 
-tlm_generic_payload *SchedulerFifo::getNextRequest(Bank bank, BmState, Row)
+tlm_generic_payload *SchedulerFifo::getNextRequest(Bank bank, BankMachine *)
 {
     if (!buffer[bank].empty())
     {
diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h
index 372f9eaf..24d25b09 100644
--- a/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h
+++ b/DRAMSys/library/src/controller/scheduler/SchedulerFifo.h
@@ -14,7 +14,7 @@ class SchedulerFifo : public SchedulerIF
 {
 public:
     void storeRequest(tlm_generic_payload *);
-    tlm_generic_payload *getNextRequest(Bank, BmState, Row);
+    tlm_generic_payload *getNextRequest(Bank, BankMachine *);
 private:
     std::map<Bank, std::queue<tlm_generic_payload *>> buffer;
 };
diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp
index 5f3cd411..128a5893 100644
--- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp
+++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp
@@ -7,19 +7,21 @@ void SchedulerFrFcfs::storeRequest(tlm_generic_payload *payload)
     buffer[bank].push_back(payload);
 }
 
-tlm_generic_payload *SchedulerFrFcfs::getNextRequest(Bank bank, BmState state, Row openRow)
+tlm_generic_payload *SchedulerFrFcfs::getNextRequest(Bank bank, BankMachine *bankMachine)
 {
     if (!buffer[bank].empty())
     {
-        if (state == BmState::Precharged)
+        BmState currentState = bankMachine->getState();
+        if (currentState == BmState::Precharged)
         {
             tlm_generic_payload *result = buffer[bank].front();
             buffer[bank].erase(buffer[bank].begin());
             return result;
         }
-        else if (state == BmState::Activated)
+        else if (currentState == BmState::Activated)
         {
             // Search for row hit
+            Row openRow = bankMachine->getOpenRow();
             for (auto it = buffer[bank].begin(); it != buffer[bank].end(); it++)
             {
                 if (DramExtension::getRow(*it) == openRow)
diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h
index 27db26cb..23869455 100644
--- a/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h
+++ b/DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h
@@ -14,7 +14,7 @@ class SchedulerFrFcfs : public SchedulerIF
 {
 public:
     void storeRequest(tlm_generic_payload *);
-    tlm_generic_payload *getNextRequest(Bank, BmState, Row);
+    tlm_generic_payload *getNextRequest(Bank, BankMachine *);
 private:
     std::map<Bank, std::vector<tlm_generic_payload *>> buffer;
 };
diff --git a/DRAMSys/library/src/controller/scheduler/SchedulerIF.h b/DRAMSys/library/src/controller/scheduler/SchedulerIF.h
index 7170591c..a4025f6d 100644
--- a/DRAMSys/library/src/controller/scheduler/SchedulerIF.h
+++ b/DRAMSys/library/src/controller/scheduler/SchedulerIF.h
@@ -9,13 +9,14 @@
 using namespace tlm;
 
 enum class BmState;
+class BankMachine;
 
 class SchedulerIF
 {
 public:
     virtual ~SchedulerIF() {}
     virtual void storeRequest(tlm_generic_payload *) = 0;
-    virtual tlm_generic_payload *getNextRequest(Bank, BmState, Row) = 0;
+    virtual tlm_generic_payload *getNextRequest(Bank, BankMachine *) = 0;
 protected:
     void printDebugMessage(std::string message)
     {