From dca7d88a68608ab36940700da034ab03b5c6dec3 Mon Sep 17 00:00:00 2001 From: "Thanh C. Tran" Date: Mon, 12 Jun 2017 12:34:53 +0200 Subject: [PATCH] Clean up unused classes & Add notes about SMS scheduler --- DRAMSys/simulator/library.pro | 2 - .../simulator/src/controller/scheduler/MPKC.h | 55 ----------------- .../src/controller/scheduler/ReadyBatch.cpp | 59 ------------------- .../src/controller/scheduler/ReadyBatch.h | 30 ---------- .../simulator/src/controller/scheduler/SMS.h | 10 +++- 5 files changed, 9 insertions(+), 147 deletions(-) delete mode 100644 DRAMSys/simulator/src/controller/scheduler/MPKC.h delete mode 100644 DRAMSys/simulator/src/controller/scheduler/ReadyBatch.cpp delete mode 100644 DRAMSys/simulator/src/controller/scheduler/ReadyBatch.h diff --git a/DRAMSys/simulator/library.pro b/DRAMSys/simulator/library.pro index 3770561e..4cac1673 100644 --- a/DRAMSys/simulator/library.pro +++ b/DRAMSys/simulator/library.pro @@ -82,7 +82,6 @@ SOURCES += \ src/controller/scheduler/Fr_Fcfs.cpp \ src/controller/scheduler/Fifo.cpp \ src/controller/scheduler/SMS.cpp \ - src/controller/scheduler/ReadyBatch.cpp \ src/controller/core/refresh/RefreshManagerBankwise.cpp \ src/controller/core/refresh/RefreshManager.cpp \ src/controller/core/scheduling/checker/WriteChecker.cpp \ @@ -133,7 +132,6 @@ HEADERS += \ src/controller/scheduler/Fr_Fcfs.h \ src/controller/scheduler/Fifo.h \ src/controller/scheduler/SMS.h \ - src/controller/scheduler/ReadyBatch.h \ src/controller/Controller.h \ src/controller/core/refresh/RefreshManagerBankwise.h \ src/controller/core/refresh/RefreshManager.h \ diff --git a/DRAMSys/simulator/src/controller/scheduler/MPKC.h b/DRAMSys/simulator/src/controller/scheduler/MPKC.h deleted file mode 100644 index 8b7add90..00000000 --- a/DRAMSys/simulator/src/controller/scheduler/MPKC.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * MPKC.h - * - * Created on: May 11, 2017 - * Author: thanhtran - */ - -#ifndef MPKC_H_ -#define MPKC_H_ - -#include "../../../common/Utils.h" - -using namespace std; - -class MPKC: public sc_module -{ - public: - MPKC(sc_module_name /*_name*/, sc_time memClk) : memClk(memClk) - { - lastGeneratedRequests = std::make_pair(0, 0); - SC_THREAD(updateMPKC); - } - SC_HAS_PROCESS(MPKC); - - void updateMPKC() - { - - while(true) - { - mpkc = 1 / (lastGeneratedRequests.second + numClk*memClk -lastGeneratedRequests.first); - wait(memClk); - numClk++; - } - } - - float getMPKC() - { - return mpkc; - } - - void sendNewRequest(sc_time timeOfGeneration) - { - std::swap(lastGeneratedRequests.first, lastGeneratedRequests.second); - lastGeneratedRequests.second = timeOfGeneration; - numClk = 0; - } - - private: - unsigned int numClk = 0; - sc_time memClk; - float mpkc = 0; - std::pair lastGeneratedRequests; -}; - -#endif /* MPKC_H_ */ diff --git a/DRAMSys/simulator/src/controller/scheduler/ReadyBatch.cpp b/DRAMSys/simulator/src/controller/scheduler/ReadyBatch.cpp deleted file mode 100644 index 55118d15..00000000 --- a/DRAMSys/simulator/src/controller/scheduler/ReadyBatch.cpp +++ /dev/null @@ -1,59 +0,0 @@ -#include "ReadyBatch.h" - -ReadyBatch::ReadyBatch() -{ - fifosize = Configuration::getInstance().ReadyBatchSize; - thresholdAge = sc_time(Configuration::getInstance().ReadyBatchThresholdAge, SC_NS); -} - -ReadyBatch::~ReadyBatch() -{ - -} - -//unsigned int ReadyBatch::getNumRequests() -//{ -// return readybatch.size(); -//} - -Row ReadyBatch::getRow() -{ - return DramExtension::getExtension(readybatch.front()).getRow(); -} - -//sc_time ReadyBatch::getTimeOfOldestRequest() -//{ -// sc_time oldestTime = sc_time_stamp(); -// for (auto reqPayload = readybatch.begin(); reqPayload != readybatch.end(); reqPayload++) -// { -// sc_time requestTimeOfGeneration = GenerationExtension::getExtension(*reqPayload).TimeOfGeneration(); -// if (requestTimeOfGeneration < oldestTime) -// { -// oldestTime = requestTimeOfGeneration; -// } -// } -// return oldestTime; -//} - -bool ReadyBatch::addTransaction(gp* payload) -{ -// sc_time currentAge = sc_time_stamp() - getTimeOfOldestRequest(); - Row newRow = DramExtension::getExtension(payload).getRow(); - Row oldRow = readybatch.empty()? newRow : getRow(); - if (/*getNumRequests() == fifosize || currentAge >= thresholdAge || */newRow != oldRow) { - return false; - } else { - readybatch.emplace_back(payload); - return true; - } -} - -std::deque& ReadyBatch::getTransactions() -{ - return readybatch; -} - -bool ReadyBatch::isEmpty() -{ - return readybatch.empty(); -} diff --git a/DRAMSys/simulator/src/controller/scheduler/ReadyBatch.h b/DRAMSys/simulator/src/controller/scheduler/ReadyBatch.h deleted file mode 100644 index 1b0f304c..00000000 --- a/DRAMSys/simulator/src/controller/scheduler/ReadyBatch.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef READYBATCH_H -#define READYBATCH_H - -#include "tlm.h" -#include "../../common/dramExtension.h" -#include "../core/configuration/Configuration.h" - -typedef tlm::tlm_generic_payload gp; - -using namespace std; - -class ReadyBatch -{ -public: - ReadyBatch(); - bool addTransaction(gp* payload); -// unsigned int getNumRequests(); - std::deque& getTransactions(); - bool isEmpty(); - ~ReadyBatch(); -private: - std::deque readybatch; - unsigned int fifosize; - sc_time thresholdAge; - - Row getRow(); -// sc_time getTimeOfOldestRequest(); -}; - -#endif // READYBATCH_H diff --git a/DRAMSys/simulator/src/controller/scheduler/SMS.h b/DRAMSys/simulator/src/controller/scheduler/SMS.h index df9c132f..73675a41 100644 --- a/DRAMSys/simulator/src/controller/scheduler/SMS.h +++ b/DRAMSys/simulator/src/controller/scheduler/SMS.h @@ -5,7 +5,6 @@ #include #include "sysc/utils/sc_report.h" #include "IScheduler.h" -#include "ReadyBatch.h" #include "../core/ControllerCore.h" #include "../core/configuration/Configuration.h" #include "../../common/dramExtension.h" @@ -22,6 +21,15 @@ using namespace std; typedef std::deque::iterator gp_deque_iterator; +/** + * SMS - Staged Memory Scheduler involves 3 steps: + * 1. Arrage request in to each buffer of each thread + * 2. Forming ready batches for each thread, i.e all requests access the same row. The batch is deemed + * ready when the next request accesses different row OR When the buffer is full OR When this batch + * is too old + * 3. Send batches to bank buffers. The rules to send batches are Shortest-Job-First OR Round-Robin + * How we select the rule depends on the probability we setup earlier. + */ class SMS: public sc_module, public IScheduler { public: