From dacaec7f11dd080c86807c5d4c7ec45f89de2982 Mon Sep 17 00:00:00 2001 From: Janik Schlemminger Date: Fri, 14 Mar 2014 16:35:44 -0700 Subject: [PATCH] connecting components in controller commandbus changing state when scheduling commands added some tests --- DRAM/main.cpp | 17 ++--- DRAM/src/core/Controller.cpp | 44 +++++++++-- DRAM/src/core/Controller.h | 14 ++-- DRAM/src/core/scheduling/CommandBus.cpp | 60 ++++++++++++--- DRAM/src/core/scheduling/CommandBus.h | 13 +++- DRAM/src/core/scheduling/CommandSchedule.h | 9 +-- .../scheduling/CommandSequenceScheduler.cpp | 24 +++--- .../scheduling/CommandSequenceScheduler.h | 12 ++- DRAM/src/core/scheduling/ScheduledCommand.h | 5 ++ .../scheduling/checker/ActivateChecker.cpp | 7 ++ .../core/scheduling/checker/ActivateChecker.h | 5 +- .../core/scheduling/checker/ICommandChecker.h | 3 +- .../scheduling/checker/PrechargeChecker.cpp | 10 ++- .../scheduling/checker/PrechargeChecker.h | 1 + .../core/scheduling/checker/ReadChecker.cpp | 7 ++ .../src/core/scheduling/checker/ReadChecker.h | 1 + .../core/scheduling/checker/WriteChecker.cpp | 7 ++ .../core/scheduling/checker/WriteChecker.h | 1 + DRAM/src/core/utils/RingBuffer.h | 20 +++-- DRAM/src/core/utils/Utils.cpp | 8 +- DRAM/src/core/utils/Utils.h | 2 +- DRAM/testing/CommandBus_test.cpp | 4 +- DRAM/testing/Utils_test.cpp | 76 +++++++++++++++++++ .../{ => checker}/ActivateChecker_test.cpp | 0 .../{ => checker}/PrechargeChecker_test.cpp | 0 .../{ => checker}/ReadChecker_test.cpp | 0 .../{ => checker}/WriteChecker_test.cpp | 0 27 files changed, 272 insertions(+), 78 deletions(-) create mode 100644 DRAM/testing/Utils_test.cpp rename DRAM/testing/{ => checker}/ActivateChecker_test.cpp (100%) rename DRAM/testing/{ => checker}/PrechargeChecker_test.cpp (100%) rename DRAM/testing/{ => checker}/ReadChecker_test.cpp (100%) rename DRAM/testing/{ => checker}/WriteChecker_test.cpp (100%) diff --git a/DRAM/main.cpp b/DRAM/main.cpp index 235e9fd1..b4db982c 100644 --- a/DRAM/main.cpp +++ b/DRAM/main.cpp @@ -24,17 +24,10 @@ int runTests(int argc, char **argv) return RUN_ALL_TESTS(); } - -/*int sc_main(int argc, char **argv) { - - return runTests(argc,argv); -}*/ - - int main(int argc, char **argv) { - /*sc_time clk(6, SC_NS); - sc_time time(18, SC_NS); - assert(!((time/clk)-ceil(time/clk))); - std::cout<<"good"<<(time/clk)-ceil(time/clk)<::iterator it = commandChecker.begin(); + while (it != commandChecker.end()) + { + delete it->second; + } + commandChecker.clear(); +} -bool Controller::schedule(sc_time currentTime, - tlm::tlm_generic_payload* externalTransaction) +bool Controller::schedule(sc_time currentTime, tlm::tlm_generic_payload* externalTransaction) { + assert(currentTime == SC_ZERO_TIME); bus.cleanUpBus(currentTime); + + + return true; +} + +const ICommandChecker& Controller::getChecker(Command command) const +{ + std::map::const_iterator result = commandChecker.find(command); + assert(result != commandChecker.end()); + return *(result->second); } } /* namespace controller */ diff --git a/DRAM/src/core/Controller.h b/DRAM/src/core/Controller.h index 930a7dfa..fa2e3ffc 100644 --- a/DRAM/src/core/Controller.h +++ b/DRAM/src/core/Controller.h @@ -12,11 +12,11 @@ #include "scheduling/CommandSequenceGenerator.h" #include "scheduling/CommandBus.h" #include "Configuration.h" -#include "scheduling/CommandSequenceScheduler.h" #include "refresh/RefreshManager.h" #include "powerdown/PowerDownManager.h" #include #include "scheduling/checker/ICommandChecker.h" +#include "scheduling/CommandSequenceScheduler.h" namespace controller { @@ -26,18 +26,22 @@ public: Controller(); virtual ~Controller(); - bool schedule( sc_time currentTime, tlm::tlm_generic_payload* externalTransaction); //return TLM status?? + bool schedule(sc_time currentTime, tlm::tlm_generic_payload* externalTransaction); //TODO return TLM status?? + const ICommandChecker& getChecker(Command command) const; private: Configuration config; ControllerState state; - CommandSequenceGenerator commandGenerator; - std::map commandScheduler; + CommandSequenceGenerator commandSequenceGenerator; + std::map commandChecker; + std::vector allCommandChecker; CommandSequenceScheduler commandSequenceScheduler; RefreshManager refreshManager; - PowerDownManager powerDownManager; + //PowerDownManager powerDownManager; CommandBus bus; + + void addCommandChecker(Command command, ICommandChecker* checker); }; } /* namespace controller */ diff --git a/DRAM/src/core/scheduling/CommandBus.cpp b/DRAM/src/core/scheduling/CommandBus.cpp index 0cbdb401..6b1c4a13 100644 --- a/DRAM/src/core/scheduling/CommandBus.cpp +++ b/DRAM/src/core/scheduling/CommandBus.cpp @@ -10,23 +10,21 @@ namespace controller { + void CommandBus::scheduleCommand(const ScheduledCommand& command) { - if (command.getCommand() == Command::Refresh) - { - scheduleRefresh(command); - lastCommandsOnBus.at(Command::Activate).at(command.getBank()) = command.getStart(); - } - assert(!pendingBusCommands.count(command.getStart())); + + changeControllerState(command); pendingBusCommands.insert(command.getStart()); lastCommandsOnBus[command.getCommand()][command.getBank()] = command.getStart(); + //notify tlm wrapper } void CommandBus::scheduleTrigger(const Trigger command, sc_time time) { - + //notify tlm wrapper } sc_time CommandBus::getLastCommand(Command command, common::Bank bank) @@ -71,9 +69,53 @@ void CommandBus::cleanUpBus(sc_time currentTime) pendingBusCommands.lower_bound(currentTime)); } -void CommandBus::scheduleRefresh(const ScheduledCommand& command) +void CommandBus::changeControllerState(const ScheduledCommand& command) { - state.bankStates.closeAllRowBuffers(); + switch (command.getCommand()) + { + case Command::Refresh: + refresh(command); + break; + case Command::Activate: + activate(command); + break; + case Command::Precharge: + precharge(command); + default: + break; + } +} + +void CommandBus::refresh(const ScheduledCommand& command) +{ + if(config.RefreshBankwise) + { + state.bankStates.closeRowBuffer(command.getBank()); + } + else + { + state.bankStates.closeAllRowBuffers(); + } +} + +void CommandBus::precharge(const ScheduledCommand& command) +{ + if(command.getCommand() == Command::Precharge) + { + state.bankStates.closeRowBuffer(command.getBank()); + } + else if(command.getCommand() == Command::PrechargeAll) + { + state.bankStates.closeAllRowBuffers(); + } +} + +void CommandBus::activate(const ScheduledCommand& command) +{ + if(command.getCommand() == Command::Activate) + { + state.bankStates.openRowInRowBuffer(command.getBank(), command.getRow()); + } } } /* namespace controller */ diff --git a/DRAM/src/core/scheduling/CommandBus.h b/DRAM/src/core/scheduling/CommandBus.h index 3375c180..f2cebb38 100644 --- a/DRAM/src/core/scheduling/CommandBus.h +++ b/DRAM/src/core/scheduling/CommandBus.h @@ -13,6 +13,7 @@ #include "core/scheduling/Trigger.h" #include "IInternalScheduler.h" #include "core/Configuration.h" +#include "core/scheduling/checker/ICommandChecker.h" #include #include @@ -21,7 +22,7 @@ namespace controller{ class CommandBus : public IInternalScheduler { public: - CommandBus(const Configuration& config, controller::ControllerState& state) : state(state), config(config) {} + CommandBus(const Configuration& config, controller::ControllerState& state,std::vector& checker) : config(config), state(state), checker(checker) {} virtual void scheduleCommand(const ScheduledCommand& command); virtual void scheduleTrigger(const Trigger trigger, sc_time time); @@ -35,13 +36,17 @@ public: const std::set& getPendingBusCommands() const {return pendingBusCommands;} private: - controller::ControllerState& state; const Configuration& config; + controller::ControllerState& state; + std::vector& checker; std::map> lastCommandsOnBus; - void scheduleRefresh(const controller::ScheduledCommand& command); - std::set pendingBusCommands; + + void refresh(const ScheduledCommand& command); + void precharge(const ScheduledCommand& command); + void activate(const ScheduledCommand& command); + void changeControllerState(const ScheduledCommand& command); }; } diff --git a/DRAM/src/core/scheduling/CommandSchedule.h b/DRAM/src/core/scheduling/CommandSchedule.h index 4d72de06..4abb111a 100644 --- a/DRAM/src/core/scheduling/CommandSchedule.h +++ b/DRAM/src/core/scheduling/CommandSchedule.h @@ -20,16 +20,11 @@ public: CommandSchedule(const tlm::tlm_generic_payload& transaction) : transaction(transaction) {}; virtual ~CommandSchedule() {} - void add(Command command, sc_time time, sc_time executionTime) + ScheduledCommand& add(Command command, sc_time time, sc_time executionTime) { assert(scheduledCommands.empty() || time >= scheduledCommands.back().getEnd()); scheduledCommands.push_back(ScheduledCommand(transaction, command, time, executionTime)); - } - - void add(ScheduledCommand scheduledCommand) - { - assert(&scheduledCommand.getTransaction() == &transaction); - scheduledCommands.push_back(scheduledCommand); + return scheduledCommands.back(); } const std::vector& getScheduledCommands() const diff --git a/DRAM/src/core/scheduling/CommandSequenceScheduler.cpp b/DRAM/src/core/scheduling/CommandSequenceScheduler.cpp index bab61737..b875232e 100644 --- a/DRAM/src/core/scheduling/CommandSequenceScheduler.cpp +++ b/DRAM/src/core/scheduling/CommandSequenceScheduler.cpp @@ -5,25 +5,25 @@ * Author: jonny */ -#include +#include "core/scheduling/CommandSequenceScheduler.h" +#include "core/Controller.h" namespace controller { -CommandSequenceScheduler::CommandSequenceScheduler() -{ - // TODO Auto-generated constructor stub - -} - -CommandSchedule CommandSequenceScheduler::prepareSchedule(tlm::tlm_generic_payload& transaction, CommandSequence commands) +CommandSchedule CommandSequenceScheduler::prepareSchedule(sc_time start, + tlm::tlm_generic_payload& transaction, CommandSequence commands) { CommandSchedule schedule(transaction); - for(unsigned int i = 0; i < commands.size(); ++i) + for (unsigned int i = 0; i < commands.size(); ++i) { Command command = commands.at(i); - sc_time start; - sc_time executionTime; - schedule.add(command, start, executionTime); + const ICommandChecker& checker = controller.getChecker(command); + + if (i > 0) + start = schedule.getEnd(); + sc_time executionTime(checker.getExecutionTime(transaction, command)); + ScheduledCommand& scheduledCommand = schedule.add(command, start, executionTime); + checker.check(scheduledCommand); } return schedule; } diff --git a/DRAM/src/core/scheduling/CommandSequenceScheduler.h b/DRAM/src/core/scheduling/CommandSequenceScheduler.h index 3264ab49..e4431abf 100644 --- a/DRAM/src/core/scheduling/CommandSequenceScheduler.h +++ b/DRAM/src/core/scheduling/CommandSequenceScheduler.h @@ -10,16 +10,24 @@ #include "CommandSchedule.h" #include "Command.h" +#include +#include "core/scheduling/checker/ICommandChecker.h" + + namespace controller { +class Controller; + class CommandSequenceScheduler { public: - CommandSequenceScheduler(); + CommandSequenceScheduler(const Controller& controller) : controller(controller){} virtual ~CommandSequenceScheduler(){} + CommandSchedule prepareSchedule(sc_time start, tlm::tlm_generic_payload& transaction, CommandSequence commands); - CommandSchedule prepareSchedule(tlm::tlm_generic_payload& transaction, CommandSequence commands); +private: + const Controller& controller; }; } /* namespace controller */ diff --git a/DRAM/src/core/scheduling/ScheduledCommand.h b/DRAM/src/core/scheduling/ScheduledCommand.h index 978c4608..8ceed8a9 100644 --- a/DRAM/src/core/scheduling/ScheduledCommand.h +++ b/DRAM/src/core/scheduling/ScheduledCommand.h @@ -59,6 +59,11 @@ public: return common::DramExtension::getExtension(&transaction).getBank(); } + common::Row getRow() const + { + return common::DramExtension::getExtension(&transaction).getRow(); + } + inline bool operator==(const ScheduledCommand& b) const { return b.command == command && b.start == start && b.executionTime == executionTime diff --git a/DRAM/src/core/scheduling/checker/ActivateChecker.cpp b/DRAM/src/core/scheduling/checker/ActivateChecker.cpp index ea079ac7..326099d7 100644 --- a/DRAM/src/core/scheduling/checker/ActivateChecker.cpp +++ b/DRAM/src/core/scheduling/checker/ActivateChecker.cpp @@ -23,6 +23,13 @@ void ActivateChecker::check(ScheduledCommand& command) const check_bus(command); } +sc_time ActivateChecker::getExecutionTime(const tlm::tlm_generic_payload& transaction, + Command command) const +{ + assert(command == Command::Activate); + return config.Timings.tRCD; +} + void ActivateChecker::check_activateToActivate(ScheduledCommand& command) const { if (bus.notYetScheduled(Command::Activate)) diff --git a/DRAM/src/core/scheduling/checker/ActivateChecker.h b/DRAM/src/core/scheduling/checker/ActivateChecker.h index 7acccced..7f4cd2b9 100644 --- a/DRAM/src/core/scheduling/checker/ActivateChecker.h +++ b/DRAM/src/core/scheduling/checker/ActivateChecker.h @@ -23,17 +23,18 @@ public: virtual ~ActivateChecker(){} virtual void check(ScheduledCommand& command) const; + virtual sc_time getExecutionTime(const tlm::tlm_generic_payload& transaction, Command command) const; virtual void cb_IInternalScheduler(const ScheduledCommand& command); private: const Configuration& config; - CommandBus& bus;//should be const .. but fucking map access operator!!!! + CommandBus& bus;//TODO should be const .. but fucking map access operator!!!! void check_activateToActivate(ScheduledCommand& command) const; void check_prechargeToActivate(ScheduledCommand& command) const; void check_nActivateWindow(ScheduledCommand& command) const; void check_bus(ScheduledCommand& command) const; - RingBuffer nActivateWindow; + RingBuffer nActivateWindow; }; } /* namespace controller */ diff --git a/DRAM/src/core/scheduling/checker/ICommandChecker.h b/DRAM/src/core/scheduling/checker/ICommandChecker.h index c7d22bb0..f83385f2 100644 --- a/DRAM/src/core/scheduling/checker/ICommandChecker.h +++ b/DRAM/src/core/scheduling/checker/ICommandChecker.h @@ -18,7 +18,8 @@ class ICommandChecker public: virtual ~ICommandChecker() {} - virtual void schedule(ScheduledCommand& command) const = 0; + virtual void check(ScheduledCommand& command) const = 0; + virtual sc_time getExecutionTime(const tlm::tlm_generic_payload& transaction, Command command) const = 0; virtual void cb_IInternalScheduler(const ScheduledCommand& command) = 0; }; diff --git a/DRAM/src/core/scheduling/checker/PrechargeChecker.cpp b/DRAM/src/core/scheduling/checker/PrechargeChecker.cpp index 3866edca..6cc78572 100644 --- a/DRAM/src/core/scheduling/checker/PrechargeChecker.cpp +++ b/DRAM/src/core/scheduling/checker/PrechargeChecker.cpp @@ -9,11 +9,17 @@ namespace controller { -void controller::PrechargeChecker::check(ScheduledCommand& command) const +void PrechargeChecker::check(ScheduledCommand& command) const { } -void controller::PrechargeChecker::cb_IInternalScheduler(const ScheduledCommand& command) +sc_time PrechargeChecker::getExecutionTime(const tlm::tlm_generic_payload& transaction, + Command command) const +{ + assert(command == Command::Precharge || command == Command::PrechargeAll); + return config.Timings.tRP; +} +void PrechargeChecker::cb_IInternalScheduler(const ScheduledCommand& command) { } diff --git a/DRAM/src/core/scheduling/checker/PrechargeChecker.h b/DRAM/src/core/scheduling/checker/PrechargeChecker.h index 4ef266f8..7aa7d417 100644 --- a/DRAM/src/core/scheduling/checker/PrechargeChecker.h +++ b/DRAM/src/core/scheduling/checker/PrechargeChecker.h @@ -21,6 +21,7 @@ public: virtual ~PrechargeChecker() {} virtual void check(ScheduledCommand& command) const; + virtual sc_time getExecutionTime(const tlm::tlm_generic_payload& transaction, Command command) const; virtual void cb_IInternalScheduler(const ScheduledCommand& command); private: const Configuration& config; diff --git a/DRAM/src/core/scheduling/checker/ReadChecker.cpp b/DRAM/src/core/scheduling/checker/ReadChecker.cpp index 11ed9a9c..e8a010ad 100644 --- a/DRAM/src/core/scheduling/checker/ReadChecker.cpp +++ b/DRAM/src/core/scheduling/checker/ReadChecker.cpp @@ -13,6 +13,13 @@ void ReadChecker::check(ScheduledCommand& command) const { } +sc_time ReadChecker::getExecutionTime(const tlm::tlm_generic_payload& transaction, + Command command) const +{ + assert(command == Command::Read || command == Command::ReadA); + return config.Timings.clk*8; +} + void ReadChecker::cb_IInternalScheduler(const ScheduledCommand& command) { } diff --git a/DRAM/src/core/scheduling/checker/ReadChecker.h b/DRAM/src/core/scheduling/checker/ReadChecker.h index 0630584a..d929ab69 100644 --- a/DRAM/src/core/scheduling/checker/ReadChecker.h +++ b/DRAM/src/core/scheduling/checker/ReadChecker.h @@ -21,6 +21,7 @@ public: virtual ~ReadChecker() {} virtual void check(ScheduledCommand& command) const; + virtual sc_time getExecutionTime(const tlm::tlm_generic_payload& transaction, Command command) const; virtual void cb_IInternalScheduler(const ScheduledCommand& command); private: const Configuration& config; diff --git a/DRAM/src/core/scheduling/checker/WriteChecker.cpp b/DRAM/src/core/scheduling/checker/WriteChecker.cpp index 1106fbc2..d3b1924d 100644 --- a/DRAM/src/core/scheduling/checker/WriteChecker.cpp +++ b/DRAM/src/core/scheduling/checker/WriteChecker.cpp @@ -13,6 +13,13 @@ void WriteChecker::check(ScheduledCommand& command) const { } +sc_time WriteChecker::getExecutionTime(const tlm::tlm_generic_payload& transaction, + Command command) const +{ + assert(command == Command::Write || command == Command::WriteA); + return config.Timings.clk*8; +} + void WriteChecker::cb_IInternalScheduler(const ScheduledCommand& command) { } diff --git a/DRAM/src/core/scheduling/checker/WriteChecker.h b/DRAM/src/core/scheduling/checker/WriteChecker.h index 360c5776..e1531d98 100644 --- a/DRAM/src/core/scheduling/checker/WriteChecker.h +++ b/DRAM/src/core/scheduling/checker/WriteChecker.h @@ -21,6 +21,7 @@ public: virtual ~WriteChecker() {} virtual void check(ScheduledCommand& command) const; + virtual sc_time getExecutionTime(const tlm::tlm_generic_payload& transaction, Command command) const; virtual void cb_IInternalScheduler(const ScheduledCommand& command); private: const Configuration& config; diff --git a/DRAM/src/core/utils/RingBuffer.h b/DRAM/src/core/utils/RingBuffer.h index 27c43aa0..7854a875 100644 --- a/DRAM/src/core/utils/RingBuffer.h +++ b/DRAM/src/core/utils/RingBuffer.h @@ -10,26 +10,29 @@ #include +template class RingBuffer { public: RingBuffer(unsigned int maxSize) : maxSize(maxSize) {} - void put(sc_time t) + void put(T t) { - buffer.push_front(t); + buffer.push_back(t); if(getSize()>maxSize) - buffer.pop_back(); + buffer.pop_front(); } - sc_time getOldest() const + T getOldest() const { + assert(!isEmpty()); return buffer.front(); } - sc_time getNewest() const + T getNewest() const { + assert(!isEmpty()); return buffer.back(); } @@ -48,13 +51,14 @@ public: return buffer.size(); } - const sc_time get(unsigned int i) const + const T get(unsigned int i) const { - return buffer.at(i); + assert(i buffer; + std::deque buffer; unsigned int maxSize; }; diff --git a/DRAM/src/core/utils/Utils.cpp b/DRAM/src/core/utils/Utils.cpp index 99f1b676..93ecf2d7 100644 --- a/DRAM/src/core/utils/Utils.cpp +++ b/DRAM/src/core/utils/Utils.cpp @@ -16,15 +16,13 @@ unsigned int getStartAddress(Bank bank) sc_time delayByConstraint(sc_time previous, sc_time start, sc_time constraint) { - assert(start > previous); - sc_time distance = start - previous; - if (distance < constraint) - return constraint - distance; + if (previous + constraint > start) + return previous + constraint - start; else return SC_ZERO_TIME; } -sc_time clkAlign(sc_time time, sc_time clk, Alignment alignment) +const sc_time clkAlign(sc_time time, sc_time clk, Alignment alignment) { if (alignment == Alignment::UP) return ceil(time / clk) * clk; diff --git a/DRAM/src/core/utils/Utils.h b/DRAM/src/core/utils/Utils.h index c1b44e04..247caefb 100644 --- a/DRAM/src/core/utils/Utils.h +++ b/DRAM/src/core/utils/Utils.h @@ -17,7 +17,7 @@ sc_time delayByConstraint(sc_time previous, sc_time start, sc_time constraint); enum class Alignment {UP, DOWN}; -sc_time clkAlign(sc_time time, sc_time clk, Alignment alignment = Alignment::UP); +const sc_time clkAlign(sc_time time, sc_time clk, Alignment alignment = Alignment::UP); bool isClkAligned(sc_time time, sc_time clk); #endif /* UTILS_H_ */ diff --git a/DRAM/testing/CommandBus_test.cpp b/DRAM/testing/CommandBus_test.cpp index 323eff7e..cb7eedd5 100644 --- a/DRAM/testing/CommandBus_test.cpp +++ b/DRAM/testing/CommandBus_test.cpp @@ -23,14 +23,14 @@ namespace controller { class CommandBusTest: public Test { public: - CommandBusTest() : config(), state(config.numberOfBanks), bus(config, state), clk(config.Timings.clk){} + CommandBusTest() : config(), state(config.numberOfBanks), bus(config, state, checker), clk(config.Timings.clk){} Configuration config; ControllerState state; CommandBus bus; + std::vector checker; sc_time clk; - }; TEST_F(CommandBusTest, cleanUpBusWorks) diff --git a/DRAM/testing/Utils_test.cpp b/DRAM/testing/Utils_test.cpp new file mode 100644 index 00000000..be265dd4 --- /dev/null +++ b/DRAM/testing/Utils_test.cpp @@ -0,0 +1,76 @@ +/* + * Utils_test.cpp + * + * Created on: Mar 14, 2014 + * Author: jonny + */ + +#include +#include "core/utils/Utils.h" +#include "core/utils/RingBuffer.h" + +//using namespace testing; + +namespace controller { + +TEST(UtilsTest, clkAlignWorks) +{ + sc_time clk(6, SC_NS); + sc_time aligned = 2* clk; + sc_time not_aligned = 2.5*clk; + + EXPECT_EQ(aligned, clkAlign(aligned, clk, Alignment::UP)); + EXPECT_EQ(aligned, clkAlign(aligned, clk, Alignment::DOWN)); + EXPECT_EQ(aligned+clk, clkAlign(not_aligned, clk, Alignment::UP)); + EXPECT_EQ(aligned+clk, clkAlign(not_aligned, clk)); + EXPECT_EQ(aligned, clkAlign(not_aligned, clk, Alignment::DOWN)); +} + +TEST(UtilsTest, isClkAlignedWorks) +{ + sc_time clk(6, SC_NS); + sc_time aligned = 2*clk; + sc_time not_aligned = 2.5 * clk; + + EXPECT_TRUE(isClkAligned(aligned, clk)); + EXPECT_FALSE(isClkAligned(not_aligned, clk)); +} + +TEST(UtilsTest, delayByConstraintWorks) +{ + sc_time start(10, SC_NS); + sc_time previous(8, SC_NS); + sc_time constraint(4, SC_NS); + + EXPECT_EQ(sc_time(2, SC_NS), delayByConstraint(previous, start, constraint)); + EXPECT_EQ(sc_time(4, SC_NS), delayByConstraint(previous, sc_time(8, SC_NS), constraint)); + EXPECT_EQ(sc_time(6, SC_NS), delayByConstraint(previous, sc_time(6, SC_NS), constraint)); + EXPECT_EQ(sc_time(0, SC_NS), delayByConstraint(previous, sc_time(12, SC_NS), constraint)); + EXPECT_EQ(sc_time(0, SC_NS), delayByConstraint(previous, sc_time(14, SC_NS), constraint)); +} + +TEST(UtilsTest, RingBufferWorks) +{ + RingBuffer buffer(4); + EXPECT_TRUE(buffer.isEmpty()); + EXPECT_EQ(0, buffer.getSize()); + EXPECT_DEATH(buffer.get(0), ".*"); + EXPECT_FALSE(buffer.isFull()); + buffer.put(3); + EXPECT_EQ(1, buffer.getSize()); + EXPECT_FALSE(buffer.isFull()); + buffer.put(5); + buffer.put(4); + EXPECT_EQ(4, buffer.getNewest()); + EXPECT_EQ(3, buffer.getOldest()); + EXPECT_FALSE(buffer.isFull()); + buffer.put(9); + buffer.put(10); + EXPECT_EQ(10, buffer.getNewest()); + EXPECT_EQ(5, buffer.getOldest()); + EXPECT_EQ(9, buffer.get(2)); + EXPECT_TRUE(buffer.isFull()); +} + +} /* namespace controller */ + diff --git a/DRAM/testing/ActivateChecker_test.cpp b/DRAM/testing/checker/ActivateChecker_test.cpp similarity index 100% rename from DRAM/testing/ActivateChecker_test.cpp rename to DRAM/testing/checker/ActivateChecker_test.cpp diff --git a/DRAM/testing/PrechargeChecker_test.cpp b/DRAM/testing/checker/PrechargeChecker_test.cpp similarity index 100% rename from DRAM/testing/PrechargeChecker_test.cpp rename to DRAM/testing/checker/PrechargeChecker_test.cpp diff --git a/DRAM/testing/ReadChecker_test.cpp b/DRAM/testing/checker/ReadChecker_test.cpp similarity index 100% rename from DRAM/testing/ReadChecker_test.cpp rename to DRAM/testing/checker/ReadChecker_test.cpp diff --git a/DRAM/testing/WriteChecker_test.cpp b/DRAM/testing/checker/WriteChecker_test.cpp similarity index 100% rename from DRAM/testing/WriteChecker_test.cpp rename to DRAM/testing/checker/WriteChecker_test.cpp