From da28a5242b3fbb1d3ccaf47ee80f6f503f33bd6b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=89der=20F=2E=20Zulian?= Date: Fri, 12 Feb 2016 11:55:57 -0200 Subject: [PATCH] PEP8 related changes. These changes are a step forward in the direction of the PEP8 style guide for python code. They do not affect functionality itself. See also: https://www.python.org/dev/peps/pep-0008/ --- DRAMSys/analyzer/scripts/tests.py | 331 +++++++++++++++--------------- 1 file changed, 168 insertions(+), 163 deletions(-) diff --git a/DRAMSys/analyzer/scripts/tests.py b/DRAMSys/analyzer/scripts/tests.py index e824378a..7e447357 100644 --- a/DRAMSys/analyzer/scripts/tests.py +++ b/DRAMSys/analyzer/scripts/tests.py @@ -13,7 +13,7 @@ class MemConfig(object): proper format when searching for elements. """ def getValue(self, id): - return self.xmlMemSpec.findall(id)[0].attrib['value'] + return self.xmlMemConfig.findall(id)[0].attrib['value'] def getIntValue(self, id): return int(self.getValue(id)) @@ -22,7 +22,7 @@ class MemConfig(object): cursor = dbconnection.cursor() cursor.execute("SELECT Memconfig FROM GeneralInfo") result = cursor.fetchone() - self.xmlMemSpec = ET.parse(result[0]) + self.xmlMemConfig = ET.parse(result[0]) class MemSpec(object): @@ -51,6 +51,7 @@ def getClock(connection): result = cursor.fetchone() return (result[0], result[1]) + class DramConfig(object): memoryType = "" scheduler = "" @@ -61,30 +62,29 @@ class DramConfig(object): nActivateWindow = numberOfBanks = 0 clk = 0 - tRP = 0 #precharge-time (pre -> act same bank) - tRAS = 0 #active-time (act -> pre same bank) - tRC = 0 #RAS-cycle-time (min time bw 2 succesive ACT to same bank) - tCCD_S = 0 #TODO: relevant? max(bl, tCCD) + tRP = 0 # precharge-time (pre -> act same bank) + tRAS = 0 # active-time (act -> pre same bank) + tRC = 0 # RAS-cycle-time (min time bw 2 succesive ACT to same bank) + tCCD_S = 0 # TODO: relevant? max(bl, tCCD) tCCD_L = 0 - tRTP = 0 #Read to precharge - tRRD_S = 0 #min time bw 2 succesive ACT to different banks (different bank group) - tRRD_L = 0 #.. (same bank group) - tRCD = 0 #act -> read/write - tNAW = 0 #n activate window - tRL = 0 #read latency (read command start to data strobe) - tWL = 0 #write latency - tWR = 0 #write recovery (write to precharge) - tWTR_S = 0 #write to read (different bank group) - tWTR_L = 0 #.. (same bank group) - tCKESR = 0 #min time in sref - tCKE = 0 #min time in pdna or pdnp - tXP = 0 #min delay to row access command after pdnpx pdnax - tXPDLL = 0 #min delay to row access command after pdnpx pdnax for dll commands - tXSR = 0 #min delay to row access command after srefx - tXSRDLL = 0 #min delay to row access command after srefx for dll commands - tAL = 0 #additive delay (delayed execution in dram) - tRFC = 0 #min ref->act delay - + tRTP = 0 # Read to precharge + tRRD_S = 0 # min time between 2 succesive ACT to different banks (different bank group) + tRRD_L = 0 # min time between 2 succesive ACT to different banks (same bank group) + tRCD = 0 # act -> read/write + tNAW = 0 # n activate window + tRL = 0 # read latency (read command start to data strobe) + tWL = 0 # write latency + tWR = 0 # write recovery (write to precharge) + tWTR_S = 0 # write to read (different bank group) + tWTR_L = 0 # write to read (same bank group) + tCKESR = 0 # min time in sref + tCKE = 0 # min time in pdna or pdnp + tXP = 0 # min delay to row access command after pdnpx pdnax + tXPDLL = 0 # min delay to row access command after pdnpx pdnax for dll commands + tXSR = 0 # min delay to row access command after srefx + tXSRDLL = 0 # min delay to row access command after srefx for dll commands + tAL = 0 # additive delay (delayed execution in dram) + tRFC = 0 # min ref->act delay def readConfigFromFiles(self, connection): print("Parsing dram configuration") @@ -100,13 +100,12 @@ class DramConfig(object): self.scheduler = memconfig.getValue("Scheduler") self.numberOfBanks = memspec.getIntValue("nbrOfBanks") - print(self.numberOfBanks) self.burstLength = memspec.getIntValue("burstLength") self.memoryType = memspec.getValue("memoryType") - self.dataRate = memspec.getIntValue("dataRate") + self.dataRate = memspec.getIntValue("dataRate") - if(self.memoryType == "WIDEIO_SDR"): - self.nActivateWindow = 2; + if (self.memoryType == "WIDEIO_SDR"): + self.nActivateWindow = 2 self.tRP = self.clk * memspec.getIntValue("RP") self.tRAS = self.clk * memspec.getIntValue("RAS") self.tRC = self.clk * memspec.getIntValue("RC") @@ -121,7 +120,7 @@ class DramConfig(object): self.tWR = self.clk * memspec.getIntValue("WR") self.tWTR_S = self.clk * memspec.getIntValue("WTR") self.tWTR_L = self.tWTR_S - self.tRTP = self.clk * memspec.getIntValue("RTP"); + self.tRTP = self.clk * memspec.getIntValue("RTP") self.tCKESR = self.clk * memspec.getIntValue("CKESR") self.tCKE = self.clk * memspec.getIntValue("CKE") self.tXP = self.clk * memspec.getIntValue("XP") @@ -131,7 +130,7 @@ class DramConfig(object): self.tAL = self.clk * memspec.getIntValue("AL") self.tRFC = self.clk * memspec.getIntValue("RFC") - elif(self. memoryType == "DDR4"): + elif (self. memoryType == "DDR4"): self.nActivateWindow = 4 self.tRP = self.clk * memspec.getIntValue("RP") self.tRAS = self.clk * memspec.getIntValue("RAS") @@ -152,7 +151,7 @@ class DramConfig(object): self.tCKE = self.clk * memspec.getIntValue("CKE") self.tXP = self.clk * memspec.getIntValue("XP") self.tXPDLL = self.clk * memspec.getIntValue("XPDLL") - self.tXSR = self.clk * memspec.getIntValue("XS"); + self.tXSR = self.clk * memspec.getIntValue("XS") self.tXSRDLL = self.clk * memspec.getIntValue("XSDLL") self.tAL = self.clk * memspec.getIntValue("AL") self.tRFC = self.clk * memspec.getIntValue("RFC") @@ -165,7 +164,7 @@ class DramConfig(object): return math.ceil(1.0*value/self.clk)*self.clk def getWriteAccessTime(self): - if(self.dataRate == 1): + if (self.dataRate == 1): return self.clk*(self.burstLength - 1) elif (self.memoryType == "DDR4"): return self.clk*self.burstLength/self.dataRate @@ -176,18 +175,23 @@ class DramConfig(object): def __init__(self): pass + dramconfig = DramConfig() + def calculateReadLength(burstLength): return dramconfig.tRL + burstLength * dramconfig.clk + def calculateWriteLength(burstLength): return dramconfig.tWL + burstLength * dramconfig.clk + # ----------- test utils --------------------------------------- tests = [] + def test(function): tests.append(function) return function @@ -196,7 +200,8 @@ def test(function): class TestResult(object): passed = True message = '' - def __init__(self, passed = True, message = ''): + + def __init__(self, passed=True, message=''): self.passed = passed self.message = message @@ -206,7 +211,7 @@ def TestSuceeded(): def TestFailed(message): - return TestResult(False,message); + return TestResult(False, message) def formatTime(time): @@ -214,6 +219,7 @@ def formatTime(time): # ----------- checks --------------------------------------- + @test def commands_are_clockaligned(connection): """Checks that all commands on the command bus are aligned to the system clock""" @@ -224,9 +230,8 @@ def commands_are_clockaligned(connection): result = cursor.fetchone() - if(result != None): - return TestFailed("Command with PhaseID {0} starts at {1} and ends at. One of those times. is not aligned to system clock ({2})" - .format(result[0], formatTime(result[1]), formatTime(result[2]), formatTime(dramconfig.clk))) + if (result is not None): + return TestFailed("Command with PhaseID {0} starts at {1} and ends at. One of those times. is not aligned to system clock ({2})".format(result[0], formatTime(result[1]), formatTime(result[2]), formatTime(dramconfig.clk))) return TestSuceeded() @@ -246,7 +251,7 @@ def commandbus_slots_are_used_once(connection): cursor.execute(query) result = cursor.fetchone() - if(result != None): + if (result is not None): return TestFailed("Slot on commandbus at time {0} is used multiple times".format(formatTime(result[0]))) return TestSuceeded() @@ -260,37 +265,36 @@ def phase_transitions_are_valid(connection): # validTransitions tells you which phases are allowed to follow the last transaction. - if(dramconfig.bankwiseLogic == "1"): + if (dramconfig.bankwiseLogic == "1"): validTransitions['PRE'] = set(['ACT', 'REFB']) validTransitions['ACT'] = set(['RD', 'RDA', 'WR', 'WRA', 'PRE', 'PRE_ALL']) - validTransitions['RD'] = set(['PRE','RD','RDA', 'WR', 'WRA', 'PDNAB']) - validTransitions['WR'] = set(['PRE', 'RD','RDA', 'WR', 'WRA', 'PDNAB']) + validTransitions['RD'] = set(['PRE', 'RD', 'RDA', 'WR', 'WRA', 'PDNAB']) + validTransitions['WR'] = set(['PRE', 'RD', 'RDA', 'WR', 'WRA', 'PDNAB']) validTransitions['RDA'] = set(['ACT', 'REFB', 'PDNPB']) validTransitions['WRA'] = set(['ACT', 'REFB', 'PDNPB']) validTransitions['REFB'] = set(['ACT', 'PDNPB', 'SREFB']) - validTransitions['PDNAB'] = set(['PRE', 'RD','RDA', 'WR', 'WRA', 'REFB']) + validTransitions['PDNAB'] = set(['PRE', 'RD', 'RDA', 'WR', 'WRA', 'REFB']) validTransitions['PDNPB'] = set(['ACT', 'REFB']) validTransitions['SREFB'] = set(['ACT']) else: - validTransitions['PRE'] = set(['ACT','PRE_ALL']) + validTransitions['PRE'] = set(['ACT', 'PRE_ALL']) validTransitions['PRE_ALL'] = set(['REFA']) validTransitions['ACT'] = set(['RD', 'RDA', 'WR', 'WRA', 'PRE_ALL']) - validTransitions['RD'] = set(['PRE', 'PRE_ALL','RD','RDA', 'WR', 'WRA', 'PDNA']) - validTransitions['WR'] = set(['PRE', 'PRE_ALL','RD','RDA', 'WR', 'WRA', 'PDNA']) + validTransitions['RD'] = set(['PRE', 'PRE_ALL', 'RD', 'RDA', 'WR', 'WRA', 'PDNA']) + validTransitions['WR'] = set(['PRE', 'PRE_ALL', 'RD', 'RDA', 'WR', 'WRA', 'PDNA']) validTransitions['RDA'] = set(['PRE_ALL', 'ACT', 'REFA', 'PDNA', 'PDNP']) validTransitions['WRA'] = set(['PRE_ALL', 'ACT', 'REFA', 'PDNA', 'PDNP']) - validTransitions['REFA'] = set(['PRE_ALL', 'ACT','REFA', 'PDNA', 'PDNP', 'SREF']) + validTransitions['REFA'] = set(['PRE_ALL', 'ACT', 'REFA', 'PDNA', 'PDNP', 'SREF']) - validTransitions['PDNA'] = set(['PRE','PRE_ALL','ACT', 'RD', 'RDA', 'WR', 'WRA', 'REFA', 'PDNA', 'PDNP']) + validTransitions['PDNA'] = set(['PRE', 'PRE_ALL', 'ACT', 'RD', 'RDA', 'WR', 'WRA', 'REFA', 'PDNA', 'PDNP']) validTransitions['PDNP'] = set(['PRE_ALL', 'ACT', 'REFA', 'PDNA', 'PDNP']) validTransitions['SREF'] = set(['PRE_ALL', 'ACT', 'REFA', 'PDNA', 'PDNP']) - # This was the original query: # query = """SELECT PhaseName, phases.ID FROM phases INNER JOIN transactions ON phases.transact=transactions.ID WHERE TBank=:bank AND PhaseName NOT IN ('REQ','RESP') ORDER BY PhaseBegin""" # However, refreshes and pre_all are attributed to Bank 0 therefore this must be added to the order evaluation: @@ -307,10 +311,10 @@ def phase_transitions_are_valid(connection): lastRow = cursor.fetchone() for currentRow in cursor: currentPhase = currentRow[0] - lastPhase = lastRow[0] + lastPhase = lastRow[0] - if(currentPhase not in validTransitions[lastPhase]): - return TestFailed("Phase {0}({1}) is not allowed to follow phase {2}({3})".format(currentRow[1],currentPhase,lastRow[1],lastPhase)) + if (currentPhase not in validTransitions[lastPhase]): + return TestFailed("Phase {0}({1}) is not allowed to follow phase {2}({3})".format(currentRow[1], currentPhase, lastRow[1], lastPhase)) lastRow = currentRow return TestSuceeded() @@ -320,49 +324,54 @@ def timing_constraint(FirstPhase, SecondPhase): FirstPhaseName = FirstPhase[0] SecondPhaseName = SecondPhase[0] - if(FirstPhaseName == "PRE" or FirstPhaseName == "PRE_ALL"): + if (FirstPhaseName == "PRE" or FirstPhaseName == "PRE_ALL"): return dramconfig.tRP - elif(FirstPhaseName == "ACT"): + elif (FirstPhaseName == "ACT"): return dramconfig.tRCD - elif(FirstPhaseName == "RD"): - if(SecondPhaseName in ["PRE, PRE_ALL"]): + elif (FirstPhaseName == "RD"): + if (SecondPhaseName in ["PRE, PRE_ALL"]): return dramconfig.tRTP - elif(SecondPhaseName in ["RD, RDA"]): + elif (SecondPhaseName in ["RD, RDA"]): return max(dramconfig.tCCD_L, getReadAccessTime()) - elif(SecondPhase in ["WR","WRA"]): - return dramconfig.tRL + getReadAccessTime() - dramconfig.tWL + 2*dramconfig.clk - elif(SecondPhase == "PDNA" ): + elif (SecondPhase in ["WR", "WRA"]): + return dramconfig.tRL + getReadAccessTime() - dramconfig.tWL + 2 * dramconfig.clk + elif (SecondPhase == "PDNA"): return dramconfig.tRL + getReadAccessTime() + dramconfig.clk - elif(FirstPhaseName == "WR"): - if(SecondPhaseName in ["PRE, PRE_ALL", "PDNA"]): + elif (FirstPhaseName == "WR"): + if (SecondPhaseName in ["PRE, PRE_ALL", "PDNA"]): return dramconfig.tWL + dramconfig.getWriteAccessTime() + dramconfig.tWR - elif(SecondPhaseName in ["RD, RDA"]): + elif (SecondPhaseName in ["RD, RDA"]): return dramconfig.tWL + dramconfig.getWriteAccessTime() + dramconfig.tWTR_L - elif(SecondPhaseName in ["WR, WRA"]): + elif (SecondPhaseName in ["WR, WRA"]): return max(dramconfig.tCCD_L, burstlength/dramconfig.dataRate) - elif(FirstPhaseName == "RDA"): - if(SecondPhaseName in ["ACT", "PRE_ALL", "REFA"]): + elif (FirstPhaseName == "RDA"): + if (SecondPhaseName in ["ACT", "PRE_ALL", "REFA"]): return dramconfig.tRTP + dramconfig.tRP - elif(SecondPhaseName in ["PDNA","PDNP"]): + elif (SecondPhaseName in ["PDNA", "PDNP"]): return dramconfig.tRL + getReadAccessTime() + dramconfig.clk - elif(FirstPhaseName == "WRA"): - if(SecondPhaseName in ["ACT", "PRE_ALL", "REFA"]): + elif (FirstPhaseName == "WRA"): + if (SecondPhaseName in ["ACT", "PRE_ALL", "REFA"]): return dramconfig.tWL + getWriteAccessTime() + dramconfig.tWR + dramconfig.tRP - elif(SecondPhaseName in ["PDNA","PDNP"]): + elif (SecondPhaseName in ["PDNA", "PDNP"]): return dramconfig.tWL + dramconfig.getWriteAccessTime() + dramconfig.tWR + dramconfig.clk - elif(FirstPhaseName == "REFA"): + elif (FirstPhaseName == "REFA"): return dramconfig.tRFC - elif(FirstPhaseName in ["PDNA","PDNP"]): + elif (FirstPhaseName in ["PDNA", "PDNP"]): + print("{0}".format(FirstPhaseName)) + print("{0}".format(formatTime(FirstPhase[3]))) + print("{0}".format(formatTime(FirstPhase[2]))) + print("{0}".format(formatTime(dramconfig.tXP))) + print("{0}".format(formatTime(dramconfig.clk))) return (FirstPhase[3] - FirstPhase[2]) + dramconfig.tXP - dramconfig.clk - elif(FirstPhaseName == "SREF"): + elif (FirstPhaseName == "SREF"): return (FirstPhase[3] - FirstPhase[2]) + dramconfig.tXSR - dramconfig.clk return 0 @@ -374,7 +383,7 @@ def timing_constraits_on_the_same_bank_hold(connection): cursor = connection.cursor() validTransitions = {} - query = """SELECT PhaseName, phases.ID,PhaseBegin,PhaseEnd FROM phases INNER JOIN transactions ON phases.transact=transactions.ID WHERE TBank=:bank + query = """SELECT PhaseName, phases.ID, PhaseBegin, PhaseEnd FROM phases INNER JOIN transactions ON phases.transact=transactions.ID WHERE TBank=:bank AND PhaseName NOT IN ('REQ','RESP') ORDER BY PhaseBegin""" for bankNumber in range(dramconfig.numberOfBanks): @@ -382,11 +391,11 @@ def timing_constraits_on_the_same_bank_hold(connection): lastRow = cursor.fetchone() for currentRow in cursor: - constraint = timing_constraint(lastRow,currentRow) - if(currentRow[2] - lastRow[2] + constraint < 0): - return TestFailed("Phase {0}({1}) starts {2} after Start of Phase {3}({4}). Minimal time is {5}".format( - currentRow[1],currentRow[0],formatTime(currentRow[2]-lastRow[2]),lastRow[1],lastRow[0], formatTime(constraint))) + constraint = timing_constraint(lastRow, currentRow) + if (currentRow[2] - (lastRow[2] + constraint) < 0): + return TestFailed("Phase {0}({1}) starts {2} after Start of Phase {3}({4}). Minimal time is {5}".format(currentRow[1], currentRow[0], formatTime(currentRow[2] - lastRow[2]), lastRow[1], lastRow[0], formatTime(constraint))) lastRow = currentRow + return TestSuceeded() @@ -406,37 +415,37 @@ def row_buffer_is_used_correctly(connection): ((TBank=:bank) OR (PhaseNAME = "REFA" AND TBank=0) OR (PhaseNAME = "PRE_ALL" AND TBank=0)) AND PhaseName NOT IN ('REQ','RESP') ORDER BY PhaseBegin""" + # phases that precharge the bank and close the rowbuffer + prechargingPhases = set(['PRE', 'PRE_ALL', 'RDA', 'WRA']) - #phases that precharge the bank and close the rowbuffer - prechargingPhases = set(['PRE','PRE_ALL','RDA','WRA']) + # phases that require the bank to be in active state and the rowbuffer to be opened + accessingPhases = set(['RD', 'RDA', 'WR', 'WRA', 'PRE']) - #phases that require the bank to be in active state and the rowbuffer to be opened - accessingPhases = set(['RD','RDA', 'WR', 'WRA', 'PRE']) - - #phases that require the bank to be in precharged state and the robuffer to be closed - idlePhases = set(['ACT', 'PDNP', 'REFA', 'SREF']) + # phases that require the bank to be in precharged state and the robuffer to be closed + idlePhases = set(['ACT', 'PDNP', 'REFA', 'SREF']) for bankNumber in range(dramconfig.numberOfBanks): - cursor.execute(query,{"bank": bankNumber}) + cursor.execute(query, {"bank": bankNumber}) rowBufferIsClosed = True for currentRow in cursor: - if(currentRow[0] in accessingPhases and rowBufferIsClosed == True): + if ((currentRow[0] in accessingPhases) and (rowBufferIsClosed is True)): return TestFailed("Phase {0}({1}) acesses a closed rowbuffer".format(currentRow[1], currentRow[0])) - if(currentRow[0] in idlePhases and rowBufferIsClosed == False): + if ((currentRow[0] in idlePhases) and (rowBufferIsClosed is False)): return TestFailed("Phase {0}({1}) needs a closed rowbuffer".format(currentRow[1], currentRow[0])) - if(currentRow[0] == 'ACT'): + if (currentRow[0] == 'ACT'): rowBufferIsClosed = False - if(currentRow[0] in prechargingPhases): + if (currentRow[0] in prechargingPhases): rowBufferIsClosed = True return TestSuceeded() -#----------- activate checks --------------------------------------- + +# ----------- activate checks --------------------------------------- @test def activate_to_activate_holds(connection): """Checks that all activates are far enough apart(JESD229 229, P. 27)""" @@ -445,14 +454,13 @@ def activate_to_activate_holds(connection): lastRow = cursor.fetchone() for currentRow in cursor: - timeBetweenActivates = currentRow[1] - lastRow[1] + timeBetweenActivates = currentRow[1] - lastRow[1] if (currentRow[2] == lastRow[2]): minTime = dramconfig.tRRD_L else: minTime = dramconfig.tRRD_S - if(timeBetweenActivates < minTime): - return TestFailed("Activates with PhaseIDs {0} and {1} are {2} apart. Minimum time between two activates is {3}". - format(currentRow[0], lastRow[0],formatTime(timeBetweenActivates), formatTime(minTime))) + if (timeBetweenActivates < minTime): + return TestFailed("Activates with PhaseIDs {0} and {1} are {2} apart. Minimum time between two activates is {3}".format(currentRow[0], lastRow[0], formatTime(timeBetweenActivates), formatTime(minTime))) lastRow = currentRow @@ -466,19 +474,19 @@ def activate_to_activate_on_same_bank_holds(connection): query = "SELECT Phases.ID,PhaseBegin from Phases INNER JOIN Transactions ON Phases.Transact = Transactions.ID WHERE PhaseName = 'ACT' AND TBANK = :bank ORDER BY PhaseBegin" for bankNumber in range(dramconfig.numberOfBanks): - cursor.execute(query,{"bank": bankNumber}) + cursor.execute(query, {"bank": bankNumber}) lastRow = cursor.fetchone() for currentRow in cursor: - timeBetweenActivates = currentRow[1] - lastRow[1]; - if(timeBetweenActivates < dramconfig.tRC): - return TestFailed("Activates with PhaseIDs {0} and {1} are {2} apart. Minimum time between two activates is {3}, since they are on the same bank({4})". - format(currentRow[0], lastRow[0],formatTime(timeBetweenActivates), dramconfig.tRC)) + timeBetweenActivates = currentRow[1] - lastRow[1] + if (timeBetweenActivates < dramconfig.tRC): + return TestFailed("Activates with PhaseIDs {0} and {1} are {2} apart. Minimum time between two activates is {3}, since they are on the same bank({4})".format(currentRow[0], lastRow[0], formatTime(timeBetweenActivates), dramconfig.tRC)) else: lastRow = currentRow return TestSuceeded() + @test def n_activate_window_holds(connection): """Checks that the n-Activate constraint is met everywhere(JEDEC 229, P. 27)""" @@ -488,15 +496,14 @@ def n_activate_window_holds(connection): for currentRow in cursor: activateWindow.append(currentRow[1]) - if(len(activateWindow) > dramconfig.nActivateWindow + 1): + if (len(activateWindow) > dramconfig.nActivateWindow + 1): activateWindow.pop(0) - if(activateWindow[dramconfig.nActivateWindow] - activateWindow[0] < dramconfig.tNAW): - return TestFailed("Activate with PhaseID {0} and the {1} preceeding activates violate the '{1} activate window' constraint." - " No more than {1} activates should be in rolling time window of {2}".format(currentRow[0], dramconfig.nActivateWindow,formatTime(dramconfig.tNAW))) + if (activateWindow[dramconfig.nActivateWindow] - activateWindow[0] < dramconfig.tNAW): + return TestFailed("Activate with PhaseID {0} and the {1} preceeding activates violate the '{1} activate window' constraint. No more than {1} activates should be in rolling time window of {2}".format(currentRow[0], dramconfig.nActivateWindow, formatTime(dramconfig.tNAW))) return TestSuceeded() - # ----------- read/write checks --------------------------------------- +# ----------- read/write checks --------------------------------------- @test def read_to_read_holds(connection): """Check that the read operations do not intefere with each other on the data bus""" @@ -505,13 +512,13 @@ def read_to_read_holds(connection): lastRow = cursor.fetchone() for currentRow in cursor: - timeBetweenReads = currentRow[1] - lastRow[1] + timeBetweenReads = currentRow[1] - lastRow[1] if (currentRow[2] == lastRow[2]): - minTime = max(dramconfig.tCCD_L,dramconfig.getReadAccessTime()) + minTime = max(dramconfig.tCCD_L, dramconfig.getReadAccessTime()) else: - minTime = max(dramconfig.tCCD_S,dramconfig.getReadAccessTime()) - if(timeBetweenReads < minTime): - return TestFailed("Reads with PhaseIDs {0} and {1} are {2} apart. Minimum time between two reads is {3}".format(currentRow[0], lastRow[0],formatTime(timeBetweenReads), minTime)) + minTime = max(dramconfig.tCCD_S, dramconfig.getReadAccessTime()) + if (timeBetweenReads < minTime): + return TestFailed("Reads with PhaseIDs {0} and {1} are {2} apart. Minimum time between two reads is {3}".format(currentRow[0], lastRow[0], formatTime(timeBetweenReads), minTime)) lastRow = currentRow return TestSuceeded() @@ -526,16 +533,17 @@ def write_to_write_holds(connection): lastRow = cursor.fetchone() for currentRow in cursor: - timeBetweenWrites = currentRow[1] - lastRow[1] + timeBetweenWrites = currentRow[1] - lastRow[1] if (currentRow[2] == lastRow[2]): - minTime = max(dramconfig.tCCD_L,dramconfig.getWriteAccessTime()) + minTime = max(dramconfig.tCCD_L, dramconfig.getWriteAccessTime()) else: - minTime = max(dramconfig.tCCD_S,dramconfig.getWriteAccessTime()) - if(timeBetweenWrites < minTime): - return TestFailed("Writes with PhaseIDs {0} and {1} are {2} apart. Minimum time between two writes is {3}".format(currentRow[0], lastRow[0],formatTime(timeBetweenWrites), minTime)) + minTime = max(dramconfig.tCCD_S, dramconfig.getWriteAccessTime()) + if (timeBetweenWrites < minTime): + return TestFailed("Writes with PhaseIDs {0} and {1} are {2} apart. Minimum time between two writes is {3}".format(currentRow[0], lastRow[0], formatTime(timeBetweenWrites), minTime)) lastRow = currentRow return TestSuceeded() + @test def write_to_read_and_read_to_write_hold(connection): """Checks that read and write operation do not interfere with each other on the data bus @@ -549,9 +557,8 @@ def write_to_read_and_read_to_write_hold(connection): lastRow = cursor.fetchone() for currentRow in cursor: - - if(currentRow[2] in ["RD","RDA"] and lastRow[2] in ["WR","WRA"]): - #write to read + if (currentRow[2] in ["RD", "RDA"] and lastRow[2] in ["WR", "WRA"]): + # write to read if (currentRow[3] == lastRow[3]): tWTR = dramconfig.tWTR_L else: @@ -560,22 +567,21 @@ def write_to_read_and_read_to_write_hold(connection): minWriteToRead = dramconfig.tWL + dramconfig.getWriteAccessTime() + tWTR writeToRead = currentRow[1] - lastRow[1] - if(writeToRead < minWriteToRead ): - return TestFailed("Read {0} starts {1} after start of write {2}. Minimum time is {3}". - format(currentRow[0],formatTime(writeToRead),lastRow[0], formatTime(minWriteToRead))) + if (writeToRead < minWriteToRead): + return TestFailed("Read {0} starts {1} after start of write {2}. Minimum time is {3}".format(currentRow[0], formatTime(writeToRead), lastRow[0], formatTime(minWriteToRead))) - elif(currentRow[2] in ["WR","WRA"] and lastRow[2] in ["RD","RDA"]): - #read to write + elif (currentRow[2] in ["WR", "WRA"] and lastRow[2] in ["RD", "RDA"]): + # read to write minReadToWrite = dramconfig.tRL + dramconfig.getReadAccessTime() - dramconfig.tWL + dramconfig.clk * 2 readToWrite = currentRow[1] - lastRow[1] - if(readToWrite < minReadToWrite ): - return TestFailed("Write {0} starts {1} after start of read {2}. Minimum time is {3}". - format(currentRow[0],formatTime(readToWrite),lastRow[0], formatTime(minWriteToRead))) + if (readToWrite < minReadToWrite): + return TestFailed("Write {0} starts {1} after start of read {2}. Minimum time is {3}".format(currentRow[0], formatTime(readToWrite), lastRow[0], formatTime(minWriteToRead))) lastRow = currentRow return TestSuceeded() + # TODO: Check if this test still is correct! @test def read_holds_dll_constraint_after_sref(connection): @@ -586,17 +592,17 @@ def read_holds_dll_constraint_after_sref(connection): WHERE PhaseName IN ('RD', 'RDA', 'SREF') ORDER BY PhaseBegin""" for bankNumber in range(dramconfig.numberOfBanks): - cursor.execute(query,{"bank": bankNumber}) + cursor.execute(query, {"bank": bankNumber}) lastRow = cursor.fetchone() for currentRow in cursor: - if(currentRow[2] in ["RD","RDA"] and lastRow[2] == 'SREF'): + if (currentRow[2] in ["RD", "RDA"] and lastRow[2] == 'SREF'): srefEndToRead = currentRow[1] - (lastRow[1] - dramconfig.clk) - if(srefEndToRead < dramconfig.tXSRDLL ): - return TestFailed("Read {0} starts {1} after end of sref {2}. Minimum time is {3}". - format(currentRow[0],formatTime(srefEndToRead),lastRow[0], formatTime(dramconfig.tXSRDLL))) + if (srefEndToRead < dramconfig.tXSRDLL): + return TestFailed("Read {0} starts {1} after end of sref {2}. Minimum time is {3}".format(currentRow[0], formatTime(srefEndToRead), lastRow[0], formatTime(dramconfig.tXSRDLL))) lastRow = currentRow return TestSuceeded() + @test def strict_transaction_order(connection): """Checks that all transactions are processed in the right order""" @@ -609,14 +615,14 @@ def strict_transaction_order(connection): for currentRow in cursor: transactions += str(currentRow[0]) + "," - if(transactions != ""): - if(dramconfig.scheduler == "FIFO_STRICT"): + if (transactions != ""): + if (dramconfig.scheduler == "FIFO_STRICT"): return TestFailed("Transactions {0} is/are not in Order ".format(transactions)) else: - return TestResult(True, "Transactions are not in Order, however this is okay since no FIFO_STRICT was choosen"); + return TestResult(True, "Transactions are not in Order, however this is okay since no FIFO_STRICT was choosen") return TestSuceeded() - # ----------- powerdown checks --------------------------------------- +# ----------- powerdown checks --------------------------------------- # @test # def sref_active_for_minimal_time(connection): @@ -625,7 +631,7 @@ def strict_transaction_order(connection): # cursor = connection.cursor() # cursor.execute("SELECT ID, PhaseEnd-clk-PhaseBegin FROM Phases, GeneralInfo WHERE PhaseName = 'SREF'") # for currentRow in cursor: -# if(currentRow[1] < dramconfig.tCKESR): +# if (currentRow[1] < dramconfig.tCKESR): # return TestFailed("SREF with ID {0} is {1} long. Minimal time in SREF is {2}".format(currentRow[0], formatTime(currentRow[1]), dramconfig.tCKESR)) # return TestSuceeded() @@ -636,48 +642,47 @@ def strict_transaction_order(connection): # cursor = connection.cursor() # cursor.execute("SELECT ID,PhaseName, PhaseEnd-PhaseBegin FROM Phases, GeneralInfo WHERE PhaseName IN ('PDNA', 'PDNP') ") # for currentRow in cursor: -# if(currentRow[2] < dramconfig.tCKE): +# if (currentRow[2] < dramconfig.tCKE): # return TestFailed("{0} with ID {1} is {2} long. Minimal time in SREF is {3}".format(currentRow[1], currentRow[0], formatTime(currentRow[2]), dramconfig.tCKE)) # return TestSuceeded() # -------------------------- interface methods -------------------- + def runTests(pathToTrace): - connection = sqlite3.connect(pathToTrace) - dramconfig.readConfigFromFiles(connection) + connection = sqlite3.connect(pathToTrace) + dramconfig.readConfigFromFiles(connection) - testResults = [] - numberOfFailedTest = 0 - print("================================") - print("RUNNING TEST ON {0}".format(pathToTrace)) + testResults = [] + numberOfFailedTest = 0 + print("================================") + print("RUNNING TEST ON {0}".format(pathToTrace)) - print("-----------------------------\n") + print("-----------------------------\n") - for test in tests: - testResult = test(connection) - testName = test.__name__.replace("_"," ") - testResults.append((testName, testResult.passed,testResult.message)) + for test in tests: + testResult = test(connection) + testName = test.__name__.replace("_", " ") + testResults.append((testName, testResult.passed, testResult.message)) + if (testResult.passed): + print("[passed] {0}".format(testName)) + else: + print("[failed] {0} failed. Message: {1}".format(testName, testResult.message)) + numberOfFailedTest = numberOfFailedTest + 1 - if(testResult.passed): - print("[passed] {0}".format(testName)) - else: - print("[failed] {0} failed. Message: {1}".format(testName, testResult.message)) - numberOfFailedTest = numberOfFailedTest + 1 + print("\n-----------------------------") - print("\n-----------------------------") - - if(numberOfFailedTest == 0): + if (numberOfFailedTest == 0): print("All tests passed") - else: - print("{0} of {1} tests passed".format(len(tests) - numberOfFailedTest,len(tests))) + else: + print("{0} of {1} tests passed".format(len(tests) - numberOfFailedTest, len(tests))) - print("================================") - connection.close() + print("================================") + connection.close() - return testResults + return testResults if __name__ == "__main__": sys.stdout = os.fdopen(sys.stdout.fileno(), 'w') - for i in range(1,len(sys.argv)): + for i in range(1, len(sys.argv)): runTests(sys.argv[i]) -