diff --git a/DRAMSys/library/src/controller/Command.cpp b/DRAMSys/library/src/controller/Command.cpp
index d1e9f0d4..976f2d28 100644
--- a/DRAMSys/library/src/controller/Command.cpp
+++ b/DRAMSys/library/src/controller/Command.cpp
@@ -44,7 +44,7 @@ using namespace DRAMPower;
 std::string commandToString(Command command)
 {  
     assert(command >= Command::NOP && command <= Command::SREFEX);
-    static std::array<std::string, 16> stringOfCommand =
+    static std::array<std::string, 18> stringOfCommand =
             {"NOP",
             "RD",
             "WR",
@@ -53,6 +53,8 @@ std::string commandToString(Command command)
             "PRE",
             "ACT",
             "REFB",
+            "PRESB",
+            "REFSB",
             "PREA",
             "REFA",
             "PDEA",
@@ -66,13 +68,13 @@ std::string commandToString(Command command)
 
 unsigned numberOfCommands()
 {
-    return 16;
+    return 18;
 }
 
 tlm_phase commandToPhase(Command command)
 {
     assert(command >= Command::NOP && command <= Command::SREFEX);
-    static std::array<tlm_phase, 16> phaseOfCommand =
+    static std::array<tlm_phase, 18> phaseOfCommand =
             {UNINITIALIZED_PHASE,
             BEGIN_RD,
             BEGIN_WR,
@@ -81,6 +83,8 @@ tlm_phase commandToPhase(Command command)
             BEGIN_PRE,
             BEGIN_ACT,
             BEGIN_REFB,
+            BEGIN_PRESB,
+            BEGIN_REFSB,
             BEGIN_PREA,
             BEGIN_REFA,
             BEGIN_PDNA,
@@ -95,7 +99,7 @@ tlm_phase commandToPhase(Command command)
 Command phaseToCommand(tlm_phase phase)
 {
     assert(phase >= BEGIN_RD && phase <= END_SREF);
-    static std::array<Command, 16> commandOfPhase =
+    static std::array<Command, 18> commandOfPhase =
             {Command::RD,
             Command::WR,
             Command::RDA,
@@ -103,6 +107,8 @@ Command phaseToCommand(tlm_phase phase)
             Command::PRE,
             Command::ACT,
             Command::REFB,
+            Command::PRESB,
+            Command::REFSB,
             Command::PREA,
             Command::REFA,
             Command::PDEA,
@@ -116,8 +122,9 @@ Command phaseToCommand(tlm_phase phase)
 
 MemCommand::cmds phaseToDRAMPowerCommand(tlm_phase phase)
 {
+    // TODO: add correct phases when DRAMPower supports DDR5 same bank refresh
     assert(phase >= BEGIN_RD && phase <= END_SREF);
-    static std::array<MemCommand::cmds, 16> phaseOfCommand =
+    static std::array<MemCommand::cmds, 18> phaseOfCommand =
             {MemCommand::RD,
             MemCommand::WR,
             MemCommand::RDA,
@@ -125,6 +132,8 @@ MemCommand::cmds phaseToDRAMPowerCommand(tlm_phase phase)
             MemCommand::PRE,
             MemCommand::ACT,
             MemCommand::REFB,
+            MemCommand::NOP,
+            MemCommand::NOP,
             MemCommand::PREA,
             MemCommand::REF,
             MemCommand::PDN_S_ACT,
@@ -144,7 +153,7 @@ bool phaseNeedsEnd(tlm_phase phase)
 tlm_phase getEndPhase(tlm_phase phase)
 {
     assert(phase >= BEGIN_RD && phase <= BEGIN_REFA);
-    return (phase + 15);
+    return (phase + 17);
 }
 
 bool isBankCommand(Command command)
@@ -153,6 +162,12 @@ bool isBankCommand(Command command)
     return (command <= Command::REFB);
 }
 
+bool isGroupCommand(Command command)
+{
+    assert(command >= Command::NOP && command <= Command::SREFEX);
+    return (command >= Command::PRESB && command <= Command::REFSB);
+}
+
 bool isRankCommand(Command command)
 {
     assert(command >= Command::NOP && command <= Command::SREFEX);
diff --git a/DRAMSys/library/src/controller/Command.h b/DRAMSys/library/src/controller/Command.h
index 3a511f38..a773fbb1 100644
--- a/DRAMSys/library/src/controller/Command.h
+++ b/DRAMSys/library/src/controller/Command.h
@@ -43,31 +43,35 @@
 #include "../common/third_party/DRAMPower/src/MemCommand.h"
 
 // DO NOT CHANGE THE ORDER!
-DECLARE_EXTENDED_PHASE(BEGIN_RD);   // 5
-DECLARE_EXTENDED_PHASE(BEGIN_WR);   // 6
-DECLARE_EXTENDED_PHASE(BEGIN_RDA);  // 7
-DECLARE_EXTENDED_PHASE(BEGIN_WRA);  // 8
-DECLARE_EXTENDED_PHASE(BEGIN_PRE);  // 9
-DECLARE_EXTENDED_PHASE(BEGIN_ACT);  // 10
-DECLARE_EXTENDED_PHASE(BEGIN_REFB); // 11
-DECLARE_EXTENDED_PHASE(BEGIN_PREA); // 12
-DECLARE_EXTENDED_PHASE(BEGIN_REFA); // 13
-DECLARE_EXTENDED_PHASE(BEGIN_PDNA); // 14
-DECLARE_EXTENDED_PHASE(END_PDNA);   // 15
-DECLARE_EXTENDED_PHASE(BEGIN_PDNP); // 16
-DECLARE_EXTENDED_PHASE(END_PDNP);   // 17
-DECLARE_EXTENDED_PHASE(BEGIN_SREF); // 18
-DECLARE_EXTENDED_PHASE(END_SREF);   // 19
+DECLARE_EXTENDED_PHASE(BEGIN_RD);    // 5
+DECLARE_EXTENDED_PHASE(BEGIN_WR);    // 6
+DECLARE_EXTENDED_PHASE(BEGIN_RDA);   // 7
+DECLARE_EXTENDED_PHASE(BEGIN_WRA);   // 8
+DECLARE_EXTENDED_PHASE(BEGIN_PRE);   // 9
+DECLARE_EXTENDED_PHASE(BEGIN_ACT);   // 10
+DECLARE_EXTENDED_PHASE(BEGIN_REFB);  // 11
+DECLARE_EXTENDED_PHASE(BEGIN_PRESB); // 12
+DECLARE_EXTENDED_PHASE(BEGIN_REFSB); // 13
+DECLARE_EXTENDED_PHASE(BEGIN_PREA);  // 14
+DECLARE_EXTENDED_PHASE(BEGIN_REFA);  // 15
+DECLARE_EXTENDED_PHASE(BEGIN_PDNA);  // 16
+DECLARE_EXTENDED_PHASE(END_PDNA);    // 17
+DECLARE_EXTENDED_PHASE(BEGIN_PDNP);  // 18
+DECLARE_EXTENDED_PHASE(END_PDNP);    // 19
+DECLARE_EXTENDED_PHASE(BEGIN_SREF);  // 20
+DECLARE_EXTENDED_PHASE(END_SREF);    // 21
 
-DECLARE_EXTENDED_PHASE(END_RD);     // 20
-DECLARE_EXTENDED_PHASE(END_WR);     // 21
-DECLARE_EXTENDED_PHASE(END_RDA);    // 22
-DECLARE_EXTENDED_PHASE(END_WRA);    // 23
-DECLARE_EXTENDED_PHASE(END_PRE);    // 24
-DECLARE_EXTENDED_PHASE(END_ACT);    // 25
-DECLARE_EXTENDED_PHASE(END_REFB);   // 26
-DECLARE_EXTENDED_PHASE(END_PREA);   // 27
-DECLARE_EXTENDED_PHASE(END_REFA);   // 28
+DECLARE_EXTENDED_PHASE(END_RD);      // 22
+DECLARE_EXTENDED_PHASE(END_WR);      // 23
+DECLARE_EXTENDED_PHASE(END_RDA);     // 24
+DECLARE_EXTENDED_PHASE(END_WRA);     // 25
+DECLARE_EXTENDED_PHASE(END_PRE);     // 26
+DECLARE_EXTENDED_PHASE(END_ACT);     // 27
+DECLARE_EXTENDED_PHASE(END_REFB);    // 28
+DECLARE_EXTENDED_PHASE(END_PRESB);   // 29
+DECLARE_EXTENDED_PHASE(END_REFSB);   // 30
+DECLARE_EXTENDED_PHASE(END_PREA);    // 31
+DECLARE_EXTENDED_PHASE(END_REFA);    // 32
 
 enum Command
 {
@@ -79,6 +83,8 @@ enum Command
     PRE,
     ACT,
     REFB,
+    PRESB,
+    REFSB,
     PREA,
     REFA,
     PDEA,
@@ -97,6 +103,7 @@ bool phaseNeedsEnd(tlm::tlm_phase);
 tlm::tlm_phase getEndPhase(tlm::tlm_phase);
 unsigned numberOfCommands();
 bool isBankCommand(Command);
+bool isGroupCommand(Command);
 bool isRankCommand(Command);
 bool isCasCommand(Command);
 bool isRasCommand(Command);
diff --git a/DRAMSys/library/src/simulation/dram/Dram.cpp b/DRAMSys/library/src/simulation/dram/Dram.cpp
index 8238195c..a18098be 100644
--- a/DRAMSys/library/src/simulation/dram/Dram.cpp
+++ b/DRAMSys/library/src/simulation/dram/Dram.cpp
@@ -142,7 +142,7 @@ void Dram::reportPower()
 tlm_sync_enum Dram::nb_transport_fw(tlm_generic_payload &payload,
                                            tlm_phase &phase, sc_time &)
 {
-    assert(phase >= 5 && phase <= 19);
+    assert(phase >= 5 && phase <= 21);
 
     if (Configuration::getInstance().powerAnalysis)
     {