From d7ed07405605331980c93ff7b5e86dd3b0a561c4 Mon Sep 17 00:00:00 2001 From: scorrea Date: Wed, 8 Apr 2020 00:27:06 +0200 Subject: [PATCH] json files added --- .../configs/simulator/ddr3-single-device.json | 1 + .../resources/configs/simulator/ddr3.json | 1 + .../configs/simulator/ddr3_boot_linux.json | 1 + .../resources/configs/simulator/ddr3_ecc.json | 1 + .../configs/simulator/ddr3_gem5_se.json | 1 + .../resources/configs/simulator/ddr4.json | 1 + .../resources/configs/simulator/hbm2.json | 1 + .../resources/configs/simulator/lpddr4.json | 1 + .../resources/configs/simulator/orgr.json | 1 + .../simulator/orgr_4b_opt_timings_ddr3.json | 1 + .../simulator/orgr_4b_std_timings_ddr3.json | 1 + .../simulator/orgr_8b_opt_timings_ddr3.json | 1 + .../simulator/orgr_8b_std_timings_ddr3.json | 1 + .../resources/configs/simulator/orgr_ddr4.json | 1 + .../configs/simulator/rgrsimcfg-gem5-fs.json | 1 + .../configs/simulator/rgrsimcfg-gem5-se.json | 1 + .../resources/configs/simulator/rgrsimcfg.json | 1 + .../resources/configs/simulator/sms.json | 1 + .../resources/configs/simulator/wideio.json | 1 + .../resources/configs/simulator/wideio_ecc.json | 1 + .../configs/simulator/wideio_thermal.json | 1 + run | 3 +++ xml_json.py | 17 +++++++++++++++++ 23 files changed, 41 insertions(+) create mode 100644 DRAMSys/library/resources/configs/simulator/ddr3-single-device.json create mode 100644 DRAMSys/library/resources/configs/simulator/ddr3.json create mode 100644 DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.json create mode 100644 DRAMSys/library/resources/configs/simulator/ddr3_ecc.json create mode 100644 DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json create mode 100644 DRAMSys/library/resources/configs/simulator/ddr4.json create mode 100644 DRAMSys/library/resources/configs/simulator/hbm2.json create mode 100644 DRAMSys/library/resources/configs/simulator/lpddr4.json create mode 100644 DRAMSys/library/resources/configs/simulator/orgr.json create mode 100644 DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.json create mode 100644 DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.json create mode 100644 DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.json create mode 100644 DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.json create mode 100644 DRAMSys/library/resources/configs/simulator/orgr_ddr4.json create mode 100644 DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-fs.json create mode 100644 DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-se.json create mode 100644 DRAMSys/library/resources/configs/simulator/rgrsimcfg.json create mode 100644 DRAMSys/library/resources/configs/simulator/sms.json create mode 100644 DRAMSys/library/resources/configs/simulator/wideio.json create mode 100644 DRAMSys/library/resources/configs/simulator/wideio_ecc.json create mode 100644 DRAMSys/library/resources/configs/simulator/wideio_thermal.json create mode 100755 run create mode 100644 xml_json.py diff --git a/DRAMSys/library/resources/configs/simulator/ddr3-single-device.json b/DRAMSys/library/resources/configs/simulator/ddr3-single-device.json new file mode 100644 index 00000000..aa79c674 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/ddr3-single-device.json @@ -0,0 +1 @@ +{"simconfig": {"SimulationName": {"@value": "ddr3_single_dev"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "1"}, "CheckTLM2Protocol": {"@value": "0"}, "AddressOffset": {"@value": "0"}, "ECCControllerMode": {"@value": "Disabled"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": ""}, "StoreMode": {"@value": "NoStorage"}, "UseMalloc": {"@value": "0"}}} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/ddr3.json b/DRAMSys/library/resources/configs/simulator/ddr3.json new file mode 100644 index 00000000..9992f9db --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/ddr3.json @@ -0,0 +1 @@ +{"simconfig": {"SimulationName": {"@value": "ddr3"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "0"}, "EnableWindowing": {"@value": "0"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "8"}, "CheckTLM2Protocol": {"@value": "0"}, "AddressOffset": {"@value": "0"}, "ECCControllerMode": {"@value": "Disabled"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": ""}, "StoreMode": {"@value": "NoStorage"}, "UseMalloc": {"@value": "0"}}} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.json b/DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.json new file mode 100644 index 00000000..7de9abd2 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/ddr3_boot_linux.json @@ -0,0 +1 @@ +{"simconfig": {"SimulationName": {"@value": "ddr3"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "8"}, "CheckTLM2Protocol": {"@value": "0"}, "ECCControllerMode": {"@value": "Disabled"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": ""}, "StoreMode": {"@value": "Store"}, "AddressOffset": {"@value": "2147483648"}, "UseMalloc": {"@value": "1"}}} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/ddr3_ecc.json b/DRAMSys/library/resources/configs/simulator/ddr3_ecc.json new file mode 100644 index 00000000..42026b4c --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/ddr3_ecc.json @@ -0,0 +1 @@ +{"simconfig": {"SimulationName": {"@value": "ddr3"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "8"}, "CheckTLM2Protocol": {"@value": "0"}, "AddressOffset": {"@value": "0"}, "ECCControllerMode": {"@value": "Hamming"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": ""}, "StoreMode": {"@value": "ErrorModel"}, "UseMalloc": {"@value": "0"}}} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json b/DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json new file mode 100644 index 00000000..cc1fc350 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/ddr3_gem5_se.json @@ -0,0 +1 @@ +{"simconfig": {"SimulationName": {"@value": "ddr3"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "8"}, "CheckTLM2Protocol": {"@value": "0"}, "AddressOffset": {"@value": "0"}, "ECCControllerMode": {"@value": "Disabled"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": ""}, "StoreMode": {"@value": "Store"}, "UseMalloc": {"@value": "0"}}} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/ddr4.json b/DRAMSys/library/resources/configs/simulator/ddr4.json new file mode 100644 index 00000000..43f6024d --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/ddr4.json @@ -0,0 +1 @@ +{"simconfig": {"SimulationName": {"@value": "ddr4"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "0"}, "EnableWindowing": {"@value": "0"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "8"}, "CheckTLM2Protocol": {"@value": "0"}, "AddressOffset": {"@value": "0"}, "ECCControllerMode": {"@value": "Disabled"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": ""}, "StoreMode": {"@value": "NoStorage"}, "UseMalloc": {"@value": "0"}}} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/hbm2.json b/DRAMSys/library/resources/configs/simulator/hbm2.json new file mode 100644 index 00000000..2d721f40 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/hbm2.json @@ -0,0 +1 @@ +{"simconfig": {"SimulationName": {"@value": "hbm2"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "0"}, "EnableWindowing": {"@value": "0"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "1"}, "CheckTLM2Protocol": {"@value": "0"}, "AddressOffset": {"@value": "0"}, "ECCControllerMode": {"@value": "Disabled"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": ""}, "StoreMode": {"@value": "NoStorage"}, "UseMalloc": {"@value": "0"}}} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/lpddr4.json b/DRAMSys/library/resources/configs/simulator/lpddr4.json new file mode 100644 index 00000000..599c23b3 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/lpddr4.json @@ -0,0 +1 @@ +{"simconfig": {"SimulationName": {"@value": "lpddr4"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "0"}, "EnableWindowing": {"@value": "0"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "1"}, "CheckTLM2Protocol": {"@value": "0"}, "AddressOffset": {"@value": "0"}, "ECCControllerMode": {"@value": "Disabled"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": ""}, "StoreMode": {"@value": "NoStorage"}, "UseMalloc": {"@value": "0"}}} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/orgr.json b/DRAMSys/library/resources/configs/simulator/orgr.json new file mode 100644 index 00000000..d7818d14 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/orgr.json @@ -0,0 +1 @@ +{"simconfig": {"SimulationName": {"@value": "orgr"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "NumberOfMemChannels": {"@value": "1"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "4"}, "ControllerCoreRefDisable": {"@value": "0"}, "ControllerCoreRGR": [{"@value": "1"}, {"@value": "1"}], "ControllerCoreRefNumARCmdsIntREFI": {"@value": "8192"}, "ControllerCoreRGRtRASBInClkCycles": {"@value": "20"}, "ControllerCoreRGRtRRDB_LInClkCycles": {"@value": "6"}, "ControllerCoreRGRtRRDB_SInClkCycles": {"@value": "6"}, "ControllerCoreRGRtRPBInClkCycles": {"@value": "8"}, "ControllerCoreRGRtRCBInClkCycles": {"@value": "27"}, "ControllerCoreRGRtFAWBInClkCycles": {"@value": "27"}, "ControllerCoreRGRB0": {"@value": "1"}, "ControllerCoreRGRB1": {"@value": "1"}, "ControllerCoreRGRB2": {"@value": "1"}, "ControllerCoreRGRB3": {"@value": "1"}, "ControllerCoreRGRB4": {"@value": "1"}, "ControllerCoreRGRB5": {"@value": "1"}, "ControllerCoreRGRB6": {"@value": "1"}, "ControllerCoreRGRB7": {"@value": "1"}, "ControllerCoreRGRB8": {"@value": "0"}, "ControllerCoreRGRB9": {"@value": "0"}, "ControllerCoreRGRB10": {"@value": "0"}, "ControllerCoreRGRB11": {"@value": "0"}, "ControllerCoreRGRB12": {"@value": "0"}, "ControllerCoreRGRB13": {"@value": "0"}, "ControllerCoreRGRB14": {"@value": "0"}, "ControllerCoreRGRB15": {"@value": "0"}, "UseMalloc": {"@value": "0"}}} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.json b/DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.json new file mode 100644 index 00000000..8dd11597 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/orgr_4b_opt_timings_ddr3.json @@ -0,0 +1 @@ +{"simconfig": {"SimulationName": {"@value": "orgr_4b_opt_timings"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "NumberOfMemChannels": {"@value": "1"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "4"}, "ControllerCoreRefDisable": {"@value": "0"}, "ControllerCoreRGR": {"@value": "1"}, "ControllerCoreRefNumARCmdsIntREFI": {"@value": "8192"}, "ControllerCoreRGRtRASBInClkCycles": {"@value": "11"}, "ControllerCoreRGRtRRDB_LInClkCycles": {"@value": "2"}, "ControllerCoreRGRtRRDB_SInClkCycles": {"@value": "2"}, "ControllerCoreRGRtRPBInClkCycles": {"@value": "5"}, "ControllerCoreRGRtRCBInClkCycles": {"@value": "16"}, "ControllerCoreRGRtFAWBInClkCycles": {"@value": "0"}, "ControllerCoreRGRB0": {"@value": "1"}, "ControllerCoreRGRB1": {"@value": "1"}, "ControllerCoreRGRB2": {"@value": "1"}, "ControllerCoreRGRB3": {"@value": "1"}, "ControllerCoreRGRB4": {"@value": "0"}, "ControllerCoreRGRB5": {"@value": "0"}, "ControllerCoreRGRB6": {"@value": "0"}, "ControllerCoreRGRB7": {"@value": "0"}, "ControllerCoreRGRB8": {"@value": "0"}, "ControllerCoreRGRB9": {"@value": "0"}, "ControllerCoreRGRB10": {"@value": "0"}, "ControllerCoreRGRB11": {"@value": "0"}, "ControllerCoreRGRB12": {"@value": "0"}, "ControllerCoreRGRB13": {"@value": "0"}, "ControllerCoreRGRB14": {"@value": "0"}, "ControllerCoreRGRB15": {"@value": "0"}, "UseMalloc": {"@value": "0"}}} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.json b/DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.json new file mode 100644 index 00000000..cf291096 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/orgr_4b_std_timings_ddr3.json @@ -0,0 +1 @@ +{"simconfig": {"SimulationName": {"@value": "orgr_4b_std_timings"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "NumberOfMemChannels": {"@value": "1"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "4"}, "ControllerCoreRefDisable": {"@value": "0"}, "ControllerCoreRGR": [{"@value": "1"}, {"@value": "1"}], "ControllerCoreRefNumARCmdsIntREFI": {"@value": "8192"}, "ControllerCoreRGRtRASBInClkCycles": {"@value": "20"}, "ControllerCoreRGRtRRDB_LInClkCycles": {"@value": "6"}, "ControllerCoreRGRtRRDB_SInClkCycles": {"@value": "6"}, "ControllerCoreRGRtRPBInClkCycles": {"@value": "8"}, "ControllerCoreRGRtRCBInClkCycles": {"@value": "27"}, "ControllerCoreRGRtFAWBInClkCycles": {"@value": "27"}, "ControllerCoreRGRB0": {"@value": "1"}, "ControllerCoreRGRB1": {"@value": "1"}, "ControllerCoreRGRB2": {"@value": "1"}, "ControllerCoreRGRB3": {"@value": "1"}, "ControllerCoreRGRB4": {"@value": "0"}, "ControllerCoreRGRB5": {"@value": "0"}, "ControllerCoreRGRB6": {"@value": "0"}, "ControllerCoreRGRB7": {"@value": "0"}, "ControllerCoreRGRB8": {"@value": "0"}, "ControllerCoreRGRB9": {"@value": "0"}, "ControllerCoreRGRB10": {"@value": "0"}, "ControllerCoreRGRB11": {"@value": "0"}, "ControllerCoreRGRB12": {"@value": "0"}, "ControllerCoreRGRB13": {"@value": "0"}, "ControllerCoreRGRB14": {"@value": "0"}, "ControllerCoreRGRB15": {"@value": "0"}, "UseMalloc": {"@value": "0"}}} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.json b/DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.json new file mode 100644 index 00000000..a4850ba6 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/orgr_8b_opt_timings_ddr3.json @@ -0,0 +1 @@ +{"simconfig": {"SimulationName": {"@value": "orgr_8b_opt_timings"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "NumberOfMemChannels": {"@value": "1"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "4"}, "ControllerCoreRefDisable": {"@value": "0"}, "ControllerCoreRGR": {"@value": "1"}, "ControllerCoreRefNumARCmdsIntREFI": {"@value": "8192"}, "ControllerCoreRGRtRASBInClkCycles": {"@value": "11"}, "ControllerCoreRGRtRRDB_LInClkCycles": {"@value": "2"}, "ControllerCoreRGRtRRDB_SInClkCycles": {"@value": "2"}, "ControllerCoreRGRtRPBInClkCycles": {"@value": "5"}, "ControllerCoreRGRtRCBInClkCycles": {"@value": "16"}, "ControllerCoreRGRtFAWBInClkCycles": {"@value": "0"}, "ControllerCoreRGRB0": {"@value": "1"}, "ControllerCoreRGRB1": {"@value": "1"}, "ControllerCoreRGRB2": {"@value": "1"}, "ControllerCoreRGRB3": {"@value": "1"}, "ControllerCoreRGRB4": {"@value": "1"}, "ControllerCoreRGRB5": {"@value": "1"}, "ControllerCoreRGRB6": {"@value": "1"}, "ControllerCoreRGRB7": {"@value": "1"}, "ControllerCoreRGRB8": {"@value": "0"}, "ControllerCoreRGRB9": {"@value": "0"}, "ControllerCoreRGRB10": {"@value": "0"}, "ControllerCoreRGRB11": {"@value": "0"}, "ControllerCoreRGRB12": {"@value": "0"}, "ControllerCoreRGRB13": {"@value": "0"}, "ControllerCoreRGRB14": {"@value": "0"}, "ControllerCoreRGRB15": {"@value": "0"}, "UseMalloc": {"@value": "0"}}} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.json b/DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.json new file mode 100644 index 00000000..6131bec2 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/orgr_8b_std_timings_ddr3.json @@ -0,0 +1 @@ +{"simconfig": {"SimulationName": {"@value": "orgr_8b_std_timings_ddr3"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "NumberOfMemChannels": {"@value": "1"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "4"}, "ControllerCoreRefDisable": {"@value": "0"}, "ControllerCoreRGR": [{"@value": "1"}, {"@value": "1"}], "ControllerCoreRefNumARCmdsIntREFI": {"@value": "8192"}, "ControllerCoreRGRtRASBInClkCycles": {"@value": "20"}, "ControllerCoreRGRtRRDB_LInClkCycles": {"@value": "6"}, "ControllerCoreRGRtRRDB_SInClkCycles": {"@value": "6"}, "ControllerCoreRGRtRPBInClkCycles": {"@value": "8"}, "ControllerCoreRGRtRCBInClkCycles": {"@value": "27"}, "ControllerCoreRGRtFAWBInClkCycles": {"@value": "27"}, "ControllerCoreRGRB0": {"@value": "1"}, "ControllerCoreRGRB1": {"@value": "1"}, "ControllerCoreRGRB2": {"@value": "1"}, "ControllerCoreRGRB3": {"@value": "1"}, "ControllerCoreRGRB4": {"@value": "1"}, "ControllerCoreRGRB5": {"@value": "1"}, "ControllerCoreRGRB6": {"@value": "1"}, "ControllerCoreRGRB7": {"@value": "1"}, "ControllerCoreRGRB8": {"@value": "0"}, "ControllerCoreRGRB9": {"@value": "0"}, "ControllerCoreRGRB10": {"@value": "0"}, "ControllerCoreRGRB11": {"@value": "0"}, "ControllerCoreRGRB12": {"@value": "0"}, "ControllerCoreRGRB13": {"@value": "0"}, "ControllerCoreRGRB14": {"@value": "0"}, "ControllerCoreRGRB15": {"@value": "0"}, "UseMalloc": {"@value": "0"}}} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/orgr_ddr4.json b/DRAMSys/library/resources/configs/simulator/orgr_ddr4.json new file mode 100644 index 00000000..fbdb4071 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/orgr_ddr4.json @@ -0,0 +1 @@ +{"simconfig": {"SimulationName": {"@value": "orgr_ddr4"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "4"}, "CheckTLM2Protocol": {"@value": "0"}, "AddressOffset": {"@value": "0"}, "ECCControllerMode": {"@value": "Disabled"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": ""}, "StoreMode": {"@value": "NoStorage"}, "UseMalloc": {"@value": "0"}}} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-fs.json b/DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-fs.json new file mode 100644 index 00000000..9491c878 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-fs.json @@ -0,0 +1 @@ +{"simconfig": {"SimulationName": {"@value": "rgr"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "0"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "4"}, "CheckTLM2Protocol": {"@value": "0"}, "AddressOffset": {"@value": "2147483648"}, "ECCControllerMode": {"@value": "Disabled"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": ""}, "StoreMode": {"@value": "Store"}, "UseMalloc": {"@value": "1"}}} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-se.json b/DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-se.json new file mode 100644 index 00000000..0c1aceca --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/rgrsimcfg-gem5-se.json @@ -0,0 +1 @@ +{"simconfig": {"SimulationName": {"@value": "rgr"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "4"}, "CheckTLM2Protocol": {"@value": "0"}, "AddressOffset": {"@value": "0"}, "ECCControllerMode": {"@value": "Disabled"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": ""}, "StoreMode": {"@value": "Store"}, "UseMalloc": {"@value": "0"}}} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/rgrsimcfg.json b/DRAMSys/library/resources/configs/simulator/rgrsimcfg.json new file mode 100644 index 00000000..7f2324ca --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/rgrsimcfg.json @@ -0,0 +1 @@ +{"simconfig": {"SimulationName": {"@value": "rgr"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "4"}, "CheckTLM2Protocol": {"@value": "0"}, "AddressOffset": {"@value": "0"}, "ECCControllerMode": {"@value": "Disabled"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": ""}, "StoreMode": {"@value": "NoStorage"}, "UseMalloc": {"@value": "0"}}} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/sms.json b/DRAMSys/library/resources/configs/simulator/sms.json new file mode 100644 index 00000000..e78cbf32 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/sms.json @@ -0,0 +1 @@ +{"simconfig": {"SimulationName": {"@value": "sms"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "4"}, "NumberOfDevicesOnDIMM": {"@value": "1"}, "CheckTLM2Protocol": {"@value": "0"}, "UseMalloc": {"@value": "0"}}} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/wideio.json b/DRAMSys/library/resources/configs/simulator/wideio.json new file mode 100644 index 00000000..c0c3bc1d --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/wideio.json @@ -0,0 +1 @@ +{"simconfig": {"SimulationName": {"@value": "wideio"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "4"}, "NumberOfDevicesOnDIMM": {"@value": "1"}, "CheckTLM2Protocol": {"@value": "0"}, "ECCControllerMode": {"@value": "Disabled"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": "../../DRAMSys/library/resources/error/wideio.csv"}, "StoreMode": {"@value": "NoStorage"}, "UseMalloc": {"@value": "0"}}} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/wideio_ecc.json b/DRAMSys/library/resources/configs/simulator/wideio_ecc.json new file mode 100644 index 00000000..a897ca72 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/wideio_ecc.json @@ -0,0 +1 @@ +{"simconfig": {"SimulationName": {"@value": "wideio_ecc"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "0"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "1"}, "CheckTLM2Protocol": {"@value": "0"}, "ECCControllerMode": {"@value": "Hamming"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": "../../DRAMSys/library/resources/error/wideio.csv"}, "StoreMode": {"@value": "ErrorModel"}, "UseMalloc": {"@value": "0"}}} \ No newline at end of file diff --git a/DRAMSys/library/resources/configs/simulator/wideio_thermal.json b/DRAMSys/library/resources/configs/simulator/wideio_thermal.json new file mode 100644 index 00000000..8de132d8 --- /dev/null +++ b/DRAMSys/library/resources/configs/simulator/wideio_thermal.json @@ -0,0 +1 @@ +{"simconfig": {"SimulationName": {"@value": "wideio"}, "Debug": {"@value": "0"}, "DatabaseRecording": {"@value": "1"}, "PowerAnalysis": {"@value": "1"}, "EnableWindowing": {"@value": "1"}, "WindowSize": {"@value": "1000"}, "ThermalSimulation": {"@value": "1"}, "SimulationProgressBar": {"@value": "1"}, "NumberOfMemChannels": {"@value": "1"}, "NumberOfDevicesOnDIMM": {"@value": "1"}, "CheckTLM2Protocol": {"@value": "0"}, "ECCControllerMode": {"@value": "Disabled"}, "ErrorChipSeed": {"@value": "42"}, "ErrorCSVFile": {"@value": "../../DRAMSys/library/resources/error/wideio.csv"}, "StoreMode": {"@value": "NoStorage"}, "UseMalloc": {"@value": "0"}}} \ No newline at end of file diff --git a/run b/run new file mode 100755 index 00000000..59b099af --- /dev/null +++ b/run @@ -0,0 +1,3 @@ +#!/usr/bin/env bash +export LD_LIBRARY_PATH=${LD_LIBRARY_PATH:+${LD_LIBRARY_PATH}:}./libraries +build/simulator/DRAMSys $1 diff --git a/xml_json.py b/xml_json.py new file mode 100644 index 00000000..47014e5c --- /dev/null +++ b/xml_json.py @@ -0,0 +1,17 @@ +import xmltodict +import json +from pathlib import Path + + + + +basepath= Path('DRAMSys/library/resources/configs/simulator') +for path in basepath.iterdir(): + if path.is_file(): + filename=str(path) + if filename.endswith('.xml'): + # if os.stat(path).st_size != 0: #check if it is empty + with open(path, "r") as in_file: + xml = in_file.read() + with open(filename.replace(".xml",".json"), 'w') as out_file: + json.dump(xmltodict.parse(xml), out_file) \ No newline at end of file