diff --git a/DRAMSys/tests/tests.pri b/DRAMSys/tests/tests.pri
index b264d78f..0224ef01 100644
--- a/DRAMSys/tests/tests.pri
+++ b/DRAMSys/tests/tests.pri
@@ -17,11 +17,12 @@ OTHER_FILES += tests/error/fr_fcfs.xml
 OTHER_FILES += tests/error/generateErrorTest.pl
 OTHER_FILES += tests/error/WideIO.xml
 
-# evaluation test
-OTHER_FILES += tests/evaluation/sim-batch.xml
-OTHER_FILES += tests/evaluation/fifoStrict.xml
-OTHER_FILES += tests/evaluation/test.pl
+# timing compliance test
+OTHER_FILES += tests/timing_compliance/sim-batch.xml
+OTHER_FILES += tests/timing_compliance/fifoStrict.xml
+OTHER_FILES += tests/timing_compliance/test.pl
 
 # python unit tests
 OTHER_FILES += tests/unit/unit_test.py
 OTHER_FILES += tests/unit/mem_util.py
+
diff --git a/DRAMSys/tests/evaluation/fifoStrict.xml b/DRAMSys/tests/timing_compliance/fifoStrict.xml
similarity index 86%
rename from DRAMSys/tests/evaluation/fifoStrict.xml
rename to DRAMSys/tests/timing_compliance/fifoStrict.xml
index 270d9037..46b65ad7 100644
--- a/DRAMSys/tests/evaluation/fifoStrict.xml
+++ b/DRAMSys/tests/timing_compliance/fifoStrict.xml
@@ -1,10 +1,10 @@
 <memconfig>
-    <BankwiseLogic value="0"/>
+    <BankwiseLogic value="1"/>
     <OpenPagePolicy value="1" />
     <MaxNrOfTransactions value="8" />
     <Scheduler value="FIFO_STRICT" />
     <Capsize value="5" />
-    <PowerDownMode value="NoPowerDown" />
+    <PowerDownMode value="TimeoutSREF" />
     <PowerDownTimeout value="100" />
     <!-- Error Modelling -->
     <ErrorChipSeed value="42" />
diff --git a/DRAMSys/tests/evaluation/sim-batch.xml b/DRAMSys/tests/timing_compliance/sim-batch.xml
similarity index 87%
rename from DRAMSys/tests/evaluation/sim-batch.xml
rename to DRAMSys/tests/timing_compliance/sim-batch.xml
index b68f43b1..acae2530 100644
--- a/DRAMSys/tests/evaluation/sim-batch.xml
+++ b/DRAMSys/tests/timing_compliance/sim-batch.xml
@@ -3,7 +3,7 @@
     <simconfig>
         <Debug value="0" />
         <DatabaseRecording value="1" />
-        <PowerAnalysis value="1" />
+        <PowerAnalysis value="0" />
         <EnableWindowing value = "0" />
         <WindowSize value="1000" />
         <NumberOfTracePlayers value="1"/>
@@ -39,12 +39,12 @@
     </addressmappings>
 
     <memconfigs>
-        <memconfig src="../../DRAMSys/tests/evaluation/fifoStrict.xml"/>
+        <memconfig src="../../DRAMSys/tests/timing_compliance/fifoStrict.xml"/>
     </memconfigs>
 
     <tracesetups>
-        <tracesetup id="evaluation_test_fifoStrict">
-            <device clkMhz="200">mediabench-c-ray-1.1_32.stl</device>
+        <tracesetup id="timing_compliance_test_fifoStrict">
+            <device clkMhz="200">chstone-jpeg_32.stl</device>
         </tracesetup>
     </tracesetups>
 
diff --git a/DRAMSys/tests/evaluation/test.pl b/DRAMSys/tests/timing_compliance/test.pl
similarity index 77%
rename from DRAMSys/tests/evaluation/test.pl
rename to DRAMSys/tests/timing_compliance/test.pl
index 10968545..cd18a4e9 100644
--- a/DRAMSys/tests/evaluation/test.pl
+++ b/DRAMSys/tests/timing_compliance/test.pl
@@ -33,7 +33,7 @@
 #    Matthias Jung, Felipe S. Prado
 #
 
-# Test Evaluation:
+# Test Timing Compliance:
 # This test runs the simulation with standard configuration
 
 # Run Simulation:
@@ -53,40 +53,39 @@ chdir("../../../build/simulator/");
 
 foreach (@powerDownModes)
 {
-    system("sed -i '" . $powerAnalysisLine . "s^.*^        <PowerAnalysis value=\"1\" />^' ../../DRAMSys/tests/evaluation/sim-batch.xml");
-    system("sed -i '" . $bankwiseLogicLine . "s^.*^    <BankwiseLogic value=\"0\"/>^' ../../DRAMSys/tests/evaluation/fifoStrict.xml");
-    system("sed -i '" . $powerDownModeLine . "s^.*^    <PowerDownMode value=\"$_\" />^' ../../DRAMSys/tests/evaluation/fifoStrict.xml");   
+    system("sed -i '" . $powerAnalysisLine . "s^.*^        <PowerAnalysis value=\"1\" />^' ../../DRAMSys/tests/timing_compliance/sim-batch.xml");
+    system("sed -i '" . $bankwiseLogicLine . "s^.*^    <BankwiseLogic value=\"0\"/>^' ../../DRAMSys/tests/timing_compliance/fifoStrict.xml");
+    system("sed -i '" . $powerDownModeLine . "s^.*^    <PowerDownMode value=\"$_\" />^' ../../DRAMSys/tests/timing_compliance/fifoStrict.xml");
 
-    `./dramSys ../../DRAMSys/tests/evaluation/sim-batch.xml`;
+    `./dramSys ../../DRAMSys/tests/timing_compliance/sim-batch.xml`;
 
-    @files = `ls sim-batch/evaluation_test_fifoStrict_channel*.tdb`;
+    @files = `ls sim-batch/timing_compliance_test_fifoStrict_channel*.tdb`;
     chomp @files;
 
     foreach (@files)
     {
-        `python3.5 ../../DRAMSys/analyzer/scripts/tests.py $_ > ../../DRAMSys/tests/evaluation/output.txt`;
+        `python3.5 ../../DRAMSys/analyzer/scripts/tests.py $_ > ../../DRAMSys/tests/timing_compliance/output.txt`;
 
-        if("All tests passed\n" ne `grep "All tests passed" ../../DRAMSys/tests/evaluation/output.txt`)
-	{
+        if("All tests passed\n" ne `grep "All tests passed" ../../DRAMSys/tests/timing_compliance/output.txt`)
+        {
             exit -1;
-	}
+        }
     }
 
-    system("sed -i '" . $powerAnalysisLine . "s^.*^        <PowerAnalysis value=\"0\" />^' ../../DRAMSys/tests/evaluation/sim-batch.xml");
-    system("sed -i '" . $bankwiseLogicLine . "s^.*^    <BankwiseLogic value=\"1\"/>^' ../../DRAMSys/tests/evaluation/fifoStrict.xml");
+    system("sed -i '" . $powerAnalysisLine . "s^.*^        <PowerAnalysis value=\"0\" />^' ../../DRAMSys/tests/timing_compliance/sim-batch.xml");
+    system("sed -i '" . $bankwiseLogicLine . "s^.*^    <BankwiseLogic value=\"1\"/>^' ../../DRAMSys/tests/timing_compliance/fifoStrict.xml");
 
-    `./dramSys ../../DRAMSys/tests/evaluation/sim-batch.xml`;
+    `./dramSys ../../DRAMSys/tests/timing_compliance/sim-batch.xml`;
 
     foreach (@files)
     {
-        `python3.5 ../../DRAMSys/analyzer/scripts/tests.py $_ > ../../DRAMSys/tests/evaluation/output.txt`;
+        `python3.5 ../../DRAMSys/analyzer/scripts/tests.py $_ > ../../DRAMSys/tests/timing_compliance/output.txt`;
 
-        if("All tests passed\n" ne `grep "All tests passed" ../../DRAMSys/tests/evaluation/output.txt`)
-	{
+        if("All tests passed\n" ne `grep "All tests passed" ../../DRAMSys/tests/timing_compliance/output.txt`)
+        {
             exit -1;
-	}
+        }
     }
-
 }
 exit 0;